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UC1526A UC2526A UC3526A
Regulating Pulse Width Modulator
FEATURES
* * * * * * * * * * * * Reduced Supply Current Oscillator Frequency to 600kHz Precision Band-Gap Reference 7 to 35V Operation Dual 200mA Source/Sink Outputs Minimum Output Cross-Conduction Double-Pulse Suppression Logic Under-Voltage Lockout Programmable Soft-Start Thermal Shutdown TTL/CMOS Compatible Logic Ports 5 Volt Operation (VIN = VC = VREF = 5.0V)
DESCRIPTION
The UC1526A Series are improved-performance pulse-width modulator circuits intended for direct replacement of equivalent non- "A" versions in all applications. Higher frequency operation has been enhanced by several significant improvements including: a more accurate oscillator with less minimum dead time, reduced circuit delays (particularly in current limiting), and an improved output stage with negligible cross-conduction current. Additional improvements include the incorporation of a precision, band-gap reference generator, reduced overall supply current, and the addition of thermal shutdown protection. Along with these improvements, the UC1526A Series retains the protective features of under-voltage lockout, soft-start, digital current limiting, double pulse suppression logic, and adjustable deadtime. For ease of interfacing, all digital control ports are TTL compatible with active low logic. Five volt (5V) operation is possible for "logic level" applications by connecting VIN, VC and VREF to a precision 5V input supply. Consult factory for additional information.
BLOCK DIAGRAM
6/93
UC1526A UC2526A UC3526A ABSOLUTE MAXIMUM RATINGS (Note 1, 2)
Input Voltage (+VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +40V Collector Supply Voltage (+VC) . . . . . . . . . . . . . . . . . . . . . +40V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.5V Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +VIN Source/Sink Load Current (each output) . . . . . . . . . . . . 200mA Reference Load Current . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Logic Sink Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA Power Dissipation at TA = +25C (Note 2) . . . . . . . . . 1000mW Power Dissipation at TC = +25C (Note 2) . . . . . . . . . . 3000mW Operating Junction Temperature . . . . . . . . . . . . . . . . . . +150C Storage Temperature Range . . . . . . . . . . . . . . -65C to +150C Lead Temperature (soldering, 10 seconds) . . . . . . . . . . +300C
RECOMMENDED OPERATING CONDITIONS
(Note 3) Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V to +35V Collector Supply Voltage . . . . . . . . . . . . . . . . . . +4.5V to +35V Sink/Source Load Current (each output) . . . . . . . . 0 to 100mA Reference Load Current . . . . . . . . . . . . . . . . . . . . . . 0 to 20mA Oscillator Frequency Range . . . . . . . . . . . . . . . . 1Hz to 600kHz Oscillator Timing Resistor. . . . . . . . . . . . . . . . . . . 2k to 150k Oscillator Timing Capacitor. . . . . . . . . . . . . . . . . 400pF to 20F Available Deadtime Range at 40kHz . . . . . . . . . . . . 1% to 50% Operating Ambient Temperature Range UC1526A. . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C UC2526A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25C to +85C UC3526A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Note 3: Range over which the device is functional and parameter limits are guaranteed.
Note 1: Values beyond which damage may occur. Note 2: Consult packaging Section of Databook for thermal limitations and considerations of package.
CONNECTION DIAGRAMS
DIL-18, SOIC-18 (TOP VIEW) J or N Package, DW Package PLCC-20, LCC-20 (TOP VIEW) Q and L Packages
PACKAGE PIN FUNCTION FUNCTION PIN
N/C +ERROR -ERROR COMP. CSS RESET - CURRENT SENSE + CURRENT SENSE SHUTDOWN RTIMING CT RD SYNC OUTPUT A VC N/C GROUND OUTPUT B +VIN VREF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
2
UC1526A UC2526A UC3526A ELECTRICAL CHARACTERISTICS: +VIN = 15V, and over operating ambient temperature, unless otherwise specified TA = TJ.
UC1526A / UC2526A PARAMETER Reference Section (Note 4) Output Voltage Line Regulation Load Regulation Temperature Stability Total Output Voltage Range Short Circuit Current Under-Voltage Lockout RESET Output Voltage Oscillator Section (Note 6) Initial Accuracy Voltage Stability Temperature Stability Minimum Frequency Maximum Frequency Sawtooth Peak Voltage Sawtooth Valley Voltage SYNC Pulse Width Input Offset Voltage Input Bias Current Input Offset Current DC Open Loop Gain HIGH Output Voltage LOW Output Voltage Common Mode Rejection Supply Voltage Rejection PWM Comparator (Note 6) Minimum Duty Cycle Maximum Duty Cycle HIGH Output Voltage LOW Output Voltage HIGH Input Current LOW Input Current Shutdown Delay Sense Voltage Input Bias Current Shutdown Delay From pin 7, 100mV Overdrive, TJ = 25C VCOMPENSATION = +0.4V VCOMPENSATION = +3.6V ISOURCE = 40A ISINK = 3.6mA VIH = +2.4V VIL = +0.4V From Pin 8, TJ = 25C RS 50 90 45 2.4 49 4.0 0.2 -125 -225 160 100 -3 260 110 -10 80 0.4 -200 -360 0 45 2.4 49 4.0 0.2 -125 -225 160 100 -3 260 120 -10 0.4 -200 -360 0 % % V V A A ns mV A ns RL 10M VPIN 1 - VPIN 2 150mV, ISOURCE = 100A VPIN 2 - VPIN 1 150mV, ISINK = 100A RS 2k +VIN = 12 to 18V 70 66 64 3.6 TJ = +25C +VIN = 7 to 35V Over Operating TJ (Note 5) RT = 150k, CT = 20F (Note 5) RT = 2k, CT = 470pF +VIN = 35V +VIN =7V TJ = 25C, RL = 2.7k to VREF RS 2k 0.5 550 3.0 1.0 1.1 2 -350 35 72 4.2 0.2 94 80 0.4 70 66 5 -1000 100 60 3.6 3.5 0.5 3 0.5 2 8 1 6 1 650 3.0 1.0 1.1 2 -350 35 72 4.2 0.2 94 80 0.4 10 -2000 200 3.5 3 0.5 1 8 1 3 1 % % % Hz kHz V V s mV nA nA dB V V dB dB VREF = 3.8V VREF = 4.7V 2.4 0.2 4.7 0.4 2.4 0.2 4.8 0.4 V V TJ = +25C +VIN = 7 to 35V IL = 0 to 20mA Over Operating TJ (Note 5) Over Recommended Operating Conditions VREF = 0V 4.90 25 4.95 5.00 2 5 15 5.00 50 5.05 10 20 50 5.10 100 4.85 25 4.90 5.00 2 5 15 5.00 50 5.10 15 20 50 5.15 100 V mV mV mV V mA TEST CONDITIONS MIN TYP MAX MIN UC3526A TYP MAX UNITS
Error Amplifier Section (Note 7)
Digital Ports (SYNC, SHUTDOWN, and RESET)
Current Limit Comparator (Note 8)
Note 4: IL = 0mA. Note 5: Guaranteed by design, not 100% tested in production. Note 6: FOSC = 40kHz, (RT = 4.12k 1%, CT = 0.01F 1%, RD = 0 ).
Note 7: VCM = 0 to +5.2V Note 8: VCM = 0 to +12V. Note 9: VC = +15V. Note 10:VIN = +35V, RT = 4.12k.
3
UC1526A UC2526A UC3526A ELECTRICAL CHARACTERISTICS: +VIN = 15V, and over operating ambient temperature, unless otherwise specified TA = TJ.
PARAMETER Soft-Start Section Error Clamp Voltage CS Charging Current HIGH Output Voltage LOW Output Voltage Collector Leakage Rise Time Fall Time Cross-Conduction Charge Standby Current RESET = +0.4V RESET = +2.4V ISOURCE = 20mA ISOURCE = 100mA ISINK = 20mA ISINK = 100mA VC = 40V CL = 1000pF (Note 5) CL = 1000pF (Note 5) Per cycle, TJ = 25C SHUTDOWN = +0.4V 50 12.5 12 0.1 100 13.5 13 0.2 1.2 50 0.3 0.1 8 14 20 0.3 2.0 150 0.6 0.2 0.4 150 50 12.5 12 0.1 100 13.5 13 0.2 1.2 50 0.3 0.1 8 14 20 0.3 2.0 150 0.6 0.2 0.4 150 V A V V V V A s s nC mA TEST CONDITIONS MIN UC1526A UC2526A TYP MAX MIN UC3526A UNITS TYP MAX
Output Drivers (Each Output) (Note 9)
Power Consumption (Note 10)
Note 4: IL = 0mA. Note 5: Guaranteed by design, not 100% tested in production. Note 6: FOSC = 40kHz, (RT = 4.12k 1%, CT = 0.01F 1%, RD = 0 ). Note 7: VCM = 0 to +5.2V Note 8: VCM = 0 to +12V. Note 9: VC = +15V. Note 10:VIN = +35V, RT = 4.12k.
Open Loop Test Circuit UC1526A
4
UC1526A UC2526A UC3526A APPLICATIONS INFORMATION Voltage Reference
The reference regulator of the UC1526A is based on a precision band-gap reference, internally trimmed to 1% accuracy. The circuitry is fully active at supply voltages above +7V, and provides up to 20mA of load current to external circuitry at +5.0V. In systems where additional current is required, an external PNP transistor can be used to boost the available current. A rugged low frequency audio-type transistor should be used, and lead lengths between the PWM and transistor should be as short as possible to minimize the risk of oscillations. Even so, some types of transistors may require collector-base capacitance for stability. Up to 1 amp of load current can be obtained with excellent regulation if the device selected maintains high current gain.
Figure 2. Under-Voltage Lockout Schematic Soft-Start Circuit The soft-start circuit protects the power transistors and rectifier diodes from high current surges during power supply turn-on. When supply voltage is first applied to the UC1526A, the under-voltage lockout circuit holds RESET LOW with Q3. Q1 is turned on, which holds the soft-start capacitor voltage at zero. The second collector of Q1 clamps the output of the error amplifier to ground, guaranteeing zero duty cycle at the driver outputs. When the supply voltage reaches normal operating range, RESET will go HIGH. Q1 turns off, allowing the internal 100A current source to charge CS. Q2 clamps the error amplifier output to 1VBE above the voltage on CS. As the soft-start voltage ramps up to +5V, the duty cycle of the PWM linearly increases to whatever value the voltage regulation loop requires for an error null.
Figure 1. Extending Reference Output Current
Under-Voltage Lockout
The under-voltage lockout circuit protects the UC1526A and the power devices it controls from inadequate supply voltage, If +VIN is too low, the circuit disables the output drivers and holds the RESET pin LOW. This prevents spurious output pulses while the control circuitry is stabilizing, and holds the soft-start timing capacitor in a discharged state. The circuit consists of a +1.2V bandgap reference and comparator circuit which is active when the reference voltage has risen to 3VBE or +1.8V at 25C. When the reference voltage rises to approximately +4.4V, the circuit enables the output drivers and releases the RESET pin, allowing a normal soft-start. The comparator has 350mV of hysteresis to minimize oscillation at the trip point. When +VIN to the PWM is removed and the reference drops to +4.2V, the under-voltage circuit pulls RESET LOW again. The soft-start capacitor is immediately discharged, and the PWM is ready for another soft-start cycle. The UC1526A can operate from a +5V supply by connecting the VREF pin to the +VIN pin and maintaining the supply between +4.8 and +5.2V.
Figure 3. Soft-Start Circuit Schematic Digital Control Ports The three digital control ports of the UC1526A are bi-directional. Each pin can drive TTL and 5V CMOS logic directly, up to a fan-out of 10 low-power Schottky gates. Each pin can also be directly driven by open-collector TTL, open-drain CMOS, and open-collector voltage comparators; fan-in is equivalent to 1 low-power Schottky gate. Each port is normally HIGH; the pin is pulled LOW to activate the particular function. Driving SYNC LOW initiates a discharge cycle in the oscillator. Pulling SHUTDOWN LOW immediately inhibits all PWM output pulses. Holding RESET LOW discharges the soft-start 5
APPLICATIONS INFORMATION (cont.)
capacitor. The logic threshold is +1.1V at +25C. Noise immunity can be gained at the expense of fan-out with an external 2k pull-up resistor to +5V.
UC1526A UC2526A UC3526A
the SYNC pin will then lock the oscillator to the external frequency. Multiple devices can be synchronized together by programming one master unit for the desired frequency, and then sharing its sawtooth and clock waveforms with the slave units. All CT terminals are connected to the CT pin of the master and all SYNC terminals are likewise connected to the SYNC pin of the master. Slave RT terminals are left open or connected to VREF. Slave RD terminal may be either left open or grounded.
Figure 4. Digital Control Port Schematic
Oscillators
The oscillator is programmed for frequency and dead time with three components: RT, CT and RD. Two waveforms are generated: a sawtooth waveform at pin 10 for pulse width modulation, and a logic clock at pin 12. The following procedure is recommended for choosing timing values: 1. With RD= 0 (pin 11 shorted to ground) select values for RT and CT from the graph on page 4 to give the desired oscillator period. Remember that the frequency at each driver output is half the oscillator frequency, and the frequency at the +VC terminal is the same as the oscillator frequency. 2. If more dead time is required, select a larger value of RD. At 40kHz dead time increases by 400ns/. 3. Increasing the dead time will cause the oscillator frequency to decrease slightly. Go back and decrease the value of RT slightly to bring the frequency back to the nominal design value. The UC1526A can be synchronized to an external logic clock by programming the oscillator to free-run at a frequency 10% slower than the SYNC frequency. A periodic LOW logic pulse approximately 0.5s wide at
Figure 6. Error Amplifier Connections
Error Amplifier
The error amplifier is a transconductance design, with an output impedance of 2M. Since all voltage gain takes place at the output pin, the open-loop gain/frequency characteristics can be controlled with shunt reactance to ground. When compensated for unity-gain stability with 100pF, the amplifier has an open-loop pole at 800Hz. The input connections to the error amplifier are determined by the polarity of the switching supply output voltage. For positive supplies, the common-mode voltage is +5.0V and the feedback connections in Figure 6A are used. With negative supplies, the common-mode voltage is ground and the feedback divider is connected between the negative output and the +5.0V reference voltage, as shown in Figure 6B.
Figure 5. Oscillator Connections and Waveforms 6
Figure 7. Push-Pull Configuration
APPLICATIONS INFORMATION (cont.)
Output Drivers The totem pole output drivers of the UC1526A are designed to source and sink 100mA continuously and 200mA peak. Loads can be driven either from the output pins 13 and 16, or from the +VC, as required. Since the bottom transistor of the totem-pole is allowed to saturate, there is a momentary conduction path from the
UC1526A UC2526A UC3526A
+VC terminal to ground during switching; however, improved design has limited this cross-conduction period to less than 50ns. Capacitor decoupling at VC is recommended and careful grounding of Pin 15 is needed to insure that high peak sink currents from a capacitive load do not cause ground transients.
Figure 8. Single-Ended Configuration
Figure 9. Driving N-Channel Power MOSFETs
TYPICAL CHARACTERISTICS
OSCILLATOR PERIOD vs RT and CT OUTPUT BLANKING
7
UC1526A UC2526A UC3526A TYPICAL CHARACTERISTICS (Cont.)
Output Driver Deadtime vs. RD Value Under Voltage Lockout Characteristic
Error Amplifier Open Loop Gain vs. Frequency
Current Limit Transfer Function
Shutdown Delay
Output Driver Saturation Voltage
UNITRODE INTEGRATED CIRCUITS 7 CONTINENTAL BLVD. * MERRIMACK, NH 03054 TEL. (603) 424-2410 * FAX (603) 424-3460
8
PACKAGE OPTION ADDENDUM
www.ti.com
15-Nov-2005
PACKAGING INFORMATION
Orderable Device 85515022A 8551502VA UC1526AJ UC1526AJ883B UC1526AL UC1526AL883B UC2526ADW UC2526ADWTR UC2526ADWTRG4 UC2526AJ UC2526AN UC2526ANG4 UC2526AQ UC3526ADW UC3526ADWG4 UC3526ADWTR UC3526ADWTRG4 UC3526AJ UC3526AN UC3526ANG4 UC3526AQ
(1)
Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type LCCC CDIP CDIP CDIP LCCC LCCC SOIC SOIC SOIC CDIP PDIP PDIP PLCC SOIC SOIC SOIC SOIC CDIP PDIP PDIP PLCC
Package Drawing FK J J J FK FK DW DW DW J N N FN DW DW DW DW J N N FN
Pins Package Eco Plan (2) Qty 20 18 18 18 20 20 18 18 18 18 18 18 20 18 18 18 18 18 18 18 20 1 1 1 1 1 1 40 TBD TBD TBD TBD TBD TBD Green (RoHS & no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
POST-PLATE Level-NC-NC-NC A42 SNPB A42 SNPB A42 SNPB Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC
POST-PLATE Level-NC-NC-NC POST-PLATE Level-NC-NC-NC CU NIPDAU CU NIPDAU CU NIPDAU A42 SNPB CU NIPDAU CU NIPDAU CU SN CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU A42 SNPB CU NIPDAU CU NIPDAU CU SN Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-2-260C-1 YEAR
2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 1 20 20 46 40 40 TBD Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 1 20 20 46 TBD Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
15-Nov-2005
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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