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74F401 CRC Generator/Checker
April 1988 Revised August 1999
74F401 CRC Generator/Checker
General Description
The 74F401 Cycle Redundancy Check (CRC) Generator/ Checker provides an advanced tool for implementing the most widely used error detection scheme in serial digital data handling systems. A 3-bit control input selects one-ofeight generator polynomials. The list of polynomials includes CRC-16 and CRC-CCITT as well as their reciprocals (reverse polynomials). Automatic right justification is incorporated for polynomials of degree less than 16. Separate clear and preset inputs are provided for floppy disk and other applications. The Error output indicates whether or not a transmission error has occurred. Another control input inhibits feedback during check word transmission. The 74F401 is fully compatible with all TTL families.
Features
s Eight selectable polynomials s Error indicator s Separate preset and clear controls s Automatic right justification s Fully compatible with all TTL logic families s 14-pin package s 9401 equivalent s Typical applications: Floppy and other disk storage systems Digital cassette and cartridge systems Data communication systems
Ordering Code:
Order Number 74F401SC 74F401PC Package Number M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Connection Diagram
(c) 1999 Fairchild Semiconductor Corporation
DS009534
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74F401
Unit Loading/Fan Out
Pin Names S0-S2 D CP CWE P MR Q ER Description Polynomial Select Inputs Data Input Clock Input (Operates on HIGH-to-LOW Transition) Check Word Enable Input Preset (Active LOW) Input Master Reset (Active HIGH) Input Data Output Error Output U.L. HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 50/33.3 Input IIH/IIL Output IOH/IOL 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA -1 mA/20 mA -1 mA/20 mA
Functional Description
The 74F401 is a 16-bit programmable device which operates on serial data streams and provides a means of detecting transmission errors. Cyclic encoding and decoding schemes for error detection are based on polynomial manipulation in modulo arithmetic. For encoding, the data stream (message polynomial) is divided by a selected polynomial. This division results in a remainder which is appended to the message as check bits. For error checking, the bit stream containing both data and check bits is divided by the same selected polynomial. If there are no detectable errors, this division results in a zero remainder. Although it is possible to choose many generating polynomials of a given degree, standards exist that specify a small number of useful polynomials. The 74F401 implements the polynomials listed in Table 1 by applying the appropriate logic levels to the select pins S0, S1 and S2. The 74F401 consists of a 16-bit register, a Read Only Memory (ROM) and associated control circuitry as shown in the block diagram. The polynomial control code presented at inputs S0, S1 and S2 is decoded by the ROM, selecting the desired polynomial by establishing shift mode operation on the register with Exclusive OR gates at appropriate inputs. To generate the check bits, the data stream is entered via the Data inputs (D), using the HIGH-to-LOW transition of the Clock input (CP). This data is gated with the most significant output (Q) of the register, and controls the Exclusive OR gates Figure 1. The Check Word Enable (CWE) must be held HIGH while the data is being entered. After the last data bit is entered, the CWE is brought LOW and the check bits are shifted out of the register and appended to the data bits using external gating Figure 2. To check an incoming message for errors, both the data and check bits are entered through the D input with the CWE input held HIGH. The 74F401 is not in the data path, but only monitors the message. The Error Output becomes valid after the last check bit has been entered into the 74F401 by a HIGH-to-LOW transition of CP. If no detectable errors have occurred during the data transmission, the resultant internal register bits are all LOW and the Error Output (ER) is LOW. If a detectable error has occurred, ER is HIGH. A HIGH on the Master Reset input (MR) asynchronously clears the register. A LOW on the Preset input (P) asynchronously sets the entire register if the control code inputs specify a 16-bit polynomial; in the case of 12- or 8-bit check polynomials only the most significant 12 or 8 register bits are set and the remaining bits are cleared.
TABLE 1. Select Code S2 L L L L H H H H S1 L L H H L L H H S0 L H L H L H L H Polynomial X16 + X15 + X2 + 1 X16 + X14 + X + 1 X16 + X15 + X13 + X7 + X4 + X2 + X1 + 1 X12 + X11 + X3 + X2 + X + 1 X8 + X7 + X5 + X4 + X + 1 X8 + 1 X16 + X12 + X5 + 1 X16 + X11 + X4 + 1 LRC-8 CRC-CCITT CRC-CCITT REVERSE CRC-12 Remarks CRC-16 CRC-16 REVERSE
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74F401
Block Diagram
FIGURE 1. Equivalent Circuit for X16 + X15 + X2 + 1
FIGURE 2. Check Word Generation
Note 1: Check word Enable is HIGH while data is being clocked, LOW while transmission of check bits. Note 2: 74F401 must be reset or preset before each computation. Note 3: CRC check bits are generated and appended to data bits.
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74F401
Absolute Maximum Ratings(Note 4)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 5) Input Current (Note 5) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) -0.5V to VCC -0.5V to +5.5V -65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage 0C to +70C +4.5V to +5.5V
Note 4: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 5: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH VOL IIH IBVI ICEX VID IOD IIL IOS ICCH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Short-Circuit Current Power Supply Current -60 70 4.75 3.75 -0.6 -150 105 10% VCC 5% VCC 10% VCC 2.5 2.7 0.5 5.0 7.0 50 Min 2.0 0.8 -1.2 Typ Max Units V V V V V A A A V A mA mA mA Min Min Min Max Max Max 0.0 0.0 Max Max Max VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = -18 mA IOH = -1 mA IOH = -1 mA IOL = 20 mA VIN = 2.7V VIN = 7.0V VOUT = VCC IID = 1.9 A All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V VOUT = 0V VO = HIGH
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74F401
AC Electrical Characteristics
TA = +25C Symbol Parameter Min fMAX tPLH tPHL tPHL tPLH tPHL tPLH tPLH tPHL Maximum Clock Frequency Propagation Delay CP to Q Propagation Delay MR to Q Propagation Delay P to Q Propagation Delay MR to ER Propagation Delay P to ER Propagation Delay CP to ER 100 4.5 4.0 3.0 3.0 3.5 3.0 5.0 4.5 11.5 10.0 7.5 8.5 11.0 8.5 13.0 11.5 VCC = +5.0V CL = 50 pF Typ Max TA = 0C to +70C VCC = +5.0V CL = 50 pF Min 85 4.5 4.0 3.0 3.0 3.5 3.0 5.0 4.5 13.5 11.0 8.0 9.5 12.0 10.0 14.5 12.5 Max MHz ns ns ns ns ns Units
ns
AC Operating Requirements
TA = +25C Symbol Parameter VCC = +5.0V Min tS(H) tS(L) tS(H) tS(L) tH(H) tH(L) tW(L) tW(H) tW(L) tW(H) tREC tREC Set-up Time, HIGH or LOW D to CP Set-up Time, HIGH or LOW CWE to CP Hold Time, HIGH or LOW D and CWE to CP P Pulse Width, LOW Clock Pulse Width, HIGH or LOW MR Pulse Width, HIGH Recovery Time MR to CP Recovery Time P to CP 5.0 5.0 4.0 4.0 2.0 2.0 7.0 5.0 5.0 5.0 4.0 Max TA = 0C to +70C VCC = +5.0V Min 5.5 5.5 4.5 4.5 2.0 2.0 8.0 6.0 6.0 5.5 4.5 ns ns ns ns ns Max Units
2.0
2.0
ns
5
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74F401
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A
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74F401 CRC Generator/Checker
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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