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TM
DG406/883, DG407/883
Single 16-Channel/Differential 8-Channel CMOS Analog Multiplexers
Description
The DG406/883 and DG407/883 monolithic CMOS analog multiplexers are drop-in replacements for the popular DG506A/883 and DG507A/883 series devices. They each include an array of sixteen analog switches, a TTL and CMOS compatible digital decode circuit for channel selection, a voltage reference for logic thresholds, and an ENABLE input for device selection when several multiplexers are present. These multiplexers feature lower signal ON resistance (<100) and faster transition time (tTRANS <250ns) compared to the DG506A/883 and DG507A/883. Charge injection has been reduced, simplifying sample and hold applications. The improvements in the DG406 series are made possible by using a high voltage silicon-gate process. An epitaxial layer prevents the latch-up associated with older CMOS technologies. The 44V maximum voltage range permits controlling 30VP-P signals when operating with 15V power supplies. The sixteen switches are bilateral, equally matched for AC or bidirectional signals. The ON resistance variation with analog signals is quite low over a 5V analog input range.
April 1997
Features
* This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * ON-Resistance 100 (Max) * Low Power Consumption (PD <1.2mW) * Fast Transition Time (300ns Max) * Low Charge Injection * TTL, CMOS Compatible * Single or Split Supply Operation
Applications
* * * * * *
Battery Operated Systems Data Acquisition Medical Instrumentation Hi-Rel Systems Communication Systems Automatic Test Equipment
Ordering Information
PART NUMBER DG406AK/883 DG407AK/883 TEMP. RANGE (oC) -55 to 125 -55 to 125 PACKAGE 28 Ld CERDIP 28 Ld CERDIP PKG. NO. F28.6 F28.6
Pinouts
DG406/883 (CERDIP) TOP VIEW
V+ 1 NC 2 NC 3 S16 4 S15 5 S14 6 S13 7 S12 8 S11 9 S10 10 S9 11 GND 12 NC 13 A3 14 28 D 27 V26 S8 25 S7 24 S6 23 S5 22 S4 21 S3 20 S2 19 S1 18 EN 17 A0 16 A1 15 A2 V+ 1 DB 2 NC 3 S8B 4 S7B 5 S6B 6 S5B 7 S4B 8 S3B 9 S2B 10 S1B 11 GND 12 NC 13 NC 14
DG407/883 (CERDIP) TOP VIEW
28 DA 27 V26 S8A 25 S7A 24 S6A 23 S5A 22 S4A 21 S3A 20 S2A 19 S1A 18 EN 17 A0 16 A1 15 A2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved
Spec Number
1
512041-883 FN3720.1
DG406/883, DG407/883 Functional Block Diagrams
DG406
S1A S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 TO DECODER LOGIC CONTROLLING BOTH TIERS OF MUXING ADDRESS DECODER 1 OF 16 D S2A S3A S4A S5A S6A S7A S8A S1B S2B S3B S4B S5B S6B S7B S8B TO DECODER LOGIC CONTROLLING BOTH TIERS OF MUXING ADDRESS DECODER 1 OF 8 DB DA
DG407
ENABLE
ENABLE
A0
A1
A2
A3
EN
A0
A1
A2
EN
DG406 TRUTH TABLE A3 X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 EN 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ON SWITCH None 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A2 X 0 0 0 0 1 1 1 1 A1 X 0 0 1 1 0 0 1 1
DG407 TRUTH TABLE A0 X 0 1 0 1 0 1 0 1 EN 0 1 1 1 1 1 1 1 1 ON SWITCH PAIR None 1 2 3 4 5 6 7 8
Logic "0" = V AL < 0.8V Logic "1" = V AH > 2.4V X = Don't Care
Spec Number 2
512041-883
DG406/883, DG407/883
Absolute Maximum Ratings
Voltages Referenced to VV+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44.0V GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V Digital Inputs, VS , VD (Note 1) . . . . . . (V-) -2V to (V+) +2V or 20mA, Whichever Occurs First Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA (Pulsed 1ms, 10% Duty Cycle Max)
Thermal Information
Thermal Resistance (Typical, Note 2)
JA (oC/W) JC (oC/W)
CERDIP Package . . . . . . . . . . . . . . . . 55 12 Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Signals on SX , D X or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings. 2. JA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS Devices tested at +VSUPPLY = +15V, -VSUPPLY = -15V, VAL = 0.8V, VAH = 2.4V, Unless Otherwise Specified GROUP A SUBGROUP 1, 3 2 1 1 2, 3 DEVICE TYPE All All All All All (NOTE 3) MIN -0.5 -50 (NOTE 3) MAX 90 120 15 0.5 50
PARAMETER Drain-Source ON Resistance
SYMBOL rDS(ON)
CONDITIONS VD = 10V, IS = -10mA VD = -10V, IS = 10mA (Note 4)
UNITS nA nA
Matching Between Channels Source OFF Leakage Current
rDS(ON) rDS(ON) Max - rDS(ON) Min (Note 3) IS(OFF) VEN = 0V, VS = 10V, VD = +10V VEN = 0V, VS = 10V, VD = +10V
Drain OFF Leakage Current DG406
ID(OFF)
1 2, 3
DG406
-1 -200
1 200 1 100
nA nA nA nA
DG407
1 2, 3
DG407
-1 -100
Drain ON Leakage Current DG406
ID(ON)
VS = VD = 10V Sequence Each Switch ON (Note 4)
1 2, 3
DG406
-1 -200
1 200 1 100 1 1 100 500 -
nA nA nA nA A A A A A A
DG407
1 2, 3
DG407
-1 -100
Logic High Input Current Logic Low Input Current Positive Supply Current
IAH IAL ICC
VA = 2.4V, 15V VEN = 0V, 2.4V, VA = 0V VEN = 2.4V, VA = 0V
1, 2, 3 1, 2, 3 1 2, 3
All All All All All All
-1 -1 -1 -10
Negative Supply Current
IEE
1 2, 3
Spec Number 3
512041-883
DG406/883, DG407/883
TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS Devices tested at +VSUPPLY = +15V, -VSUPPLY = -15V, VAL = 0.8V, VAH = 2.4V, Unless Otherwise Specified (Continued) GROUP A SUBGROUP 1 2, 3 1 2, 3 DEVICE TYPE All All All All (NOTE 3) MIN -1 -10 (NOTE 3) MAX 30 75 -
PARAMETER Positive Standby Current
SYMBOL ICC Standby IEE Standby
CONDITIONS VEN = VA = 0V or 5V
UNITS A A A A
Negative Standby Current
NOTES: 3. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 4. Room = 25oC, Cold and Hot = as determined by the operating temperature suffix. TABLE 1A. ELECTRICAL PERFORMANCE SPECIFICATIONS (SINGLE SUPPLY) Devices tested at +VSUPPLY = +12V, -VSUPPLY = 0V, VAL = 0.8V, VAH = 2.4V, Unless Otherwise Specified GROUP A SUBGROUP 1 DEVICE TYPE All
PARAMETER Drain-Source ON Resistance
SYMBOL rDS(ON) ICC
CONDITIONS VD = 3V, 10V IS = -1mA VEN = 0V or 5V, VA = 0V or 5V
MIN -
MAX 120
UNITS A A A A ns
Positive Current
1 2, 3 1 2, 3
All All All All All
-1 -5 -
30 75 450
Negative Current
IEE
Switching Time of Multiplexer
tTRANS tON(EN) tOFF(EN)
VS1 = 8V, VSS - 0V, VIN = 2.4V VINH = 2.4V, VINL = 0V, VS1 = 5V
1
Enable Turn-ON Time Enable Turn-OFF Time
1 1
All All
-
600 300
ns ns
TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS Devices tested at +VSUPPLY = +15V, -VSUPPLY = -15V, VAL = 0.8V, VAH = 2.4V, Unless Otherwise Specified GROUP A SUBGROUP 9 10, 11 9 10, 11 9 10, 11 Break Before Leakage Current tOPEN CL = 35pF, RL = 300, See Figure 3 9 10, 11 DEVICE TYPE All All All All All All All All
PARAMETER Transition Time
SYMBOL tTRANS
CONDITIONS CL = 35pF, RL = 300, See Figure 1 CL = 35pF, RL = 300, See Figure 2
MIN 25 10
MAX 300 400 200 400 150 300 -
UNITS ns ns ns ns ns ns ns ns
Enable Turn-ON Time
tON(EN)
Enable Turn-OFF Time
tOFF(EN)
Spec Number 4
512041-883
DG406/883, DG407/883
TABLE 3. DC ELECTRICAL PERFORMANCE SPECIFICATIONS Devices tested at +VSUPPLY = +15V, -VSUPPLY = -15V, VAL = 0.8V, VAH = 2.4V, Unless Otherwise Specified PARAMETER Off Isolation Time SYMBOL VISO CONDITIONS VEN = 0V, RL = 1K, f = 100kHz, GEN = 1VP-P Sine Wave, See Figure 5 CL = 10nF, VS = 0V, RS = 0, See Figure 4 RL = 1K, f = 100kHz, GEN = 1VP-P Sine Wave, See Figure 5 VEN = 0V, VS = 0V, f = 1MHz VEN = 0V, VD = 0V, f = 1MHz 5 5 CD(ON) VEN = 0V, VD = 0V, f = 1MHz 5 5 25 25 400 200 pF pF 25 25 200 100 pF pF NOTE 5 TEMP (oC) 25 MIN 50 TYP MAX UNITS dB
Charge Transfer Error
V CTE V CT
5
25
-
-
10
mV
Crosstalk
5
25
50
-
-
dB
Source OFF Capacitance Drain OFF Capacitance DG406 DG407 Drain ON Capacitance DG406 DG407 NOTE:
CS(OFF) CD(OFF)
65
25
-
-
10
pF
5. Parameters listed via process parameters and are not directly tested at final production. These parameters are lab characterized upon design release, or upon design changes. These parameters are guaranteed by characterization based upon data from multiple production rich reflect lot to lot and within lot variation. TABLE 4. ELECTRICAL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS Interim Electrical Parameters (Pre Burn0In) Final Electrical Test Parameters Group A Test Requirements Group C and D Endpoints NOTE: 6. PDA applied to Subgroup 1 only. SUBGROUPS (SEE TABLES 1 AND 2) 1 1 (Note 6), 2, 3, 9, 10, 11 1, 2, 3, 9, 10, 11 1
Spec Number 5
512041-883
DG406/883, DG407/883 Test Circuits and Waveforms
+15V +15V
+2.4V
EN A3 A2 A1
V+
S1
10V
+2.4V
EN A2
V+
S1B
10V
S2 - S15 300 300 LOGIC INPUT DG406 S 16 VD 35pF 10V VO 50
VDB 300 35pF 300 DG407 S8B 10V VO
A1
A0 GND 50
A0 GND
-15V
FIGURE 1A.
-15V
= S1A - S8A , S2B - S7B , DA
FIGURE 1B.
tr < 20ns tf < 20ns 50% 50%
LOGIC INPUT
3V 0V VS1B 0V VS8B tTRANS S1 ON 80%
SWITCH OUTPUT VO
80%
S8 ON
tTRANS
FIGURE 1C. FIGURE 1. TRANSITION TIME
+15V
+15V
A3 A2 A1
V+
S1
-5V
A2 A1 A0 VO 35pF EN 50
V+ DG407
S1B
-5V
S2 - S16 DG406 VD
A0 EN GND 50
GND
V-
DB 35pF
VO
-15V
FIGURE 2A.
-15V
= S1A - S8A , S2B - S8B , DA
FIGURE 2B.
3V 50% 0V tON(EN) 0V 50%
tr < 20ns tf < 20ns
tOFF(EN)
SWITCH OUTPUT VO VO
90%
FIGURE 2C.
Spec Number 6
512041-883
DG406/883, DG407/883 Test Circuits and Waveforms
+15V LOGIC INPUT +5V 0V VD
(Continued) FIGURE 2. ENABLE SWITCHING TIME
tr < 20ns tf < 20ns 50%
3V
+2.4V
EN A3 A2
V+
ALL S AND DA
A1 A0 GND 50
DG406 DG407
D, V- DB 300 35pF
VO
SWITCH OUTPUT VO
80%
0V tOPEN
-15V
FIGURE 3A. FIGURE 3. BREAK-BEFORE-MAKE INTERVAL
FIGURE 3B.
+15V V+ 3V OFF 0V ON OFF
SX EN VGEN = 0-3V A0 A1 A2
LOGIC INPUT D CL 10nF VVO SWITCH OUTPUT
DG406 DG407
A3 GND
VO
5V
-15V
FIGURE 4. CHARGE INJECTION
+15V VS RG = 50 VGEN = 1VP-P SX1 V+ 1k D RL 1k VO 1VP-P RG = 50 S1 SX2
+15V
V+
VS
SX16 A0 DG406 DG407 A1 A2
SX16 A0 DG406 DG407 A1 A2 A3
D RL 1k
VO
A3 GND EN V-
GND EN V-
-15V
OFF ISOLATION = 20LOG
VOUT VIN
-15V
CROSSTALK = 20LOG
VOUT VIN
FIGURE 5. OFF ISOLATION
FIGURE 6. CROSSTALK
Spec Number 7
512041-883
DG406/883, DG407/883 Burn-In Circuit
CERDIP BURN-IN SCHEMATIC DG406/407AK/883
+15V D1 C1 R1 1 +V 2 NC/OUT B 3 NC 4 IN 16/8B 5 IN 15/7B 6 IN 14/6B 7 IN 13/5B 8 IN 12/4B 9 IN 11/3B 10 IN 10/2B 11 IN 9/1B 12 GND 13 VREF +5V 14 A3/NC OUT/OUTA 28 -V 27 IN 8/8A 26 IN 7/7A 25 IN 6/6A 24 IN 5/5A 23 IN 4/4A 22 IN 3/3A 21 IN 2/2A 20 IN 1/1A 19 EN 18 A0 17 A1 16 A2 15 R2 D2 -15V C2
NOTE: R1, R2 = 10k 5%, 1/2W or 1/4W (Per Socket) C1, C2 = 0.01F (Min, Per Socket) or 0.1F (Min, Per Row) D1, D2 = IN402 (or Equivalent, Per Board)
Schematic Diagram
V+ GND VREF
(Typical Channel)
D A0 V+ AX LEVEL SHIFT DECODE/ DRIVE V-
S1
V+ EN SN V-
Spec Number 8
512041-883
DG406/883, DG407/883 Typical Design Information
The information contained in this section has been developed through characterization by Harris Semiconductor and is for use as application and design information only. No guarantee is implied.
Typical Performance Curves
160 rDS(ON) , ON RESISTANCE () rDS(ON), ON-RESISTANCE () 140 120 100 80 60 40 20 0 -20 8V 10V 12V 15V 20V 5V 80 70 60 50 40 30 20 10 0 -15 -10 -5 0 5 VD , DRAIN VOLTAGE (V) -40 oC -55oC V+ = 15V V- = -15V 10 15 125oC 85oC 25oC 0oC
-16
-12
-8 -4 0 4 8 VD , DRAIN VOLTAGE (V)
12
16
20
FIGURE 7. rDS(ON) vs VD AND SUPPLY
FIGURE 8. rDS(ON) vs VD AND TEMPERATURE
240 rDS(ON) , ON-RESISTANCE () 200 160 10V 120 12V 80 40 0 15V 20V V+ = 7.5V
V- = 0V
120 80 ID , I S , CURRENT (pA) 40 0 -40 -80 -120 -15
V+ = 15V, V- = -15V VS = -VD FOR ID(OFF) VD = VS(OPEN) FOR ID(ON)
IS(OFF)
DG406 I D(ON), I D(OFF) DG407 ID(ON), ID(OFF)
22V
0
4
8 12 VD , DRAIN VOLTAGE (V)
16
20
-10
-5 0 5 10 VS , VD , SOURCE DRAIN VOLTAGE (V)
15
FIGURE 9. rDS(ON) vs VD AND SUPPLY
FIGURE 10. ID , IS LEAKAGE CURRENTS vs ANALOG VOLTAGE
Spec Number 9
512041-883
DG406/883, DG407/883 Typical Performance Curves
100nA 10nA ID , IS , CURRENT (A) 1nA TIME (ns) 100pA 10pA 1pA 0.1pA -55 I D(ON), ID(OFF)
(Continued)
V+ = 15V, V- = -15V VS OR VD = 10V
350 300 250 200 tON(EN) 150 100 50 0 tOFF(EN) tTRANS
IS(OFF)
-35
-15
5
25
45
65
85
105
125
5
TEMPERATURE (oC)
10 15 VSUPPLY , SUPPLY VOLTAGE (V)
20
FIGURE 11. ID , IS LEAKAGE vs TEMPERATURE
700 V- = 0V 600 500 TIME (ns) 400 300 200 tOFF(EN) 100 0 tTRANS tON(EN)
FIGURE 12. SWITCHING TIMES vs BIPOLAR SUPPLIES
-140 -120 -100 ISOL (dB) -80 -60 -40 -20 0 100
5
10 15 V+, SUPPLY VOLTAGE (V)
20
1K
10K 100K f, FREQUENCY (Hz)
1M
10M
FIGURE 13. SWITCHING TIMES vs SINGLE SUPPLY
FIGURE 14. OFF-ISOLATION vs FREQUENCY
10 8 6 I , CURRENT (mA) 4 2 0 -2 -4 -6 -8 -10 10
EN = 5V, A X = 0V OR 5V
300 280 260 I+ TIME (ns) 240 220 200 180 160 140 I120 100 80
V+ = 15V, V- = -15V
tTRANS tON(EN)
IGND
tOFF(EN) -35 -15 5 25 45 65 85 105 125
100
1K
10K
100K
1M
10M
60 -55
f, FREQUENCY (Hz)
TEMPERATURE (oC)
FIGURE 15. SUPPLY CURRENTS vs SWITCHING FREQUENCY
FIGURE 16. tON /tOFF vs TEMPERATURE
Spec Number 10
512041-883
DG406/883, DG407/883 Typical Performance Curves
(Continued)
3
2 VA (V) 1 0 0
5
10
15
20
VSUPPLY , SUPPLY VOLTAGE (V)
FIGURE 17. SWITCHING THRESHOLD vs SUPPLY VOLTAGE
Spec Number 11
512041-883
DG406/883, DG407/883 Die Characteristics
DIE DIMENSIONS: 2490m x 4560m x 485m 25m METALLIZATION: Type: SiAl Thickness: 12kA 1kA PASSIVATION: Type: Nitride Thickness: 8kA 1kA WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm2
Metallization Mask Layout
DG406/883
NC V+ D V-
S16
S8
S15
S7
S14
S6
S13
S5
S12
S4
S11
S3
S10
S2
S9
S1
GND A3
A2
A1
A0
EN
Die Characteristics
DIE DIMENSIONS: 2490m x 4560m x 485m 25m Spec Number 12
512041-883
DG406/883, DG407/883 Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 -A-DBASE METAL b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A-B S AA C A-B S D -CQ A L DS M (b) SECTION A-A (c) LEAD FINISH
F28.6 MIL-STD-1835 GDIP1-T28 (D-10, CONFIGURATION A) 28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
INCHES SYMBOL A b b1 b2 b3 c c1 D MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.500 MAX 0.232 0.026 0.023 0.065 0.045 0.018 0.015 1.490 0.610 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 12.70 MAX 5.92 0.66 0.58 1.65 1.14 0.46 0.38 37.85 15.49 2.54 BSC 15.24 BSC 7.62 BSC 3.18 0.38 0.13 90o 28 5.08 1.52 105o 0.38 0.76 0.25 0.038 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94
E
eA
E e eA eA/2 L Q S1
e
DS
eA/2
c
0.100 BSC 0.600 BSC 0.300 BSC 0.125 0.015 0.005 90o 28 0.200 0.060 105o 0.015 0.030 0.010 0.0015
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH.
aaa bbb ccc M N
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Spec Number 13
512041-883

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