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HA118144AF
Video Camera CDS/AGC IC
Description
The HA118144AF is a bipolar IC that wa s developed to perform the analog signal processing between the CCD and the ADC in a CCD camera, and is optimal for use in CCD camera digital signal processing systems.
Features
* Excellent suppression of CCD output lower frequency noise by using clamp-type correlated double sampling. A high S/N ration by using dual (pre- and post-) AGC amplifi e rs and high sensitiv i t y based on increased coverage. Provides compensation for IC variations and imaging device sensitivity variations with an 8 state gain select circuit. Allows the AGC, gain select, and knee control to be controlled from the system microprocessor over a serial interface.
*
Functions
* * * * * * Correlated double sampling AGC Sample and hold Gain select Knee processing Serial interface control
*
*
1
HA118144AF
Pin Arrangement
HA118144AF
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24
NC SCK SDATA NC INJECT NC SP1 SP2 GND1 NC VDC NC
NC KNP CND4 NC CP NC VCLM CLM SO2 SO1 GND9 NC
1 2 3 4 5 6 7 8 9 10 11 12
NC SIN NC VFB1 VCC1 VCC2 VAGC SOA1 SIA2 VFB2 NC S/N
2
NC VCC9 SPRE NC GND3 NC OSC VCC3 BLK OBP GND2 NC HA118144AF (top view)
HA118144AF
Pin Functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Pin Name NC KNP GND4 NC CP NC VCLM CLM SO2 SO1 GND9 NC NC VCC9 SPRE NC GND3 NC OSC Oscillator correction 1.7 V DC 5k GND for IIL 0V VCC for 9 V Signal preview 9V 1.3 V Video signal 385 mVPP Emitter Clamp input Clamp output Signal output 2 Signal output 1 GND for 9 V 5.4 V 3.3 V 0V DC DC Video signal Video signal 1.5VPP 1.5VPP Base Emitter Emitter Emitter Clamp pulse CP pulse 5VPP Base Knee pulse GND for IIL interface 0V Pulse 5VPP 30 k Standard DC Signal Signal Voltage Type Level
HA118144AF
Signal
Impedance Function Description
Knee pulse input (unused). Fix at the low level. GND = 0 V
Clamp pulse input (unused). Fix at the low level.
Clamp input (unused). Fix at the low level. Clamp output (unused). Leave open. Signal output 2 Signal output 1 GND = 0 V
Power supply +9 V Signal preview. For use as an output monitor.
GND = 0 V
Oscillator correction pin for the AGC DAC bias circuit. Connect to GND through a 0.1 F capacitor. Power supply +5 V
20 21
VCC3 BLK
VCC for IIL interface Blanking pulse
5V BLK signal OBP signal 5VPP Base
Blanking pulse input. The output is clipped at the BLK level when a low level is input. Optical black pulse input. The feedback clamp operates when a high level is input.
22
OBP
Optical black pulse
5VPP
40 k
3
HA118144AF
Pin Functions (cont)
Pin Pin No. Name 23 24 25 GND2 NC S/N S/N correction 3.1 V DC Base Standard DC Signal Signal Voltage Type Level
HA118144AF
Signal
Impedance Function Description GND = 0 V
GND for AGC, 0V knee, BLK, DAC
AGC 1 bias circuit noise correction pin. Connect to GND through a 0.1 F capacitor.
26 27 28 29
NC VFB2 SIA2 SOA1 AGC2 feed back 2.4 V out AGC2 input AGC1 output 2.4 V 2V DC Video signal Video signal 370 mVPP 370 mVPP Collector Base Emitter AGC2 feedback output. Connect to SIA2. AGC2 input. Connect to SOA1 through a 0.1 F capacitor. AGC1 output. Connect to SIA2 through a 0.1 F capacitor. AGC control voltage output. Connect to GND through a 0.1 F capacitor. Power supply +5 V Power supply +5 V DC Base AGC1 feedback output. Connect to GND through a 0.1 F capacitor.
30
VAGC
AGC1 control out
2.5 V to DC 3.3 V
Diode
31 32 33
VCC2 VCC1 VFB1
VCC for AGC, 5V knee, BLK, DAC VCC for gain select, CDS AGC1 feed back out 5V 2.3 V
34 35 36 37 38
NC SIN NC NC VDC Bias for FBC 3.5 V DC 10 k Gain select bias voltage output. Connect to GND through a 0.1 F capacitor. Signal input 2.3 V Video 115 mVPP to Base 380 mVPP Signal input from the CCD sensor
39 40
NC GND1 GND for gain select, CDS 0V GND = 0 V
4
HA118144AF
Pin Functions (cont)
Pin Pin No. Name 41 SP2 Standard DC Signal Signal Voltage Type Level S&H pulse 5 VPP
HA118144AF
Signal Sample & hold pulse 2
Impedance Function Description 10 k Signal period sample and hold pulse. Duty = 25%, phase difference = 180 (with respect to SP1). Field through period clamp pulse. Duty = 25%, phase difference = 180 (with respect to SP2).
42
SP1
Sample & hold pulse 1
S&H
5 VPP
10 k
43 44 45 46 47 48
NC INJECT IIL injector NC SDATA SCK NC Serial data input Serial data clock Pulse Pulse 5 VPP 5 VPP 30 k 30 k Serial data input pin Serial clock pin. Period of 2 s to 20 s. 0.7 V DC 2.46 mA Bias current pin for internal logic circuits. Leave open.
5
6
VCC5V NC 31 VCC2 OSC supplement pad S/N correction pad OBP SP1 OBP AGC1 AGC2 385 mVPP 0.5 dB to 11.3 dB 1.3 VDC SPRE SP2 36 15 14 11.7 dB GAIN select Knee Knee ref BLK SO1 10 SO2 9 3.3 VDC 8 state 7 bit D/A AGC bias 8 CLM 5 Data converter 5 bit D/A CP 7 VCLM GND4 GND3 GND2 13 NC SDATA SCK KNP 3 17 23 46 47 2 16 NC 18 NC 24 NC 26 NC OBP BLK OBP 22 21 GND1 40 34 NC CP NC Pre view VCC9V 5.4 VDC 0 dB to 10.50 dB 19 25 VCC1 SOA1 SIA2 GND9 32 48 45 43 29 28 27 11 44 39 37 NC NC 2VDC 2.4 VDC VFB2 linj NC NC 370 mV PP 1.5 dB step -0.2 dB to 10.1 dB
Block Diagram
HA118144AF
20
VCC3
NC
1
33
VFB1
2.3 VDC
30
VAGC
SP1
42
SP1
Typical level: 115 V PP 35 to 380 VPP
SIN
SP2
41
SP2
38
VDC
3.5 VDC
NC
4
NC
6
12
HA118144AF
NC
NC 2
0.1 mA 200 2 k 1 k 1.6 mA 1 k 5 k 17 k 15.5 k 200 750 0.1 mA 1 k 9V 3 k 500 1 k 12 k 500 18.8 k 10 k 40 k 40 k 2.5 k 200 14.8 k 3 k 20.9 k 1 k 1 k 28 k 1 k 1 k 40 k 1.5 k 1 k 10 k 7.5 k 1 k 0.4 mA 1 k 1 k 3 k 1.5 k 500 10 k 2 k 9V 12 k 3 k 200 10 k 1.1 mA 1 k 9V 0.2 mA 1 mA
KNP GND4 NC 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
CP
NC
VCLM CLM SO2
SO1 GND9 NC
NC
VCC9V SPRE NC GND3 NC
HA118144AF
1
20 k 10 k
NC 48
OSC 19 correction
I/O Pin Equivalent Circuits
20 k
SCK 47
20 VCC3
10 k
20 k
SDATA 46
21 BLK
10 k
NC 45
4.05 k 5.6 k 1.5 k
22 OBP
17.5 k
3 k
Iinj 44
23 GND2
3 k
1.5 k
NC 43
24 NC
10 k
7.5 k
42 SP2 GND1 NC VDC NC NC SIN
41
40
39
38
37
36
35
34 NC
33
32
31
30
29
28
27 VFB1 VCC1 VCC2 VAGC SOA1 SIA2 VFB2
26 NC
25 S/N
SP1
HA118144AF
7
HA118144AF
Absolute Maximum Ratings
Item Maximum power supply voltage 1 Maximum power supply voltage 2 Operating temperature Storage temperature Operating power supply voltage 1 Operating power supply voltage 2 Power dissipation Symbol VCC5 Max VCC9 Max Topr Tstg VOP5 VOP9 PT Rated Value 6.0 10.0 -10 to +75 -55 to +125 4.75 to 5.25 8.5 to 9.5 440
HA118144AF
Unit V V C C V V mW
Notes: 1. These values are for the FQFP package mounted under the following conditions. Substrate material: Glass epoxy Wiring density: 40 mm x 1.5 mm 30% 2. This IC is for use in consumer products. It should not be used in industrial products, or in products that will be used outdoors for extended periods.
8
HA118144AF
Electrical Characteristics (Ta = 25C, VCC = 5 V, 9 V)
HA118144AF
Item Current ICC 5 V dissipation ICC 9 V FBC voltage fluctuations Pin inflow currents VFB1 voltage fluctuation SIA2 voltage fluctuation SIN pin current VFB1 pin current 1 VFB1 pin current 2 VFB1 pin current 3 SIA2 pin current VFB2 pin current 1 VFB2 pin current 2 VFB2 pin current 3 CP pin current VCLM pin current CLM pin current 1
Symbol Min ICC5 ICC9 VFB1 SIA2 ISIN IVFB1 IVFB2 IVFB3 ISIA2 IVFB21 IVFB22 IVFB23 ICP IVCLM ICLM1 25 3.25 -100 -120 -0.5 -0.5 60 -140 -0.5 -0.5 37 -75 -3.5 -3.5 -0.5
Typ 36 4.2 0 0 0 0 100 -100 0 0 50 -50 -1 -1 0
Max 47 5.55 100 120 0.5 0.5 140 -60 0.5 0.5 77 -35 0 0 0.5
Unit mA mA mV mV A A A A A A A A A A A
Test Conditions
Applicable Pins 20, 31, 32 14
FBC on, VVFB max - VVFB min FBC on, VSIA2 - VSIA2 min 42 pin 0 VDC 22 pin 0 VDC 22, 41, 42 pin 5 VDC 33 pin 2.5 VDC 22, 41, 42 pin 5VDC 33 pin 2.5 VDC 22 pin 0 VDC 22 pin 0 VDC 22, 41 pin, 5 VDC 27 pin 3 VDC 22, 41 pin, 5 VDC 27 pin 2 VDC 7 pin 2 VDC, 5 pin 2 VDC 7 pin 2 VDC, 5 pin, 1 VDC 7 pin 0 V, 5 pin 1 VDC, 8 pin 5 VDC 7 pin 0 V, 5 pin 1 VDC, 8 pin 0 VDC 7 pin 5 V, 5 pin 1 VDC, 8 pin 5 VDC 7 pin 5 V, 5 pin 2 VDC, 8 pin 0.7 VDC 22 pin 5 VDC 21 pin 0 VDC
33 28 35 33
28 27
5 7 8
CLM pin current 2
ICLM2
-0.5
0
0.5
A
CLM pin current 3
ICLM3
150
191
271
A
CLM pin current 4
ICLM4
-5
-3
-1
A
OBP pin current BLK pin current
IOBP IBLK
164 -14
205 -5
285 -2
A A
22 21
9
HA118144AF
Electrical Characteristics (Ta = 25C, VCC = 5 V, 9 V) (cont)
HA118144AF
Item Pin inflow currents SDATA pin current SCK pin current KNP pin current Pin voltages SIN pin voltage VFB1 pin voltage SOA1 pin voltage SIA2 pin voltage
Symbol Min ISDATA ISCK IKNP VSIN VVFB1 VSOA1 VSIA2 8.2 7.9 8.3 2.5 2.5 1.78 2.2
Typ 10.2 10.4 10.3 2.8 2.8 2.0 2.4
Max 12.2 12.1 12.3 3.1 3.1 2.22 2.6
Unit A A A V V V V
Test Conditions 46 pin 0.3 VDC 47 pin 0.3 VDC 2 pin 0.3 VDC
Applicable Pins 46 47 2
41, 42 pin 5 V, 35 22 pin 5 V, 2 pin 0 VDC 33 gain min 29 41 pin 5 V, 22 pin 5 V, 28 21 pin 5 V, 2 pin 0 VDC gain min 41 pin 5 V, 22 pin 5 VDC, 21 pin 5 V, 2 pin 0 V, gain min 7 pin 1.9 VDC, 5 pin 5 VDC Adjusts the pin 46 and 47 serial data amplitudes. 22, 41, 42 pin 5 VDC AGC 1 min 15 10 9 8 46, 47
SPRE pin voltage SO1 pin voltage SO2 pin voltage CLM pin voltage Serial input VTH
VSPRE VSO1 VSO2 VCLM SVTH
1.2 4.95 2.9 1.8 2.8
1.4 5.25 3.15 1.9 --
1.6 5.65 3.45 2.05 --
V V V V V
AC items
Gain select 1 Gain select 2 Gain select 3 Gain select 4 Gain select 5 Gain select 6 Gain select 7 Gain select 8 AGC1 G (0) AGC1 G (60) AGC1 G (70) AGC1 G (80) AGC1 G (90) AGC1 G (100) AGC1 G (110) AGC1 G (120) AGC1 G (127)
GSA1 GSA2 GSA3 GSA4 GSA5 GSA6 GSA7 GSA8 GA01 GA60 GA70 GA80 GA90 GA100 GA110 GA120 GA127
-0.8 0.3 1.7 3.1 4.6 6.2 7.7 9.1 -1.2 -0.6 0.4 2.1 3.7 5.4 7.1 8.8 9.7
-0.2 1.3 2.7 4.1 5.6 7.2 8.7 10.1 -0.2 0.2 1.2 2.9 4.5 6.2 7.9 9.6 10.5
1.2 2.3 3.7 5.1 6.6 8.2 9.7 11.1 0.8 1.0 2.0 3.7 5.3 7.0 8.7 10.4 11.3
dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
33, 29
22, 41, 42 pin 5 VDC gain select min
10
HA118144AF
Electrical Characteristics (Ta = 25C, VCC = 5 V, 9 V) (cont)
HA118144AF
Item AC items AGC2 G (0) AGC2 G (10) AGC2 G (20) AGC2 G (30) AGC2 G (40) AGC2 G (50) AGC2 G (60) AGC2 G (70) SO1 gain SO2 gain Gain ref pulse BLK level Knee compression ratio Knee off Knee start point
Symbol GA02 GA10 GA20 GA30 GA40 GA50 GA60 GA70 GS01 GS02 VGRP VBLK Gknee Knee off
Min -0.5 0.7 2.3 4.0 5.9 7.6 9.2 9.9 10.7 10.7 170 0.5 2.6 0.8
Typ 0.5 1.5 3.1 4.8 6.7 8.4 10.0 10.7 12.2 12.2 210 0.6 3.8 0.9 0.25
Max 1.5 2.3 3.9 5.6 7.5 9.2 10.8 11.5 13.7 13.7 250 0.7 5.0 1.0 0.35
Units Test Conditions dB dB dB dB dB dB dB dB dB dB mV V dB V V Pins 21, 22, 41, 42: 5 VDC, Pins 27, 28: Short knee max. Pins 21, 22, 41, 42: 5 VDC, Pins 27, 28: Short knee max.
Applicable Pins 28, 15
28, 10 28, 9
2, 29 Pins 41, 42: 5 VDC Pins 27, 28: Short knee 21, 9 max. 41, 42 pin 5 VDC Gknee max-Gknee min 41, 42 pin 5 VDC knee min 28, 15
Kne start 0.15
11
HA118144AF
Test Circuits
DC item test circuit SDATA SCK
HA118144AF
0.1 F 47 46 44 KNP 2 3 5 7 42 41 40 38 33 32 31 30 29 28
HA118144AF
0.1 F
11 14 17 19 20 21 22 23 25 10 F 0.1 F + - VCC 9 V 0.1 F 0.1 F VCC 5 V
AC item test circuit
SDATA SCK 0.1 F 47 46 42 41 40 38 33 32 31 30 29 28 27
KNP CP pulse
2 3 5 HA118144AF 8
1000 pF 0.1 F 0.1 F 75
11 14
17 19 20 21 22 23 25 0.1 F 0.1 F 10 F OBP pulse + - VCC 5 V BLK pulse
VCC 9 V 0.1 F
12
Test Patterns
2 s
HA118144AF
SCK1 AGC0 AGC10 AGC20 AGC30 AGC40 AGC50 AGC60 AGC70 AGC80 AGC90 AGC100 AGC110 AGC120 AGC127 Gain calibration MSB SCK input SDATA input LO 0 V HI 5 V LO 0 V HI 5 V t LSB MSB LSB Knee level AGC gain setting When observing the KNP pulse response, input pulses after DATE transmission. Pulse selection t SDATA18 SDATA17
SDATA1
SDATA2
SDATA3
SDATA4
Pin 46 SDATA input
SDATA5
SDATA5.5
SDATA6
SDATA6.5
SDATA7
SDATA8
MSB t
HA118144AF
13
HA118144AF
Main Characteristics
AGC1 gain I/O characteristics (VFB1 SOA1) (SOA1) (V) 3.750
HA118144AF
60 .2500 /div
80
100
120
127
AGC No.
Quiescent output potential, OBP high
1.250 1.000
VIN (VFB1 ) .2500/div (V) Gain select min, AGC No. 60, 80, 100, 120, 127 SP1, SP2: high, OBP: low
3.500
AGC2 gain I/O characteristics (SIA2 SPRE) (SPRE) (V) 2.500
AGC No. .2500 /div
60
40
20
0 Quiescent output potential, OBP high
.0000 1.000
VIN (SIA2) .2500/div (V) Knee SDATA min, AGC No. 0, 20, 40, 60
3.500
14
HA118144AF
Gain select I/O characteristics (V FB1 SOA1) (SOA1) (V) 3.750
HA118144AF
1 .2500 /div Gain select No. 1
2
3 4 5 67 8 Gain select No. 8
Quiescent output potential, OBP high
1.250 1.000
1.5
2.0
2.5
2.75
3.0
3.500
VIN (VFB1 ).2500/div (V) AGC gain min, gain select No. 1, 2, 3, 4, 5, 6, 7, 8 SP1, SP2: high, OBP: low
Knee I/O characteristics (V) 3.000
Compression ratio =
slope B slope A = 0.66 Slope A: 1.084
Slope B: 0.715 Knee max Knee point max .2500 /div Knee point min Knee min 0.94 VPP
SPRE output
0.25 VPP
1.3 V (black level)
.5000 1.500
.2500/div (V) SIA2 input
4.000
15
HA118144AF
Gain select characteristics 10 8 Gain (dB) 6 4 2 0 0 1 2 3 4 5 6 7
HA118144AF
Gain select number Gain for SIN (37) SOA1 (32) (AGC number 0)
AGC1 + AGC2 combined gain control characteristics Maximum gain control level: 21.3 dB
20 Gain control due to AGC1 (pre-stage)
15 Gain control level (dB)
10
Gain control due to AGC2 (post-stage) 5
0 10 20 30 40 50 60 70 80 90 100110 120 127 Gain select number
16
HA118144AF
Built-In Functions and Timing Charts
Function Overview * * * * CDS (correlated double sampling) circuit Gain select AGC gain setting Knee level setting
HA118144AF
Serial data control functions
Gain select (sensor) SIN CDS
AGC
Knee SO1, SO2
Serial interface
SP1 SP2
SCK
SDATA
Figure 1 CDS/AGC IC Function Overview
17
HA118144AF
Operation * CDS (correlated double sampling) circuit A CCD image sensor alternately outputs a noise segment (the A period signal) and a signal segment (the B period signal) that includes noise. Since the main noise generated by the image sensor is low frequency noise, and that noise is added to the signal, this noise is a factor in S/N ratio degradation. The CDS circuit removes the low frequency noise by first clamping the image sensor output signal noise segment (the A period signal) to a fixed voltage, and then replacing the noise segment with the signal segment by sampling and holding the signal segment (B period), which includes noise. Thus the CDS circuit generates a continuous signal, and consists of a clamping circuit, and sample and hold circuit, and inverting amplifier. (See figures 2 and 3.) -- Clamp circuit (CLAMP)
HA118144AF
This circuit removes low frequency noise by clamping the input signal 1 noise segment (A period) to a fixed voltage using the SP1 sample/hold pulse, and supplies its output signal to the sample and hold circuit. (See figures 2 and 3 4 .) -- Sample and hold circuit (S/H) This is a circuit that samples and holds the signal segment, and uses the SP2 sample/hold pulse to sample the signal segment (B period) and replace the noise segment with the signal segment to generate a continuous signal. (See figures 2 and 3 5 .) -- Following the inverting amplifier, the signal is supplied to the gain select circuit.
SP1 2 1 Input CLAMP 4
SP2 3 5 S/H AMP Output
Figure 2 CDS Circuit
18
HA118144AF
* Gain select The gain select circuit can be set to one of eight gain levels from -0.2 dB to 10.1 dB in 1.5 dB increments according to 3 bits of control data. The gain select circuit setting is used to adjust the input level to the AGC circuit in the next stage. * AGC gain The AGC gain is set by 7 bits of control data. The setting range is from 0 dB to 21 dB. Internally, the circuit is divided into two stages, AGC1 (pre-stage) and AGC2 (post*
HA118144AF
stage), which together realize a variable amplification of up to 21 dB. The application should implement an autoaliasing function by processing the camera DSPIC iris result in the microprocessor, and using that to control the AGC gain in this IC using serial data transfers. Knee level The amplifier I/O characteristics are shown in figure 4. The inflection point where the gain changes is determined by 5 bits of data.
A
B Low FREQ noise
1
2
3
4
5
6
Figure 3 CDS Timing Chart
19
HA118144AF
HA118144AF
Output
Output
Gain G2 Inflection point Knee start (typ 0.25 V) G2 G1 = 2 3
Knee off (typ 0.9 V)
Gain G1
(1.5 VPP )
Input
Input
Figure 4 Knee Level Characteristics
20
HA118144AF
Serial Data Control * Timing chart -- Serial transfers are performed by the SCK and SDATA pins in the CDS/AGC IC.
HA118144AF
-- Internally, the IC takes the case where SDATA is high on the falling edge of SCK as the data latch timing. -- Data is acquired on the falling edge of SCK for D1 to D10 prior to the latch timing.
Table 3-1 Serial Control Overview
SDATA Function Knee level gain selection setting D1 0 D2 0 D3 D4 D5 D6 D7 D8 D9 D10
Knee level setting d1 d2 d3 d4 d5
Gain select d1 d2 d3 --
AGC gain setting
0
1
AGC gain d1 d2 d3 d4 d5 d6 d7
Pulse selection
1
0
Correc- -- tion/ knee
2 s to 20 s
SCK
SDATA
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
IC internal data latch timing
Figure 5 Serial Data Timing Chart
21
HA118144AF
* Bit weightings in serial settings data
HA118144AF
* Gain select D10 D9 D8 d3 d2 d1 1 1 1 10.1 dB 110 101 100 011 010 001 0 0 0 -0.2 dB
* Knee level D7 D6 D5 d5 d4 d3 111 011 101
D4 d2 1 1 1
D3 d1 1 Knee start 1 1
* AGC gain D9 D8 D7 d7 d6 d5 111 011 101
D6 d4 1 1 1
D5 d3 1 1 1
D4 d2 1 1 1
D3 d1 1 21 dB 1 1
1 0 1 0
1 1 0 0
0 0 0 0
0 0 0 0
0 0 0 0
Knee off
1 0 1 0
1 1 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 dB
*
Pulse selection Since this function is not guaranteed, it should not be used.
The KNP pin (pin 2) should be held low. This bit can be set to either 0 or 1.
22
HA118144AF
Other Items * Standard waveforms for SIN, SP1, and SP2 -- SIN inputs a video signal from a CCD. -- The SP1 signal performs the field through period clamping, and the SP2 signal performs the signal period sample and hold. * SO1 and SO2 outputs
HA118144AF
The figure below shows the equivalent circuit for these outputs. As shown in the figure, the output waveform response speed is increased by using a capacitor coupled push-pull structure.
SIN SOA1 (x) 0.5 V/div 50 ns/div
SP2 SP1
0.5 V/div 50 ns/div
Figure 6 CDS AGC1 Operating Waveforms
10
SO1
9
SO2
Figure 7 Internal Equivalent Circuit for SO1 and SO2
23

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