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| UC1714/5 UC2714/5 UC3714/5 Complementary Switch FET Drivers FEATURES * Single Input (PWM and TTL Compatible) * High Current Power FET Driver, 1.0A Source/2A Sink * Auxiliary Output FET Driver, 0.5A Source/1A Sink * Time Delays Between Power and Auxiliary Outputs Independently Programmable from 50ns to 500ns * Time Delay or True Zero-Voltage Operation Independently Configurable for Each Output * Switching Frequency to 1MHz * Typical 50ns Propagation Delays * ENBL Pin Activates 220A Sleep Mode * Power Output is Active Low in Sleep Mode * Synchronous Rectifier Driver DESCRIPTION These two families of high speed drivers are designed to provide drive waveforms for complementary switches. Complementary switch configurations are commonly used in synchronous rectification circuits and active clamp/reset circuits, which can provide zero voltage switching. In order to facilitate the soft switching transitions, independently programmable delays between the two output waveforms are provided on these drivers. The delay pins also have true zero voltage sensing capability which allows immediate activation of the corresponding switch when zero voltage is applied. These devices require a PWM-type input to operate and can be interfaced with commonly available PWM controllers. In the UC1714 series, the AUX output is inverted to allow driving a p-channel MOSFET. In the UC1715 series, the two outputs are configured in a true complementary fashion. BLOCK DIAGRAM 2 PWR 50ns -500ns INPUT 6 TIMER S Q R VREF 50ns -500ns TIMER S Q T2 5 R VREF UC1714 ONLY T1 7 4 1 VCC 5V LOGIC GATES TIMER REF AUX VCC BIAS ENBL 3V GND 3 1.4V ENBL 8 ENABLE GND Note: Pin numbers refer to J, N and D packages. UDG-99028 02/99 UC1714/5 UC2714/5 UC3714/5 ABSOLUTE MAXIMUM RATINGS Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V Power Driver IOH continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -200mA peak. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1A Power Driver IOL continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400mA peak. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2A Auxiliary Driver IOH continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -100mA peak . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -500mA Auxiliary Driver IOL continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA peak. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A Input Voltage Range (INPUT, ENBL) . . . . . . . . . . -0.3V to 20V Storage Temperature Range . . . . . . . . . . . . . . -65C to 150C Operating Junction Temperature (Note 1) . . . . . . . . . . . . 150C Lead Temperature (Soldering 10 seconds) . . . . . . . . . . . 300C Note 1: Unless otherwise indicated, voltages are referenced to ground and currents are positive into, negative out of, the specified terminals. Note 2: Consult Packaging Section of databook for thermal limitations and specifications of packages. CONNECTION DIAGRAMS DIL-8, SOIC-8 (Top View) J or N, D Packages SOIC-16 (Top View) DP Package ELECTRICAL CHARACTERISTICS: Unless otherwise stated, VCC = 15V, ENBL 2V, RT1 = 100k from T1 to GND, RT2 = 100k from T2 to GND, and -55C < TA < 125C for the UC1714/5, -40C < TA < 85C for the UC2714/5, and 0C < TA < 70C for the UC3714/5, TA = TJ. PARAMETER Overall VCC ICC, nominal ICC, sleep mode Power Driver (PWR) Pre Turn-on PWR Output, Low PWR Output Low, Sat. (VPWR) PWR Output High, Sat. (VCC - VPWR) Rise Time Fall Time T1 Delay, AUX to PWR T1 Delay, AUX to PWR PWR Prop Delay VCC = 0V, IOUT = 10mA, ENBL (R) 0.8V INPUT = 0.8V, IOUT = 40mA INPUT = 0.8V, IOUT = 400mA INPUT = 2.0V, IOUT = -20mA INPUT = 2.0V, IOUT = -200mA CL = 2200pF CL = 2200pF INPUT rising edge, RT1 = 10k (Note 4) INPUT rising edge, RT1 = 100k (Note 4) INPUT falling edge, 50% (Note 3) 20 350 0.3 0.3 2.1 2.1 2.3 30 25 35 500 35 1.6 0.8 2.8 3 3 60 60 80 700 100 V V V V V ns ns ns ns ns ENBL = 2.0V ENBL = 0.8V 7 18 200 20 24 300 V mA A TEST CONDITIONS MIN TYP MAX UNITS 2 UC1714/5 UC2714/5 UC3714/5 ELECTRICAL CHARACTERISTICS: Unless otherwise stated, VCC = 15V, ENBL 2V, RT1 = 100k from T1 to GND, RT2 = 100k from T2 to GND, and -55C < TA < 125C for the UC1714/5, -40C < TA < 85C for the UC2714/5, and 0C < TA < 70C for the UC3714/5, TA = TJ. PARAMETER Auxiliary Driver (AUX) AUX Output Low, Sat (VAUX) VIN = 2.0V, IOUT = 20mA VIN = 2.0V, IOUT = 200mA AUX Output High, Sat (VCC - VAUX) Rise Time Fall Time T2 Delay, PWR to AUX T2 Delay, PWR to AUX AUX Prop Delay Enable (ENBL) Input Threshold Input Current, IIH Input Current, IIL T1 Current Limit Nominal Voltage at T1 Minimum T1 Delay T2 Current Limit Nominal Voltage at T2 Minumum T2 Delay Input (INPUT) Input Threshold Input Current, IIH Input Current, IIL INPUT = 15V INPUT = 0V 0.8 1.4 1 -5 TEST CONDITIONS MIN TYP 0.3 1.8 2.1 2.3 45 30 MAX UNITS 0.8 2.6 3.0 3.0 60 60 80 550 80 2.0 10 -10 -2 3.3 70 -2 3.3 100 2.0 10 -20 V V V V ns ns ns ns ns V A A mA V ns mA V ns V A VIN = 0.8V, IOUT = -10mA VIN = 0.8V, IOUT = -100mA CL = 1000pF CL = 1000pF INPUT falling edge, RT2 = 10k (Note 4) INPUT falling edge, RT2 = 100k (Note 4) INPUT rising edge, 50% (Note 3) 0.8 ENBL = 15V ENBL = 0V T1 = 0V 2.7 T1 = 2.5V, (Note 4) T2 = 0V 2.7 T2 = 2.5V, (Note 4) 20 250 50 350 35 1.2 1 -1 -1.6 3 40 -1.2 3 50 A Note 3: Propagation delay times are measured from the 50% point of the input signal to the 10% point of the output signal's transition with no load on outputs. Note 4: T1 delay is defined from the 50% point of the transition edge of AUX to the 10% of the rising edge of PWR. T2 delay is defined from the 90% of the falling edge of PWR to the 50% point of the transition edge of AUX. PIN DESCRIPTIONS AUX: The AUX switches immediately at INPUT's rising edge but waits through the T2 delay after INPUT's falling edge before switching. AUX is capable of sourcing 0.5A and sinking 1.0A of drive current. See the Time Relationships diagram below for the difference between the UC1714 and UC1715 for INPUT, MAIN, and AUX. During sleep mode, AUX is inactive with a high impedance. ENBL: The ENBL input switches at TTL logic levels (approximately 1.2V), and its input range is from 0V to 20V. 3 The ENBL input will place the device into sleep mode when it is a logical low. The current into VCC during the sleep mode is typically 220A. GND: This is the reference pin for all input voltages and the return point for all device currents. It carries the full peak sinking current from the outputs. Any tendency for the outputs to ring below GND voltage must be damped or clamped such that GND remains the most negative potential. UC1714/5 UC2714/5 UC3714/5 PIN DESCRIPTIONS (cont.) INPUT: The input switches at TTL logic levels (approximately 1.4V) but the allowable range is from 0V to 20V, allowing direct connection to most common IC PWM controller outputs. The rising edge immediately switches the AUX output, and initiates a timing delay, T1, before switching on the PWR output. Similarly, the INPUT falling edge immediately turns off the PWR output and initiates a timing delay, T2, before switching the AUX output. It should be noted that if the input signal comes from a controller with FET drive capability, this signal provides another option. INPUT and PWR provide a delay only at the leading edge while INPUT and AUX provide the delay at the trailing edge. PWR: The PWR output waits for the T1 delay after the INPUT's rising edge before switching on, but switches off immediately at INPUT's falling edge (neglecting propagation delays). This output is capable of sourcing 1A and sinking 2A of peak gate drive current. PWR output includes a passive, self-biased circuit which holds this pin active low, when ENBL 0.8V regardless of VCC's voltage. T1: A resistor to ground programs the time delay between AUX switch turn-off and PWR turn-on. T2: This pin functions in the same way as T1 but controls the time delay between PWR turn-off and activation of the AUX switch. T1, T2: The resistor on each of these pins sets the charging current on internal timing capacitors to provide independent time control. The nominal voltage level at each pin is 3V and the current is internally limited to 1mA. The total delay from INPUT to each output includes a propagation delay in addition to the programmable timer but since the propagation delays are approximately equal, the relative time delay between the two outputs can be assumed to be solely a function of the programmed delays. The relationship of the time delay vs. RT is shown in the Typical Characteristics curves. Either or both pins can alternatively be used for voltage sensing in lieu of delay programming. This is done by pulling the timer pins below their nominal voltage level which immediately activates the timer output. VCC: The VCC input range is from 7V to 20V. This pin should be bypassed with a capacitor to GND consistent with peak load current demands. TYPICAL CHARACTERISTICS INPUT PROPAGATION DELAYS PWR OUTPUT 500 T1 vs RT1 T2 vs RT2 400 T1 DELAY UC1714 AUX OUTPUT T2 DELAY DELAY (ns) 300 200 100 0 UC1715 AUX OUTPUT UDG-99027 0 10 20 30 40 50 60 RT (kW) 70 80 90 100 Time relationships. (Notes 3, 4) 4 T1 Delay, T2 Delay vs. RT UC1714/5 UC2714/5 UC3714/5 TYPICAL CHARACTERISTICS (cont.) 21 20 18 Icc (mA) 18 Icc (mA) 16 15 19 17 17 16 0 100 200 300 400 500 600 700 800 900 1000 Switching Frequency (kHz) 0 10 20 30 40 50 60 70 80 90 100 RT (k) ICC vs Switching Frequency with No Load and 50% Duty Cycle RT1 = RT2 = 50k ICC vs RT with Opposite RT = 50k 600 RT1 = 100k 600 500 500 Deadband Delay (ns) Deadband Delay (ns) 400 400 300 200 100 RT2 = 100k 300 RT1 = 50k 200 RT2 = 50k 100 RT1 = 10k RT1 < 6k 0 -75 -50 -25 0 25 50 Temperature (C) 75 100 125 0 -75 RT2 = 10k RT2 < 6k -50 -25 0 25 50 75 100 125 Temperature (C) T1 Deadband vs. Temperature AUX to PWR T2 Deadband vs. Temperature PWR to AUX TYPICAL APPLICATIONS UDG-94011 UDG-94012 Figure 1. Typical application with timed delays. Figure 2. Using the timer input for zero-voltage sensing. 5 UC1714/5 UC2714/5 UC3714/5 TYPICAL APPLICATIONS (cont.) UDG-94013 Figure 3. Self-actuated sleep mode with the absence of an input PWM signal. Wake up occurs with the first pulse while turn-off is determined by the (RTO CTO) time constant. UDG-94015-2 Figure 4. Using the UC1715 as a complementary synchronous rectifier switch driver with n-channel FETs UDG-94014-1 Figure 5. Synchronous rectifier application with a charge pump to drive the high-side n-channel buck switch. VIN is limited to 10V as VCC will rise to approximately 2VIN. 6 UC1714/5 UC2714/5 UC3714/5 TYPICAL APPLICATIONS (cont.) UDG-94016-1 Figure 6. Typical forward converter topology with active reset provided by the UC1714 driving an N-channel switch (Q1) and a P-channel auxilliary switch (Q2). UDG-94017-1 Figure 7. Using an N-channel active reset switch with a floating drive command. Vicor Corporation has claimed that the use of active reset in a forward converter topology is covered under its U.S. Patent 4,441,146. Unitrode is not suggesting or encouraging persons to infringe or use Vicor's patented technology absent a license from Vicor. UNITRODE CORPORATION 7 CONTINENTAL BLVD. * MERRIMACK, NH 03054 TEL. (603) 424-2410 * FAX (603) 424-3460 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 1999, Texas Instruments Incorporated |
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