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Z80180
Microprocessor Unit
Product Specification
PS014003-0603
This publication is subject to replacement by a later edition. To determine whether a later edition exists, or to request copies of publications, contact: ZiLOG Worldwide Headquarters
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Document Disclaimer
(c)2003 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Devices sold by ZiLOG, Inc. are covered by warranty and limitation of liability provisions appearing in the ZiLOG, Inc. Terms and Conditions of Sale. ZiLOG, Inc. makes no warranty of merchantability or fitness for any purpose. Except with the express written approval of ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
PS014003-0603
Z80180 Microprocessor Unit
iii
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Multiplexed Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . 15 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ASCI Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ASCI Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ASCI Transmit Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ASCI Receive Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 21 29 30 30 31 43 52 53 53 54 54 55 56
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Z80180 Microprocessor Unit iv
Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ASCI Channel Control Register A . . . . . . . . . . . . . . . . . . . . . . . ASCI CHANNEL CONTROL REGISTER B . . . . . . . . . . . . . . . . ASCI Status Register 0, 1 (STAT0, 1) . . . . . . . . . . . . . . . . . . . . CSIO Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . CSIO Transmit/Receive Data Register . . . . . . . . . . . . . . . . . Timer Data Register Channel 0L . . . . . . . . . . . . . . . . . . . . . Timer Data Register Channel 0H . . . . . . . . . . . . . . . . . . . . . Timer Reload Register 0L . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Reload Register 0H . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . ASCI Extension Control Register Channels 0 and 1 . . . . . . . . . ASEXT0 and ASEXT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Data Register Channel 1L . . . . . . . . . . . . . . . . . . . . . Timer Data Register Channel 1H . . . . . . . . . . . . . . . . . . . . . Timer Reload Register Channel 1L . . . . . . . . . . . . . . . . . . . Timer Reload Register Channel 1L . . . . . . . . . . . . . . . . . . . Free Running Counter I/O Address = 18H . . . . . . . . . . . . . . DMA Source Address Register Channel 0 . . . . . . . . . . . . . . . . . DMA Source Address Register, Channel 0L . . . . . . . . . . . . DMA Source Address Register, Channel 0H . . . . . . . . . . . . DMA Source Address Register Channel 0B . . . . . . . . . . . . . DMA Destination Address Register Channel 0 . . . . . . . . . . . . . DMA Destination Address Register Channel 0L . . . . . . . . . DMA Destination Address Register Channel 0H . . . . . . . . . DMA Destination Address Register Channel 0B . . . . . . . . . DMA Byte Count Register Channel 0 . . . . . . . . . . . . . . . . . . . . . DMA Byte Count Register Channel 0L . . . . . . . . . . . . . . . . . DMA Byte Count Register Channel 0H . . . . . . . . . . . . . . . . DMA Byte Count Register Channel 1L . . . . . . . . . . . . . . . . . DMA Byte Count Register Channel 0H . . . . . . . . . . . . . . . .
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56 57 60 62 65 68 68 69 69 70 70 72 72 74 75 75 76 76 77 78 78 79 79 80 80 81 81 82 82 83 83
Table of Contents
Z80180 Microprocessor Unit v
DMA Memory Address Register Channel 1 . . . . . . . . . . . . . . . . 83 DMA Memory Address Register, Channel 1L . . . . . . . . . . . 84 DMA Memory Address Register, Channel 1H . . . . . . . . . . . 84 DMA I/O Address Register Channel 1 . . . . . . . . . . . . . . . . . . . . 85 DMA I/O Address Register Channel 1L . . . . . . . . . . . . . . . . 86 DMA I/O Address Register Channel 1H . . . . . . . . . . . . . . . . 86 DMA I/O Address Register Channel 1B . . . . . . . . . . . . . . . . 87 DMA Status Register (DSTAT) . . . . . . . . . . . . . . . . . . . . . . 87 Mnemonic DSTAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 DMA Mode Register (DMODE) . . . . . . . . . . . . . . . . . . . . . . 89 Mnemonic DMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 DMA/WAIT Control Register (DCNTL) . . . . . . . . . . . . . . . . . . . . 92 Interrupt Vector Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Mnemonic: IL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Int/TRAP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Mnemonics ITC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Refresh Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Mnemonic RCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 MMU Common Base Register . . . . . . . . . . . . . . . . . . . . . . . . . 101 Mnemonic CBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 MMU Bank Base Register (BBR) . . . . . . . . . . . . . . . . . . . . . . . 102 Mnemonic BBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 MMU Common/Bank Area Register (CBAR) . . . . . . . . . . . . . . 103 Mnemonic CBAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Operation Mode Control Register . . . . . . . . . . . . . . . . . . . . . . 104 Mnemonic OMCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 I/O Control Register (ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table of Contents
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Z80180 Microprocessor Unit vi
PS014002-0403
Table of Contents
Z80180 Microprocessor Unit vii
List of Figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23.
List of Figures
Z80180 Functional Block Diagram . . . . . . . . . . . . . . . 3 Z80180 64-Pin Dip Configuration . . . . . . . . . . . . . . . . 4 Z80180 68-Pin PLCC Configuration . . . . . . . . . . . . . . 5 Z80180 80-Pin QFP Configuration . . . . . . . . . . . . . . . 6 Timer Initialization, Count Down, and Reload Timing 19 Timer Data Register . . . . . . . . . . . . . . . . . . . . . . . . . 20 CSIO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 21 Operating Control Register (OMCR: I/O Address = 3Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . 22 RETI Instruction Sequence with MIE = 0 . . . . . . . . . 23 M1 Temporary Enable Timing . . . . . . . . . . . . . . . . . 24 I/O READ and Write Cycles with IOC = 1 . . . . . . . . . 24 I/O READ and Write Cycles with IOC = 0 . . . . . . . . . 25 HALT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SLEEP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 AC Load Capacitance Parameters . . . . . . . . . . . . . . 29 CPU Timing (Op Code Fetch, I/O Write, and I/O Read Cycles) 44 CPU Timing (INT0 Acknowledge Cycle, Refresh Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 CPU Timing (IOC = 0) (I/O Read Cycle, I/O Write Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 DMA Control Signals . . . . . . . . . . . . . . . . . . . . . . . . 47 E Clock Timing (Memory R/W Cycle, I/O R/W Cycle) 48 E Clock Timing (Bus Release, Sleep, System Stop Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 E Clock Timing (PWEL and PWEH Minimum Timing) . 49 Timer Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . 49
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Z80180 Microprocessor Unit viii
Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53.
SLEEP Execution Cycle . . . . . . . . . . . . . . . . . . . . . . . 50
CSIO Receive/Transmit Timing . . . . . . . . . . . . . . . . Rise Time and Fall Times . . . . . . . . . . . . . . . . . . . . . ASCI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . ASCI Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ASCI Receive Register Channel 0 . . . . . . . . . . . . . . ASCI Receive Register Channel 1R . . . . . . . . . . . . . ASCI Channel Control Register A . . . . . . . . . . . . . . ASCI Channel Control Register B . . . . . . . . . . . . . . ASCI Status Registers . . . . . . . . . . . . . . . . . . . . . . . CSIO Control Register . . . . . . . . . . . . . . . . . . . . . . . ASCI Receive Register Channel 1R . . . . . . . . . . . . . ASCI Receive Register Channel 1R . . . . . . . . . . . . . Timer Data Register Channel High . . . . . . . . . . . . . . Timer Reload Register Low . . . . . . . . . . . . . . . . . . . Timer Reload Register . . . . . . . . . . . . . . . . . . . . . . . Timer Control Register (TCR: I/O Address = 10h) . . ASCI Extension Control Registers, Channel 0 and 1 Timer Data Register . . . . . . . . . . . . . . . . . . . . . . . . . Timer Data Register . . . . . . . . . . . . . . . . . . . . . . . . . Timer Data Register . . . . . . . . . . . . . . . . . . . . . . . . . Timer Data Register . . . . . . . . . . . . . . . . . . . . . . . . . Timer Data Register . . . . . . . . . . . . . . . . . . . . . . . . . DMA Channel 0L . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Channel 0H . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Channel 0B . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Destination Address Register Channel 0L . . . . DMA Destination Address Register Channel 0H . . . DMA Destination Address Register Channel 0B . . .
51 52 52 54 56 56 57 60 63 65 68 68 69 69 70 70 72 74 75 75 76 77 78 78 79 80 80 81
Figure 29. ASCI Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
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List of Figures
Z80180 Microprocessor Unit ix
Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78.
List of Figures
DMA Byte Count Register 0L . . . . . . . . . . . . . . . . . . 82 DMA Byte Count Register 0H . . . . . . . . . . . . . . . . . . 82 DMA Byte Count Register 1L . . . . . . . . . . . . . . . . . . 83 DMA Byte Count Register 0H . . . . . . . . . . . . . . . . . . 83 DMA Memory Address Register, Channel 1L . . . . . . 84 DMA Memory Address Register, Channel 1H . . . . . 84 DMA Memory Address Register, Channel 1B . . . . . 85 IAR MS Byte Register (IARIB: I/O Address 2Dh . . . 85 DMA I/O Address Register Channel 1L . . . . . . . . . . 86 DMA I/O Address Register Channel 1H . . . . . . . . . . 86 DMA I/O Address Register Channel 1B . . . . . . . . . . 87 DMA Status Register (DSTAT: I/O Address = 30h) . 87 DMA Mode Register (DMODE: I/O Address = 31h) . 90 DMA/WAIT Control Register (DCNTL: I/O Address = 32h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Interrupt Vector Low Register (IL: I/O Address = 33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Int/TRAP Control Register . . . . . . . . . . . . . . . . . . . . 95 TRAP Timing--2nd Op Code Undefined . . . . . . . . . 97 TRAP Timing--3rd Op Code Undefined . . . . . . . . . . 98 Refresh Control Register (RCA: I/O Address = 36h) 99 MMU Bank Base Register (BBR: I/O Address = 39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 MMU Bank Base Register (BBR: I/O Address = 39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 MMU Common/Bank Area Register (CBAR: I/O Address = 3 AH . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Operating Control Register(OMCR: I/O Address = 3Eh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 RETI Instruction Sequence with MIE=0 . . . . . . . . . 105 I/O Control Register (ICR: I/O Address = 3Fh) . . . . 106
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Z80180 Microprocessor Unit x
Figure 79. Figure 80. Figure 81. Figure 82.
I/O Address Relocation . . . . . . . . . . . . . . . . . . . . . 80-Pin QFP Package Diagram . . . . . . . . . . . . . . . . 64-Pin DIP Package Diagram . . . . . . . . . . . . . . . . . 68-Pin PLCC Package Diagram . . . . . . . . . . . . . . .
107 108 109 110
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List of Figures
Z80180 Microprocessor Unit xi
List of Tables
Table 1. Power Connection Conventions . . . . . . . . . . . . . . . . . . . 2 Table 2. Pin Status During RESET BUSACK and SLEEP . . . . . . 7 Table 3. Status Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 4. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . 30 Table 5. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 6. Z80180-6 AC Characteristics . . . . . . . . . . . . . . . . . . . . 32 Table 7. Z80180-8 AC Characteristics . . . . . . . . . . . . . . . . . . . . 35 Table 8. Z80180-10 AC Characteristics . . . . . . . . . . . . . . . . . . . 39 Table 9. ASCI Data Formats Mode 2, 1, 0 . . . . . . . . . . . . . . . . . 59 Table 10. Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 11. Divide Ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 12. CSIO Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . 67 Table 13. Timer Output Control. . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 14. DMA Transfer Requests . . . . . . . . . . . . . . . . . . . . . . . 81 Table 15. Channel 0 Destination. . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 16. Channel 0 Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 17. Channel 1 Transfer Mode . . . . . . . . . . . . . . . . . . . . . . 94 Table 18. DRAM Refresh Intervals . . . . . . . . . . . . . . . . . . . . . . 100 Table 19. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 111
List of Tables
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Z80180 Microprocessor Unit xii
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List of Tables
Z80180 Microprocessor Unit
1
Overview
Features * * * * * * * * * * * * * * * *
Code Compatible with ZiLOG Z80(R) CPU Extended Instructions Two DMA Channels Low Power-Down Modes On-chip Interrupt Controllers Three On-Chip Wait-State Generators On-Chip Oscillator/Generator Expanded MMU Addressing (up to 1 MB) Clocked Serial I/O Port Two 16-Bit Counter/Timers Two UARTs Clock Speeds: 6, 8, and 10 MHz 6-MHz version supports 6.144-MHz CPU Clock Operation Operating Range: 5V Operating Temperature Range: 0C to +70C Three Packaging Styles - 68-Pin PLCC - 64-Pin DIP - 80-Pin QFP
PS014003-0603
Functional Description
Z80180 Microprocessor Unit
2
General Description
The Z80180TM is an 8-bit Microprocessor Unit (MPU) which provides the benefits of reduced system costs while also providing full backward compatibility with existing ZiLOG Z80 devices. Reduced system costs are obtained by incorporating several key system functions on-chip with the CPU. These key functions include I/O devices such as DMA, UART, and timer channels. Also included on-chip are wait-state generators, a clock oscillator, and an interrupt controller. The Z80180 is housed in 80-pin QFP, 68-pin PLCC, and 64-pin DIP packages. Note: All Signals with an overline are active Low. For example, B/W, in which WORD is active Low); and B/W, in which BYTE is active Low. Power connections follow conventional descriptions as shown in Table 1.
Table 1. Power Connection Conventions Connection Power Ground Circuit VCC GND Device VDD VSS
PS014003-0603
Functional Description
Z80180 Microprocessor Unit
3
16-Bit Address Bus Processor Power Controller 8-Bit Data Bus DMACs (2) MMU Decode A B B
Clocked Serial I/O
16-Bit Programmable Reload Timers (2)
UARTs (2)
TXA1-0 RXA1-0
Figure 1. Z80180 Functional Block Diagram
PS014003-0603
Functional Description
Z80180 Microprocessor Unit
4
Pin Configuration
VSS XTAL EXTAL WAIT BUSACK BUSREQ RESET NMI INT0 INT1 INT2 ST A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 VCC
1 64
Z80180 64-Pin
32
33
PHI RD WR M1 E MREQ IORQ RFSH HALT TEND1 DREQ1 CKS RXS/CTS1 TXS CKA1/TEND0 RXA1 TXA1 CKA/DREQ0 RXA0 TXA0 DCD0 CTS0 RTS0 D7 D6 D5 D4 D3 D2 D1 D0 VSS
Figure 2. Z80180 64-Pin Dip Configuration
PS014003-0603
Functional Description
Z80180 Microprocessor Unit
5
Z80180 68-Pin PLCC Pin Configuration
NMI RESET BUSREQ BUSACK WAIT EXTAL XTAL VSS 9 10
VSS PHI RD WR M1 E MREQ IORQ RFSH 1 61 60
INT0 INT1 INT2 ST A0 A1 A2 A3 VSS A4 A5 A6 A7 A8 A9 A10 A11
Z80180 68-Pin PLCC
26 27 A12 A13 A14 A15 A16 A17 A18/TOUT
44 43 VCC A19 VSS D0 D1 D2 D3 D4 D5 D6
HALT TENDi DREQi CKS RXS/CTS1 TXS CKA1/TEND0 RXA1 TEST TXA1 CKA0/DREQ0 RXA0 TXA0 DCD0 CTS0 RTS0 D7
Figure 3. Z80180 68-Pin PLCC Configuration
PS014003-0603
Functional Description
Z80180 Microprocessor Unit
6
IORQ MREQ E M1 WR RD PHI VSS VSS XTAL N/C EXTAL WAIT BUSACK BUSREQ RESET
65
RFSH N/C N/C HALT TEND1 DREQ1 CKS RXS/CTS1 TXS CKA1/TEND0 RXA1 TEST TXA1 N/C CKA0/DREQ0 RXA0 TXA0 DCD0 CTS0 RTS0 D7 N/C N/C D6
64 60 55 50 45 41
40
Z80180 80-Pin QFP
D5 D4 D3 D2 D1 D0 VSS A19 VCC A18/TOUT NC A17 A16 A15 A14 A13
1
5
10
15
20
24
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NMI N/C N/C INT0 INT1 INT2 ST A0 A1 A2 A3 VSS A4 N/C A5 A6 A7 A8 A9 A10 A11 N/C N/C A12
Figure 4. Z80180 80-Pin QFP Configuration
Functional Description
Z80180 Microprocessor Unit
7
Table 2. Pin Status During RESET BUSACK and SLEEP Pin Number and Package Type QFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 27 25 20 21 22 23 24 25 26 18 19 20 21 22 23 24 10 11 12 13 14 15 16 17 18 19 17 9 10 11 12 13 14 15 16 PLCC 9 DIP 8 Pin Status Secondary Function RESET BUSACK IN IN
Default Function NMI NC NC INT0 INT1 INT2 ST A0 A1 A2 A3 VSS A4 NC A5 A6 A7 A8 A9 A10 A11 NC NC A12
SLEEP IN
IN IN IN 1 3T 3T 3T 3T GND 3T 3T 3T 3T 3T 3T 3T 3T
IN IN IN ? 3T 3T 3T 3T GND 3T 3T 3T 3T 3T 3T 3T 3T
IN IN IN 1 1 1 1 1 GND 1 1 1 1 1 1 1 1
3T
3T
1
PS014003-0603
Functional Description
Z80180 Microprocessor Unit
8
Table 2. Pin Status During RESET BUSACK and SLEEP (continued) Pin Number and Package Type QFP 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 44 45 46 47 48 49 41 42 43 44 45 46 33 34 35 36 37 38 39 40 41 42 43 33 34 35 36 37 38 39 40 31 32 PLCC 28 29 30 31 32 DIP 26 27 28 29 30 Secondary Pin Status Function RESET BUSACK 3T 3T 3T 3T 3T TOUT 3T VCC 3T GND 3T 3T 3T 3T 3T 3T 3T 3T 3T 3T 3T 3T 3T VCC 3T GND 3T 3T 3T 3T 3T 3T 3T
Default Function A13 A14 A15 A16 A17 NC A18 VCC A19 VSS D0 D1 D2 D3 D4 D5 D6 NC NC D7 RTS0 CTS0 DCD0 TXA0 RXA0
SLEEP 1 1 1 1 1 1 VCC 1 GND 3T 3T 3T 3T 3T 3T 3T
3T 1 IN IN 1 IN
3T OUT OUT IN OUT IN
3T 1 IN IN OUT IN
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Table 2. Pin Status During RESET BUSACK and SLEEP (continued) Pin Number and Package Type QFP 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 61 62 63 64 65 66 67 68 1 2 3 2 57 58 59 60 61 62 63 64 1 51 52 53 54 55 56 57 58 59 60 49 50 51 52 53 54 55 56 48 PLCC 50 DIP 47 Secondary Pin Status Function RESET BUSACK DREQ0 3T 1 IN TEND0 CTS1 3T 1 IN 3T IN 1 1 OUT OUT IN IN OUT IN I/O 3T OUT 1
Default Function CKA0 NC TXA1 TEST RXA1 CKA1 TXS RXS CKS DREQ1 TEND1 HALT NC NC RFSH IORQ MREQ E M1 WR RD PHI VSS VSS XTAL
SLEEP OUT OUT IN IN OUT IN I/O IN 1 0
1 1 1 0 1 1 1 OUT GND GND OUT
OUT 3T 3T OUT 1 3T 3T OUT GND GND OUT
OUT 1 1 OUT 1 1 1 OUT GND GND OUT
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Table 2. Pin Status During RESET BUSACK and SLEEP (continued) Pin Number and Package Type QFP 75 76 77 78 79 80 4 5 6 7 8 3 4 5 6 7 PLCC DIP Secondary Pin Status Function RESET BUSACK IN IN 1 IN IN IN IN OUT IN IN
Default Function NC EXTAL WAIT BUSACK BUSREQ RESET
SLEEP IN IN OUT IN IN
Pin Descriptions
A0-A19. Address Bus (output, active High, 3-state). A0-A19 form a 20-bit address bus. The Address Bus provides the address for memory data bus exchanges, up to 1 MB, and I/O data bus exchanges, up to 64 KB. The address bus enters a high-impedance state during reset and external bus acknowledge cycles. Address line A18 is multiplexed with the output of PRT channel 1 (TOUT, selected as address output on reset) and address line A19 is not available in DIP versions of the Z80180.
BUSACK. Bus Acknowledge (output, active Low). BUSACK indicates the requesting device, the MPU address and data bus, and some control signals that enter their high-impedance state. BUSREQ. Bus Request (input, active Low). This input is used by
external devices (such as DMA controllers) to request access to the system bus. This request demands a higher priority than NMI and is always recognized at the end of the current machine cycle. This signal stops the CPU from executing further instructions and
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places address and data buses, and other control signals, into the high-impedance state.
CKA0, CKA1. Asynchronous Clock 0 and 1 (bidirectional, active
High). When in output mode, these pins are the transmit and receive clock outputs from the ASCI baud rate generators. When in input mode, these pins serve as the external clock inputs for the ASCI baud rate generators. CKA0 is multiplexed with DREQ0, and CKA1 is multiplexed with TEND0.
CKS. Serial Clock (bidirectional, active High). This line is the clock for the CSIO channel. CLOCK. System Clock (output, active High). The output is used as
a reference clock for the MPU and the external system. The frequency of this output is equal to one-half that of the crystal or input clock frequency.
CTS0-CTS1. Clear to send 0 and 1 (inputs, active Low). These lines are modem control signals for the ASCI channels. CTS1 is multiplexed with RXS. D0-D7. Data Bus (bidirectional, active High, 3-state). D0-D7 constitute an 8-bit bidirectional data bus, used for the transfer of information to and from I/O and memory devices. The data bus enters the high-impedance state during reset and external bus acknowledge cycles. DCD0. Data Carrier Detect 0 (input, active Low). A programmable modem control signal for ASCI channel 0.
DREQ0, DREQ1. DMA Request 0 and 1 (input, active Low). DREQ is used to request a DMA transfer from one of the on-chip DMA channels. The DMA channels monitor these inputs to determine when an external device is ready for a READ or WRITE operation. These inputs can be programmed to be either level or edge sensed. DREQ0 is multiplexed with CKA0.
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E. Enable Clock (output, active High). Synchronous machine cycle
clock output during bus transactions.
EXTAL. External Clock Crystal (input, active High). Crystal oscilla-
tor connections. An external clock can be input to the Z80180 on this pin when a crystal is not used. This input is Schmitt-triggered.
HALT. HALT/SLEEP (output, active Low). This output is asserted after the CPU executes either the HALT or SLEEP instruction, and
is waiting for either nonmaskable or maskable interrupt before operation can resume. It is also used with the M1 and ST signals to decode status of the CPU machine cycle.
INT0. Maskable Interrupt Request 0 (input, active Low). This signal
is generated by external I/O devices. The CPU honors these requests at the end of the current instruction cycle as long as the NMI and BUSREQ signals are inactive. The CPU acknowledges this interrupt request with an interrupt acknowledge cycle. During this cycle, both the M1 and IORQ signals become active.
INT1, INT2. Maskable Interrupt Request 1 and 2 (inputs, active
Low). This signal is generated by external I/O devices. The CPU honors these requests at the end of the current instruction cycle as long as the NMI, BUSREQ, and INT0 signals are inactive. The CPU acknowledges these requests with an interrupt acknowledge cycle. Unlike the acknowledgment for INT0, during this cycle neither the M1 or IORQ signals become active.
IORQ. I/O Request (output, active Low, 3-state). IORQ indicates that the address bus contains a valid I/O address for an I/O READ or I/O WRITE operation. IORQ is also generated, along with M1, during the acknowledgment of the INT0 input signal to indicate that an interrupt response vector can be placed onto the data bus. This signal is analogous to the IOE signal of the Z64180. M1. Machine Cycle 1 (output, active Low). Together with MREQ, M1 indicates that the current cycle is the op code fetch cycle of and
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instruction execution. Together with IORQ, M1 indicates that the current cycle is for an interrupt acknowledge. It is also used with the HALT and ST signal to decode status of the CPU machine cycle. This signal is analogous to the LIR signal of the Z64180.
MREQ. Memory Request (output, active Low, 3-state). MREQ indicates that the address bus holds a valid address for a memory READ or memory WRITE operation. This signal is analogous to the ME signal of Z64180. NMI. Nonmaskable Interrupt (input, negative edge triggered). NMI demands a higher priority than INT and is always recognized at the
end of an instruction, regardless of the state of the interrupt enable flip-flops. This signal forces CPU execution to continue at location
0066h. RD. Op Code Reinitialized (output, active Low, 3-state). RD indi-
cated that the CPU wants to read data from memory or an I/O device. The addressed I/O or memory device should use this signal to gate data onto the CPU data bus.
RFSH. Refresh (output, active Low). Together with MREQ, RFSH
indicates that the current CPU machine cycle and the contents of the address bus should be used for refresh of dynamic memories. The low order 8 bits of the address bus (A7-A10) contain the refresh address. This signal is analogous to the REF signal of the Z64180.
RTS0. Request to Send 0 (output, active Low). A programmable modem control signal for ASCI channel 0. RXA0, RXA1. Receive Data 0 and 1 (input, active High). These sig-
nals are the receive data to the ASCI channels.
RXS. Clocked Serial Receive Data (input, active High). This line is the receiver data for the CSIO channel. RXS is multiplexed with the CTS1 signal for ASCI channel 1.
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ST. Status (output, active High). This signal is used with the M1 and HALT output to decode the status of the CPU machine cycle. Table 3. Status Summary ST 0 1 1 0 0 1 HALT 1 1 1 X 0 0 M1 0 0 1 1 0 1 Operation CPU Operation (1st op code fetch) CPU Operation (2nd op code and 3rd op code fetch) CPU Operation(MC except for op code fetch) DMA Operation HALT Mode SLEEP Mode (including SYSTEM STOP Mode)
Notes: X = Reserved. MC = Machine Cycle.
TEND0, TEND1. Transfer End 0 and 1 (outputs, active Low). This output is asserted active during the most recent WRITE cycle of a
DMA operation. It is used to indicate the end of the block transfer.
TEND0 is multiplexed with CKA1. TEST. Test (output, not in DIP version). This pin is for test and
should be left open.
TOUT. Timer Out (output, active High). TOUT is the pulse output
from PRT channel 1. This line is multiplexed with A18 of the address bus.
TXA0, TXA1. Transmit Data 0 and 1 (outputs, active High). These signals are the transmitted data from the ASCI channels. Transmitted data changes are with respect to the falling edge of the transmit clock. TXS. Clocked Serial Transmit Data (output, active High). This line
is the transmitted data from the CSIO channel.
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WAIT. Wait (input, active Low). WAIT indicated to the MPU that the
addressed memory or I/O devices are not ready for a data transfer. This input is sampled on the falling edge of T2 (and subsequent wait states). If the input is sampled Low, then the additional wait states are inserted until the WAIT input is sampled high, at which time execution continues.
WR. WRITE (output, active Low, 3-state). WR indicated that the
CPU data bus holds valid data to be stored at the addressed I/O or memory location.
XTAL. Crystal (input, active High). Crystal oscillator connection.
This pin should be left open if an external clock is used instead of a crystal. The oscillator input is not a TTL level (see DC Characteristics). Several pins are used for different conditions, depending on the circumstance.
Multiplexed Pin Descriptions
Table 4: Multiplexed Pin Descriptions
Pin A18/TOUT Description During RESET, this pin is initialized as A18 pin. If either TOC1 or TOC0 bit of the Timer Control Register (TCR) is set to 1, TOUT function is selected. If TOC1 and TOC0 are cleared to 0, A18 function is selected. During RESET, this pin is initialized as CKA0 pin. If either DM1 or SM1 in DMA Mode Register (DMODE) is set to 1, DREQ0 function is always selected. During RESET, this pin is initialized as CKA1 pin. If CKA1D bit in ASCI control register ch1 (CNTLA1) is set to 1, TEND0 function is selected. If CKA1D bit is set to 0, CKA1 function is selected.
CKA0/DREQ0
CKA1/TEND0
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Table 4: Multiplexed Pin Descriptions (continued)
RXS/CTS1 During RESET, this pin is initialized as RXS pin. If CTS1E bit in ASCI status register ch1 (STAT1) is set to 1, CTS1 function is selected. If CTS1E bit is set to 0, RXS function is selected.
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Architecture
The Z180(R) combines a high-performance CPU core with a variety of system and I/O resources useful in a broad range of applications. The CPU core consists of five functional blocks: clock generator, bus state controller, Interrupt controller, memory management unit (MMU), and the central processing unit (CPU). The integrated I/O resources make up the remaining four function blocks: direct memory access (DMA) control (2 channels), asynchronous serial communication interface (ASCI, 2 channels) programmable reload timers (PRT, 2 channels), and a clock serial I/O (CSIO) channel.
Clock Generator. Generates system clock from an external crystal or clock input. The external clock is divided by two or one and provided to both internal and external devices. Bus State Controller. This logic performs all of the status and bus
control activity associated with both the CPU and some on-chip peripherals. Included are wait-state timing, reset cycles, DRAM refresh, and DMA bus exchanges.
Interrupt Controller. This logic monitors and prioritizes the variety
of internal and external interrupts and traps to provide the correct responses from the CPU. To maintain compatibility with the Z80(R) CPU, three different interrupts modes are supported.
Memory Management Unit. The MMU allows the user to map the memory used by the CPU (logically only 64 KB) into the 1-MB addressing range supported by the Z80180. The organization of the MMU object code allows maintenance compatibility with the Z80 CPU, while offering access to an extended memory space. This organization is achieved by using an effective common areabanked area scheme.
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Central Processing Unit. The CPU is microcoded to provide a core
that is object-code compatible with the Z80 CPU. It also provides a superset of the Z80 instruction set, including 8-bit multiply. The core is modified to allow many of the instructions to execute in fewer clock cycles.
DMA Controller. The DMA controller provides high speed transfers
between memory and I/O devices. Transfer operations supported are memory-to-memory, memory to/from I/O, and I/O-to-I/O. Transfer modes supported are request, burst, and cycle steal. DMA transfers can access the full 1 MB address range with a block length up to 64 KB, and can cross over 64K boundaries.
Asynchronous Serial Communication Interface (ASC). The ASCI logic provides two individual full-duplex UARTs. Each channel includes a programmable baud rate generator and modem control signals. The ASCI channels can also support a multiprocessor communication format as well as break detection and generation. Programmable Reload Timers (PRT). This logic consists of two separate channels, each containing a 16-bit counter (timer) and count reload register. The time base for the counters is derived from the system clock (divided by 20) before reaching the counter. PRT channel 1 provides an optional output to allow for waveform generation.
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Timer Data Register WRITE (0004h) RESET Timer Data Register FFFFh 0004h
0 < t < 20 f 20 f 20 f
20 f
20 f
20 f
20 f
20 f
20 f
20 f
0003h 0002h
0001h 0000h 0003h 0002h 0001h 0000h 0003h
Timer Reload Register WRITE (0003h) Timer Reload Register FFFFh 0003h WRITE a 1 to TDE TDE Flag
Reload
Reload
TIF Flag
Timer Data Register READ Timer Control Requestor READ
Figure 5. Timer Initialization, Count Down, and Reload Timing
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f
Timer Data Timer Data Reg. = 0001h Reg. = 0000h
TOUT Figure 6. Timer Data Register
Clocked Serial I/O (CSIO). The CSIO channel provides a halfduplex serial transmitter and receiver. This channel can be used for simple high-speed data connection to another microprocessor or microcomputer. TRDR is used for both CSIO transmission and reception. The system design must ensure that the constraints of half-duplex operation are met. Transmit and Receive operations cannot occur simultaneously. For example, if a CSIO transmission is attempted while the CSIO is receiving data, a CSIO does not work. Note: TRDR is not buffered. Attempting to perform a CSIO transmit while the previous transmit data is still being shifted out causes the shift data to be immediately updated, corrupting the transmit operation in progress. Reading TRDR while a transmit or receive is in progress should be avoided.
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Internal Address/Data Bus f
TXS RXS
CSIO Transmit/Receive Data Register: TRDR (8) CSIO Control Register: CNTR (8)
Baud Rate Generator
CKS
Interrupt Request
Figure 7. CSIO Block Diagram
Operation Modes
Z80(R) versus 64180 Compatibility The Z80180 is descended from two different ancestor processors, ZiLOG's original Z80 and the Hitachi 64180. The Operating Mode Control Register (OMCR), illustrated in Figure 8, can be programmed to select between certain Z80 and 64180 differences.
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.
D7 D6 D5 -- -- -- -- -- Reserved IOC (R/W) M1TE (W) M1E (R/W) Figure 8. Operating Control Register (OMCR: I/O Address = 3Eh) M1E (M1 Enable) This bit controls the M1 output and is set to a 1 during RESET.
When M1E = 1, the M1 output is asserted Low during the op code fetch cycle, the INT0 acknowledge cycle, and the first machine cycle of the NMI acknowledge. On the Z80180, this choice makes the processor fetch a RETI instruction one time only, and when fetching a RETI from zero-waitstate memory uses three clock machine cycles, which are not fully Z80-timing compatible but are compatible with the on-chip CTCs. When M1E = 0, the processor does not drive M1 Low during instruction fetch cycles. After fetching a RETI instruction one time only, with normal timing, the processor goes back and refetches the instruction using fully Z80-compatible cycles that include driving M1 Low. Some external Z80 peripherals may require properly decoded RETI instructions. Figure 9 illustrates the RETI sequence when M1E
= 0.
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T1 f A0-A18 (A19) D0-D7 M1 MREQ RD ST
T2
T3
T1
T2
T3
TI
TI
TI
T1
T2
T3
TI
T1
T2
T3
TI
PC EDh 4Dh
PC+1
PC EDh
PC+1 4Dh
Figure 9. RETI Instruction Sequence with MIE = 0 M1TE (M1 Temporary Enable) This bit controls the temporary assertion of the M1 signal. It is always read back as a 1 and is set to 1 during RESET.
When M1E is set to 0 to accommodate certain external Z80 peripheral(s), those same device(s) may require a pulse on M1 after programming certain of their registers to complete the function being programmed. For example, when a control word is written to the Z80 PIO to enable interrupts, no enable actually takes place until the PIO sees an active M1 signal. When M1TE = 1, there is no change in the operation of the M1 signal and M1E controls its function. When M1TE = 0, the M1 output is asserted during the next op code fetch cycle regardless of the state programmed into the M1E bit. This instance is only momentary (one time only) and the user is not required to preprogram a 1 to disable the function (see Figure 10).
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T1 f WR M1
T2
T3
T1
T2
T3
WRITE into OMCR Op Code Fetch
Figure 10. M1 Temporary Enable Timing IOC This bit controls the timing of the IORQ and RD signals. It is set to 1 by RESET. When IOC = 1, the IORQ and RD signals function the same as the Z64180 (Figure 11). T1 f IORQ RD WR Figure 11. I/O READ and WRITE Cycles with IOC = 1 T2 TW T3
When IOC = 0, the timing of the IORQ and RD signals match the timing of the Z80. The IORQ and RD signals go active as a result of the rising edge of T2. (Figure 12.)
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T1 f IORQ RD WR
T2
TW
T3
Figure 12. I/O READ and WRITE Cycles with IOC = 0 HALT and Low-Power Operating Modes. The Z80180 can operate in five modes with respect to activity and power consumption:
* * * * *
Normal Operation
HALT mode IOSTOP mode SLEEP mode
SYSTEM STOP mode
Normal Operation. The Z80180 processor is fetching and running a program. All enabled functions and portions of the device are active, and the HALT pin is High. HALT Mode. This mode is entered by the HALT instruction. Thereafter, the Z80180 processor continually fetches the following op code but does not execute it, and drives the HALT, ST and M1 pins all Low. The oscillator and PHI pin remain active, interrupts and bus granting to external masters, and DRAM refresh can occur and all
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on-chip I/O devices continue to operate including the DMA channels. The Z80180 leaves HALT mode in response to a Low on RESET, on to an interrupt from an enabled on-chip source, an external request on NMI, or an enabled external request on INT0, INT1, or INT2. In case of an interrupt, the return address is the instruction following the HALT instruction; at that point the program can either branch back to the HALT instruction to wait for another interrupt, or can examine the new state of the system/application and respond appropriately.
HALT Op Code Fetch Cycle T2 f INTi, NMI A0-A19 HALT Op Code Address HALT M1 MREQ RD T3 T1
HALT Mode T2 T3
Interrupt Acknowledge Cycle T1 T2
HALT Op Code Address + 1
Figure 13. HALT Timing
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SLEEP Mode Enter SLEEP mode by keeping the IOSTOP bit (ICR5) bits 3 and 6 of the CPU Control Register (CCR3, CCR6) all zero and executing the SLEEP instruction. The oscillator and PHI output continue operating, but are blocked from the CPU core and DMA channels to reduce power consumption. DRAM refresh stops but interrupts and granting to external master can occur. Except when the bus is granted to an external master, A19-0 and all control signals except HALT are maintained High. HALT is Low. I/O operations continue as before the SLEEP instruction, except for the DMA channels. The Z80180 leaves SLEEP mode in response to a Low on RESET, an interrupt request from an on-chip source, an external request on NMI, or an external request on INT0, INT1, or INT2. If an interrupt source is individually disabled, it cannot bring the Z80180 out of SLEEP mode. If an interrupt source is individually enabled, and the IEF bit is 1 so that interrupts are globally enabled (by an EI instruction), the highest priority active interrupt occurs, with the return address being the instruction after the SLEEP instruction. If an interrupt source is individually enabled, but the IEF bit is 0 so that interrupts are globally disabled (by a DI instruction), the Z80180 leaves SLEEP mode by simply executing the following instruction(s). This provides a technique for synchronization with high- speed external events without incurring the latency imposed by an interrupt response sequence. Figure 14 shows the timing for exiting SLEEP mode due to an interrupt request. Note: The Z80180 takes about 1.5 clocks to restart.
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SLEEP 2nd Op Code Fetch Cycle T2 f INTi, NMI A0-A19 HALT M1 SLEEP 2nd Op Code Address T3 T1 T2
SLEEP Mode TS TS T1
Op Code Fetch or Interrupt Acknowledge Cycle T2 T3
FFFFFh
Figure 14. SLEEP Timing IOSTOP Mode. IOSTOP mode is entered by setting the IOSTOP bit of the I/O Control Register (ICR) to 1. In this case, on-chip I/O (ASCI, CSIO, PRT) stops operating. However, the CPU continues to operate. Recovery from IOSTOP mode is by resetting the IOSTOP bit in ICR to 0. SYSTEM STOP Mode. SYSTEM STOP mode is the combination of SLEEP and IOSTOP modes. SYSTEM STOP mode is entered by setting the IOSTOP bit in ICR to 1 followed by execution of the SLEEP
instruction. In this mode, on-chip I/O and CPU stop operating, reducing power consumption, but the PHI output continues to operate. Recovery from SYSTEM STOP mode is the same as recovery from SLEEP mode except that internal I/O sources (disabled by IOSTOP) cannot generate a recovery interrupt.
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Standard Test Conditions
The DC Characteristics section applies to the following standard test conditions, unless otherwise noted. All voltages are referenced to GND (0V). Positive current flows in to the referenced pin. All AC parameters assume a load capacitance of 100 pF. Add 10 ns delay for each 50 pF increase in load up to a maximum of 200 pF for the data bus and 100 pF for the address and control lines. AC timing measurements are referenced to 1.5 volts (except for CLOCK, which is referenced to the 10% and 90% points). The Ordering Information section lists temperature ranges and product numbers. Package drawings are in the Package Information section. See Figure 15.
+5 V 2.1k From Output Under Test
100 pF
250 m A
Figure 15. AC Load Capacitance Parameters
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Absolute Maximum Ratings
Table 5. Absolute Maximum Ratings Item Supply Voltage Input Voltage Operating Temperature Extended Temperature Storage Temperature Symbol VCC VIN Topr Text Tstg Value -0.3 ~ +7.0 -0.3 ~ VCC +0.3 0 ~ 70 -40 ~ 85 -55 ~ +150 Unit V V C C C
Note: Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating conditions. If these conditions are exceeded, it could affect reliability of LSI.
DC Characteristics
Table 6. DC Characteristics Sym. Item Condition VIH1 Input H Voltage RESET, EXTAL, NMI VIH2 Input H Voltage Except RESET, EXTAL, NMI Min. Typ. Max. Unit VCC -0.6 - VCC +0.3 V 2.0 - VCC +0.3 V
Note: *VIHmin = VCC -1.0V, VILmax = 0.8V (all output terminals are at no load); VCC = 5.0V. Note: VCC = 5V + 10%, VSS = 0V over specified temperature range, unless otherwise noted
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Table 6. DC Characteristics (continued) Sym. Item VIL1 Input L Voltage RESET, EXTAL, NMI VIL2 Input L Voltage Except RESET, EXTAL, NMI VOH Outputs H Voltage All outputs VOL IIL ITL ICC* Outputs L Voltage All outputs Input Leakage Current All Inputs Except XTAL, EXTAL Three State Leakage Current Power Dissipation* (Normal Operation) Power Dissipation* (SYSTEM STOP mode) CP Pin Capacitance Condition Min. -0.3 -0.3 IOH = -200A IOH = -20A IOL = -2.2A Typ. Max. - 0.6 - 0.8 - - 0.45 1.0 Unit V V V V A
2.4 - VCC -1.2 - - - -
VIN = 0.5 ~ VCC -0.5 - VIN = 0.5 ~ VCC -0.5 - F = 6 MHz F = 8 MHz F = 10 MHz** F = 6 MHz F = 8 MHz F = 10 MHz** VINVin = 0V, f = 1 MHzTA = 25 C - - - - - - -
- 15 20 25 3.8 5 6.3 -
1.0 40 50 60 12.5 15 17.5 12
A MA
pF
Note: *VIHmin = VCC -1.0V, VILmax = 0.8V (all output terminals are at no load); VCC = 5.0V. Note: VCC = 5V + 10%, VSS = 0V over specified temperature range, unless otherwise noted
AC Characteristics
Tables 7, 8, and 9 provide AC characteristics for the Z80180-6, Z80180-8, and Z80180-10 respectively. VCC = 5V + 10%, VSS = 0V, TA - 0C to +70C, unless otherwise noted.
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Table 7. Z80180-6 AC Characteristics Z80180-6 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol tcyc tCHW tCLW tcf tcr tAD tAS tMED1 tRDD1 tM1D1 tAH tMED2 tRDD2 tM1D2 tDRS tDRH tSTD1 tSTD2 tWS tWH Item Clock Cycle Time Clock H Pulse Width Clock L Pulse Width Clock Fall Time Clock Rise Time ORise to Address Valid Delay Address Valid to MREQ Fall or IORQ Fall) O Fall to MREQ Fall Delay O Fall to RD Fall Delay IOC = 1 O Rise to RD Rise Delay IOC = 0 O Rise to M1 Fall Delay Address Hold Time from (MREQ, IOREQ, RD, WR) O Fall to MREQ Rise Delay O Fall to RD Rise Delay O Rise to M1 Rise Delay Data Read Set-up Time Data Read Hold Time O Fall to ST Fall Delay O Fall to ST Rise Delay WAIT Set-up Time to O Fall WAIT Hold Time from O Fall Min. 162 65 65 - - - 30 - - - - 35 - - - 40 0 - - 40 40 Max. 2000 - - 15 15 90 - 60 60 65 80 - 60 60 80 - - 90 90 - - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Table 7. Z80180-6 AC Characteristics (continued) Z80180-6 No. 21 22 23 24 25 26 26a 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Symbol tWDZ tWRD1 tWDD tWDS tWRD2 tWRP tWDH tIOD1 tIOD2 tIOD3 tINTS tINTS tNMIW tBRS tBRH tBAD1 tBAD2 tBZD tMEWH tMEWL tRFD1 tRFD2 tHAD1 tHAD2 tDRQS tDRQH Item O Rise to Data Float Delay O Rise to WR Fall Delay O Fall to WRITE Data Delay Time WRITE Data Set-up Time to WR Fall O Fall to WR Rise Delay WR Pulse Width WR Pulse Width (I/O WRITE Cycle) WRITE Data Hold Time from (WR Rise) O Fall to IORQ Fall Delay IOC = 1 O Rise to IORQ Fall Delay IOC = 1 O Fall to IORQ Rise Delay M1 Fall to IORQFall Delay INT Set-up Time to O Fall INT Hold Time from O Fall NMI Pulse Width BUSREQ Set-up Time to O Fall BUSREQ Hold Time from O Fall O Rise to BUSACK Fall Delay O Fall to BUSACK Rise Delay O Rise to Bus Floating Delay Time MREQ Pulse Width (High) MREQ Pulse Width (Low) O Rise to RFSH Fall Delay O Rise to RFSHRise Delay O Rise to HALT Fall Delay O Rise to HALTRise Delay /DREQi Set-up Time to O Rise /DREQi Hold Time from O Rise Min. - - - 40 - 170 332 40 - - - 340 40 40 120 40 40 - - - 110 125 - - - - 40 40 Max. 95 65 90 - 80 - - - 60 65 60 - - - - - - 95 90 125 - - 90 90 90 90 - - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Functional Description
Z80180 Microprocessor Unit
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Table 7. Z80180-6 AC Characteristics (continued) Z80180-6 No. 47 48 49 50 51 52 53 54 55 56 57 Symbol tTED1 tTED2 tED1 tED2 PWEH PWEL tEr tEf tTOD tSTDI tSTDE tSRSI tSRHI tSRSE tSRHE tRES tREH tOSC tEXr tEXf tRr tRf Item O Fall to TENDi Fall Delay O Fall to TENDiRise Delay O Rise to E Rise Delay O Fall or Rise to E Fall Delay E Pulse Width (High) E Pulse Width (Low) Enable Rise Time Enable Fall Time O Fall to Timer Output Delay CSIO Transmit Data Delay Time (Internal Clock Operation) CSIO Transmit Data Delay Time (External Clock Operation) CSIO Receive Data Set-up Time (Internal Clock Operation) CSIO Receive Data Hold Time (Internal Clock Operation) CSIO Receive Data Set-up Time (External Clock Operation) CSIO Receive Data Hold Time (External Clock Operation) RESET Set-up Time to O Fall RESET Hold Time from O Fall Oscillator Stabilization Time External Clock Rise Time (EXTAL) External Clock Fall Time (EXTAL) RESET Rise Time RESET Fall Time Min. - - - - 75 180 - - - - - Max. 70 70 95 95 - - 20 20 300 200 Unit ns ns ns ns ns ns ns ns ns ns
58 59 60 61 62 63 64 65 66 67 68
1 1 1 1 120 80 - - - - -
7.5tcy ns c +300 - tcyc - - - - - 20 25 25 50 50 tcyc tcyc tcyc ns ns ns ns ns ns ns
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Functional Description
Z80180 Microprocessor Unit
35
Table 7. Z80180-6 AC Characteristics (continued) Z80180-6 No. Symbol Item 69 tIr Input Rise Time (except EXTAL, RESET) Input Fall Time (except EXTAL, RESET) 70 tIf Min. - - Max. 100 100 Unit ns ns
Table 8. Z80180-8 AC Characteristics Z80180-8 No. Symbol Item 1 2 3 4 5 6 7 8 9 10 11 12 13 tcyc tCHW tCLW tcf tcr tAD tAS tMED1 tRDD1 tM1D1 tAH tMED2 tRDD2 Clock Cycle Time Clock H Pulse Width Clock L Pulse Width Clock Fall Time Clock Rise Time ORise to Address Valid Delay Address Valid to MREQ Fall or IORQ Fall) O Fall to MREQ Fall Delay O Fall to RD Fall Delay O Rise to RD Rise Delay O Rise to M1 Fall Delay Address Hold Time from (MREQ, IOREQ, RD, WR) O Fall to MREQ Rise Delay O Fall to RD Rise Delay IOC = 1 IOC = 0 Min. 125 50 50 - - - 20 - - - - 20 - - Max. Unit 2000 ns - - 15 15 80 - 50 50 60 70 - 50 50 ns ns ns ns ns ns ns ns ns ns ns ns
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Functional Description
Z80180 Microprocessor Unit
36
Table 8. Z80180-8 AC Characteristics (continued) Z80180-8 No. Symbol Item 14 15 16 17 18 19 20 21 22 23 24 25 26 26a 27 28 29 30 31 32 tWDH tIOD1 tIOD2 tIOD3 tINTS tINTS tM1D2 tDRS tDRH tSTD1 tSTD2 tWS tWH tWDZ tWRD1 tWDD tWDS tWRD2 tWRP O Rise to M1 Rise Delay Data Read Set-up Time Data Read Hold Time O Fall to ST Fall Delay O Fall to ST Rise Delay WAIT Set-up Time to O Fall WAIT Hold Time from O Fall O Rise to Data Float Delay O Rise to WR Fall Delay O Fall to WRITE Data Delay Time WRITE Data Set-up Time to WR Fall O Fall to WR Rise Delay WR Pulse Width WR Pulse Width (I/O WRITE Cycle) WRITE Data Hold Time from (WR Rise) O Fall to IORQ Fall Delay O Rise to IORQ Fall Delay O Fall to IORQ Rise Delay M1 Fall to IORQFall Delay INT Set-up Time to O Fall INT Hold Time from O Fall IOC = 1 IOC = 1 Min. - 30 0 - - 40 40 - - - 20 - 130 255 15 - - - 250 40 40 Max. Unit 70* - - 70 70 - - 70 60 80 - 60 - - - 50 60 50 - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Functional Description
Z80180 Microprocessor Unit
37
Table 8. Z80180-8 AC Characteristics (continued) Z80180-8 No. Symbol Item 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 tNMIW tBRS tBRH tBAD1 tBAD2 tBZD tMEWH tMEWL tRFD1 tRFD2 tHAD1 tHAD2 tDRQS tDRQH tTED1 tTED2 tED1 tED2 PWEH PWEL tEr NMI Pulse Width BUSREQ Set-up Time to O Fall BUSREQ Hold Time from O Fall O Rise to BUSACK Fall Delay O Fall to BUSACK Rise Delay O Rise to Bus Floating Delay Time MREQ Pulse Width (High) MREQ Pulse Width (Low) O Rise to RFSH Fall Delay O Rise to RFSHRise Delay O Rise to HALT Fall Delay O Rise to HALTRise Delay /DREQi Set-up Time to O Rise /DREQi Hold Time from O Rise O Fall to TENDi Fall Delay O Fall to TENDiRise Delay O Rise to E Rise Delay O Fall or Rise to E Fall Delay E Pulse Width (High) E Pulse Width (Low) Enable Rise Time Min. 100 40 40 - - - 90 100 - - - - 40 40 - - - - 65 130 - 70 70 90 - - 80 80 80 80 - - 60 60 70 70 - - 20 Max. Unit - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Functional Description
Z80180 Microprocessor Unit
38
Table 8. Z80180-8 AC Characteristics (continued) Z80180-8 No. Symbol Item 54 55 56 57 tEf tTOD tSTDI tSTDE Enable Fall Time O Fall to Timer Output Delay CSIO Transmit Data Delay Time (Internal Clock Operation) CSIO Transmit Data Delay Time (External Clock Operation) CSIO Receive Data Set-up Time (Internal Clock Operation) CSIO Receive Data Hold Time (Internal Clock Operation) CSIO Receive Data Set-up Time (External Clock Operation) CSIO Receive Data Hold Time (External Clock Operation) RESET Set-up Time to O Fall RESET Hold Time from O Fall Oscillator Stabilization Time External Clock Rise Time (EXTAL) External Clock Fall Time (EXTAL) RESET Rise Time RESET Fall Time Input Rise Time (except EXTAL, RESET) Min. - - - - Max. Unit 20 200 200 ns ns ns
7.5tcy ns c +200 - - - - - - 20 25 25 50 50 100 tcyc tcyc tcyc tcyc ns ns ns ns ns ns ns ns
58 59 60 61 62 63 64 65 66 67 68 69
tSRSI tSRHI tSRSE tSRHE tRES tREH tOSC tEXr tEXf tRr tRf tIr
1 1 1 1 100 70 - - - - - -
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Functional Description
Z80180 Microprocessor Unit
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Table 8. Z80180-8 AC Characteristics (continued) Z80180-8 No. Symbol Item 70 tIf Input Fall Time (except EXTAL, RESET) Min. - Max. Unit 100 ns
Table 9. Z80180-10 AC Characteristics Z80180-10 No. Symbol Item 1 2 3 4 5 6 7 8 9 10 11 12 13 tcyc tCHW tCLW tcf tcr tAD tAS tMED1 tRDD1 tM1D1 tAH tMED2 tRDD2 Clock Cycle Time Clock H Pulse Width Clock L Pulse Width Clock Fall Time Clock Rise Time ORise to Address Valid Delay Address Valid to MREQ Fall or IORQ Fall) O Fall to MREQ Fall Delay O Fall to RD Fall Delay O Rise to RD Rise Delay O Rise to M1 Fall Delay Address Hold Time from (MREQ, IOREQ, RD, WR) O Fall to MREQ Rise Delay O Fall to RD Rise Delay IOC = 1 IOC = 0 Min. 100 40 40 - - - 10 - - - - 10 - - Max. 2000 - - 10 10 70 - 50 50 55 60 - 50 50 ns ns ns ns Unit ns ns ns ns ns ns ns ns ns
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Functional Description
Z80180 Microprocessor Unit
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Table 9. Z80180-10 AC Characteristics (continued) Z80180-10 No. Symbol Item 14 15 16 17 18 19 20 21 22 23 24 25 26 26a 27 28 29 30 31 32 tWDH tIOD1 tIOD2 tIOD3 tINTS tINTS tM1D2 tDRS tDRH tSTD1 tSTD2 tWS tWH tWDZ tWRD1 tWDD tWDS tWRD2 tWRP O Rise to M1 Rise Delay Data Read Set-up Time Data Read Hold Time O Fall to ST Fall Delay O Fall to ST Rise Delay WAIT Set-up Time to O Fall WAIT Hold Time from O Fall O Rise to Data Float Delay O Rise to WR Fall Delay O Fall to WRITE Data Delay Time WRITE Data Set-up Time to WR Fall O Fall to WR Rise Delay WR Pulse Width WR Pulse Width (I/O WRITE Cycle) WRITE Data Hold Time from (WR Rise) O Fall to IORQ Fall Delay O Rise to IORQ Fall Delay O Fall to IORQ Rise Delay M1 Fall to IORQFall Delay INT Set-up Time to O Fall INT Hold Time from O Fall IOC = 1 IOC = 1 Min. - 25 0 - - 30 30 - - - 15 - 110 210 10 - - - 200 30 30 Max. 60 - - 60 60 - - 60 50 60 - 50 - - - 50 55 50 - - - ns ns ns ns ns Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Functional Description
Z80180 Microprocessor Unit
41
Table 9. Z80180-10 AC Characteristics (continued) Z80180-10 No. Symbol Item 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 tNMIW tBRS tBRH tBAD1 tBAD2 tBZD tMEWH tMEWL tRFD1 tRFD2 tHAD1 tHAD2 tDRQS tDRQH tTED1 tTED2 tED1 tED2 PWEH PWEL tEr NMI Pulse Width BUSREQ Set-up Time to O Fall BUSREQ Hold Time from O Fall O Rise to BUSACK Fall Delay O Fall to BUSACK Rise Delay O Rise to Bus Floating Delay Time MREQ Pulse Width (High) MREQ Pulse Width (Low) O Rise to RFSH Fall Delay O Rise to RFSHRise Delay O Rise to HALT Fall Delay O Rise to HALTRise Delay /DREQi Set-up Time to O Rise /DREQi Hold Time from O Rise O Fall to TENDi Fall Delay O Fall to TENDiRise Delay O Rise to E Rise Delay O Fall or Rise to E Fall Delay E Pulse Width (High) E Pulse Width (Low) Enable Rise Time Min. 80 30 30 - - - 70 80 - - - - 30 30 - - - - 55 110 - 60 60 80 - - 60 60 50 50 - - 50 50 60 60 - - 20 Max. - - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Functional Description
Z80180 Microprocessor Unit
42
Table 9. Z80180-10 AC Characteristics (continued) Z80180-10 No. Symbol Item 54 55 56 57 tEf tTOD tSTDI tSTDE Enable Fall Time O Fall to Timer Output Delay CSIO Transmit Data Delay Time (Internal Clock Operation) CSIO Transmit Data Delay Time (External Clock Operation) CSIO Receive Data Set-up Time (Internal Clock Operation) CSIO Receive Data Hold Time (Internal Clock Operation) CSIO Receive Data Set-up Time (External Clock Operation) CSIO Receive Data Hold Time (External Clock Operation) RESET Set-up Time to O Fall RESET Hold Time from O Fall Oscillator Stabilization Time External Clock Rise Time (EXTAL) External Clock Fall Time (EXTAL) RESET Rise Time RESET Fall Time Input Rise Time (except EXTAL, RESET) Min. - - - - Max. 20 150 150 Unit ns ns ns
7.5tcy ns c +150 - - - - - - TBD 25 25 50 50 100 tcyc tcyc tcyc tcyc ns ns ns ns ns ns ns ns
58 59 60 61 62 63 64 65 66 67 68 69
tSRSI tSRHI tSRSE tSRHE tRES tREH tOSC tEXr tEXf tRr tRf tIr
1 1 1 1 80 50 - - - - - -
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Functional Description
Z80180 Microprocessor Unit
43
Table 9. Z80180-10 AC Characteristics (continued) Z80180-10 No. Symbol Item 70 tIf Input Fall Time (except EXTAL, RESET) Min. - Max. 100 Unit ns
Timing Diagrams
Z80180 Timing signals are shown in Figure 16 through Figure 27.
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Functional Description
Z80180 Microprocessor Unit
44
I/O Write Cycle* I/O Read Cycle* T1 T2 TW T3 T1
Opcode Fetch Cycle T1
2 3
T2
5
TW
T3
PHI ADDRESS WAIT
4 6 1
19
20
19
20
7
MREQ
8
12 11
7 11 13 28
29 11
IORQ
13
RD
9
9
11 22 26 25
WR
14
M1
10 17 15 16 18 15 16 21
ST
Data IN
23 24 27
Data OUT
62
RESET
68
63
62
63
67
67
68
Figure 16. CPU Timing (Op Code Fetch, I/O WRITE, and I/O READ Cycles)
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Functional Description
Z80180 Microprocessor Unit
45
o 31 INTi 32
33 NMI
MI *1
10 IORQ *1
30 28
14
15 16 Date IN *1
29
39 MREQ *2 41 RFSH *2 40 42
34 BUSREQ
35
34
35
36 BUSACK
37
38 ADDRESS DATA MREQ, RD WR, IORQ 43 HALT *3
38
44
Figure 17. CPU Timing (INT0 Acknowledge Cycle, Refresh Cycle)
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Functional Description
Z80180 Microprocessor Unit
46
CPU Timin= 0) (I/O READ Cycle, I/O WRITE Cycle)
I/O READ Cycle
I/O WRITE Cycle
T1 f ADDRESS
T2
Tw
T3
T1
T2
Tw
T3
28 IROQ 9 RD
29
28
29
13
22 WR
25
CPU Timing (IOC=0)
I/O READ Cycle I/O WRITE Cycle
Figure 18. CPU Timing (IOC = 0) (I/O READ Cycle, I/O WRITE Cycle)
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Functional Description
Z80180 Microprocessor Unit
47
DMA Control Signals
CPU or DMA READ/WRITE Cycle (Only DMA WRITE Cycle for TENDi) T1 o 45 DREQi (at level sense) *2 46 *1 46 T2 TW T3 T1
45 DREQi (at level sense)
47 48 TENDi ST *3 17
*4
18
Notes: 1. tDRQS and tDHQH are specified for the rising edge of clock followed by T3. 2. tDRQS and tDHQH are specified for the rising edge of clock. 3. DMA cycle starts. 4. CPU cycle starts.
Figure 19. DMA Control Signals
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Functional Description
Z80180 Microprocessor Unit
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DMA Contrl Signals E Clock Timing (Memory READ/WRITE Cycle, I/O READ/WRITE Cycle) T1 o T2 TW TW T3
~ ~
49
50
~ ~
E (Memory READ/WRITE) 49
50
~ ~
E (I/O READ) 49 50
~ ~
E (I/O WRITE)
15
16
~~ ~~
D0-D7
Figure 20. E Clock Timing (Memory R/W Cycle, I/O R/W Cycle)
E
PH1o E BUS RELEASE mode SLEEP mode SYSTEM STOP mode 49 50
Figure 21. E Clock Timing (Bus Release, Sleep, System Stop Modes
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Functional Description
Z80180 Microprocessor Unit
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E Clock Timing (Bus Release, Sleep, System Stop Modes) E Clock Timing (Minimum timing example of T2 TW T3 50 49 50 51 T1 T2 49 53
E Example I/O READ (R) Op Code Fetch
52
54
53
54
Figure 22. E Clock Timing (PWEL and PWEH Minimum Timing)
Timer Output Timing
Timer Data Reg.=0000h
A18/TOUT 55
Figure 23. Timer Output Timing
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Functional Description
Z80180 Microprocessor Unit
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Execution Cycle
SLEEP Instruction fetch T3 o T1 T2 TS TS
Next Op Code fetch T1 T2
~ ~
31 INTi
32
~ ~
NMI
~ ~
33
~~~ ~~~
A0-A18
MREQ, M1 RD HALT
43 44
Figure 24. SLEEP Execution Cycle
~ ~
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CSIO Receive/Transmit Timing
CSIO CLock
56
56
Transmit data (Internal Clock) 57 Transmit data (External Clock) 11tcyc 58 Receive data (Internal Clock) 11.5tcyc Receive data (External Clock) 16.5tcyc 11.5tcyc 16.5tcyc 59 11tcyc 58 59 57
60
61
60
61
Figure 25. CSIO Receive/Transmit Timing
Rise Time and Fall Times
65 EXTAL VIL1 VIH1 VIH1
66 VIL1
70
69
Input Rise Time
External
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Functional Description
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Figure 26. Rise Time and Fall Times
ASCI Register Description
ASCI Block Diagram
Internal Address/Data Bus Interrupt Request ASCI Transmit Data Register Ch 0: TDR0 TXA0 ASCI Transmit Shift Register* Ch 0: TSR0 ASCI Receive Data FIFO Ch 0: RDR0 RXA0 ASCI Receive Shift Register* Ch 0: RSR0 (8) ASCI Control Register A Ch 0: CNTLA0 (8) ASCI Control Register B Ch 0: CNTB0 (8) ASCI Status FIFO Ch 0 DCD0 ASCI Status Register Ch 0: STAT0 (8) ASCI Control ASCI Transmit Data Register Ch 1: TDR1 ASCI Transmit Shift Register* Ch 1: TSR1 ASCI Receive Data FIFO Ch 1: RDR1 ASCI Receive Shift Register* Ch 1: RSR1 (8) ASCI Control Register A Ch 1: CNTLA1 (8) ASCI Control Register B Ch 1: CNTB1 (8) ASCI Status FIFO Ch 1 ASCI Status Register Ch 1: STAT1 (8) CTS1 RXA1 TXA1
RTS0 CTS0
Note: *Not Program Accessible. CKA0 CKA1 Baud Rate Generator 0 Baud Rate Generator 1 f
Figure 27. ASCI Block Diagram
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ASCI Register Description
The following paragraphs explain the various functions of the ASCI registers. ASCI Transmit Shift Register 0 (TSR0, TSR1). When the ASCI Transmit Shift Register (TSR) receives data from the ASCI Transmit Data Register (TDR), the data is shifted out to the TxA pin. When transmission is completed, the next byte (if available) is automatically loaded from TDR into TSR and the next transmission starts. If no data is available for transmission, TSR IDLEs by outputting a continuous High level. This register is not program accessible ASCI Transmit Data Register 0,1 (TDR0, TDR1). I/O address = 06h, 07h. Data written to the ASCI Transmit Data Register is transferred to the TSR as soon as TSR is empty. Data can be written while TSR is shifting out the previous byte of data. The ASCI transmitter is double buffered. Data can be written into and read from the ASCI Transmit Data Register. If data is read from the ASCI Transmit Data Register, the ASCI data transmit operation is not affected by this READ operation.
ASCI Transmit Data Registers
Register addresses 06h and 07h hold the ASCI transmit data for channel 0 and channel 1, respectively.
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Functional Description
Z80180 Microprocessor Unit
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Channel 0
Mnemonics TDR0
Adess (06h)
7 ---
6 --
5 ---
4 --
3 --
2 --
1 --
ASCI Transmit Channel 0
Figure 28. ASCI Register
Channel 1
Mnemonics TDR1
Address (07h)
7 ---
6 --
5 ---
4 --
3 --
2 --
1 --
ASCI Transmit Channel 1
Figure 29. ASCI Register
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Z80180 Microprocessor Unit
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ASCI Receive Shift Register 0,1 (RSR0, RSR1) This register receives data shifted in on the RxA pin. When full, data is automati-
cally transferred to the ASCI Receive Data Register (RDR) if it is empty. If RSR is not empty when the next incoming data byte is shifted in, an overrun error occurs. This register is not program accessible.
ASCI Receive Data FIFO 0,1 (RDR0, RDR1) I/O Address = 08h, 09h). The ASCI Receive Data Register is a READ-ONLY register. When a complete incoming data byte is assembled in RSR, it is automati-
cally transferred to the 4 character Receive Data First-In First-Out (FIFO) memory. The oldest character in the FIFO (if any) can be read from the Receive Data Register (RDR). The next incoming data byte can be shifted into RSR while the FIFO is full. The ASCI receiver is well buffered.
ASCI Receive Register
Register addresses 08h and 09h hold the ASCI receive data for channel 0 and channel 1, respectively.
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Functional Description
Z80180 Microprocessor Unit
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Channel 0
Mnemonics TSR0
Address (08h) ASCI Receive Register Channel 0
7 --
6 --
5 --
4 --
3 --
2 --
1 --
ASCI Transmit Data
Figure 30. ASCI Receive Register Channel 0
Channel 1
Mnemonics TSR1
Address (09h) ASCI Receive Register Channel 1R
7 --
6 --
5 --
4 --
3 --
2 --
1 --
ASCI Transmit Data
Figure 31. ASCI Receive Register Channel 1R
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Functional Description
Z80180 Microprocessor Unit
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ASCI Channel Control Register A
ASCI Channel Control Register A
ASCI Control Register A 0 (CNTLA0: I/O Address = 00h) Bit 7 MPE R/W 6 RE R/W 5 TE R/W 4 RTS0 R/W 3 MPBR/ EFR R/W 2 MOD2 R/W 1 MOD1 R/W 0 MOD0 R/W
ASCI Control Register A 1 (CNTLA1: I/O Address = 01h) Bit 7 MPE R/W 6 RE R/W 5 TE R/W 4 __ R/W 3 MPBR/ EFR R/W 2 MOD2 R/W 1 MOD1 R/W 0 MOD0 R/W
Figure 32. ASCI Channel Control Register A MPE: Multi-Processor Mode Enable (bit 7). The ASCI features a
multiprocessor communication mode that utilizes an extra data bit for selective communication when a number of processors share a common serial bus. Multiprocessor data format is selected when the MP bit in CNTLB is set to 1. If multiprocessor mode is not selected (MP bit in CNTLB = 0), MPE exhibits no effect. If multiprocessor mode is selected, MPE enables or disables the wake-up feature as follows. If MBE is set to 1, only received bytes in which the MPB (multiprocessor bit) = 1 can affect the RDRF and error flags. Effectively, other bytes (with MPB = 0) are ignored by the ASCI. If MPE is reset to 0, all bytes, regardless of the state of the
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Functional Description
Z80180 Microprocessor Unit
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MPB data bit, affect the REDR and error flags. MPE is cleared to 0 during RESET. RE: Receiver Enable (bit 6). When RE is set to 1, the ASCI transmitter is enabled. When TE is reset to 0, the transmitter is disables and
any transmit operation in progress is interrupted. However, the TDRE flag is not reset and the previous contents of TDRE are held. TE is cleared to 0 in IOSTOP mode during RESET.
TE: Transmitter Enable (bit 5). When TE is set to 1, the ASCI receiver is enabled. When TE is reset to 0, the transmitter is dis-
abled and any transmit operation in progress is interrupted. However, the TDRE flag is not reset and the previous contents of TDRE are held. TE is cleared to 0 in IOSTOP mode during RESET.
RTS0: Request to Send Channel 0 (bit 4 in CNTLA0 only). If bit 4 of the System Configuration Register is 0, the RTS0/TxS pin features the RTS0 function. RTS0 allows the ASCI to control (START/STOP)
another communication devices transmission (for example, by connecting to that device's CTS input). RTS0 is essentially a 1 bit output port, having no side effects on other ASCI registers or flags. Bit 4 in CNTLA1 is not used.
MPBR/EFR: Multiprocessor Bit Receive/Error Flag Reset (bit 3). When multiprocessor mode is enabled (MP in CNTLB = 1), MPBR, when read, contains the value of the MPB bit for the most recent receive operation. When written to 0, the EFR function is selected to reset all error flags (OVRN, FE, PE and BRK in the ASEXT register) to 0. MPBR/EFR is undefined during RESET. MOD2, 1, 0: ASCI Data Format Mode 2, 1, 0 (bits 2-0). These bits
program the ASCI data format as shown in Table 8.
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Functional Description
Z80180 Microprocessor Unit
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Table 10. ASCI Data Formats Mode 2, 1, 0 Bit MOD2 = 0 MOD2 = 1 MOD1 = 0 MOD1 = 1 MOD0 = 0 MOD0 = 1 Description 0(R)7 bit data 1(R)8 bit data 0(R)No parity 1(R)Parity enabled 0(R)1 stop bit 1(R)2 stop bits
The data formats available based on all combinations of MOD2, MOD1, and MOD0 are indicated in Table 9, Data Formats.
Table 11. Data Formats MOD2 0 0 0 0 1 1 1 1 MOD1 0 0 1 1 0 0 1 1 MOD0 0 1 0 1 0 1 0 1 Data Format Start + 7 bit data + 1 stop Start + 7 bit data + 2 stop Start + 7 bit data + parity + 1 stop Start + 7 bit data + parity + 2 stop Start + 8 bit data + 1 stop Start + 8 bit data + 2 stop Start + 8 bit data + parity + 1 stop Start + 8 bit data + parity + 2 stop
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ASCI CHANNEL CONTROL REGISTER B
ASCI Channel Control Register B
ASCI Control Register B 0 (CNTLB0: I/O Address = 02h) ASCI Control Register B 1 (CNTLB1: I/O Address = 03h) Bit 7 MPBT R/W 6 MP R/W 5 CTS/ PS R/W 4 PEO R/W 3 DR R/W 2 SS2 R/W 1 SS1 R/W 0 SS0 R/W
Figure 33. ASCI Channel Control Register B MPBT: Multiprocessor Bit Transmit (bit 7). When multiprocessor communication format is selected (MP bit = 1), MPBT is used to specify the MPB data bit for transmission. If MPBT = 1, then MPB = 1 is transmitted. If MPBT = 0, then MPB = 0 is transmitted. MPBT state is undefined during and after RESET. MP: Multiprocessor Mode (bit 6). When MP is set to 1, the data format is configured for multiprocessor mode based on the MOD2 (number of data bits) and MOD0 (number of stop bits) bits in CNTLA. The format is as follows.
Start bit + 7 or 8 data bits + MPB bit + 1 or 2 stop bits Multiprocessor (MP=1) format does not feature any provision for parity. If MP = 0, the data format is based on MOD0, MOD1, MOD2, and may include parity. The MP bit is cleared to 0 during RESET.
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Functional Description
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CTS/PS: Clear to Send/Prescale (bit 5). f bit 5 of the System Configuration Register is 0, the CTS0/RxS pin features the CTS0 function, and the state of the pin can be read in bit 5 of CNTLB0 in a real-time, positive-logic fashion (HIGH = 1, LOW = 0). If bit 5 in the System Configuration Register is 0 to auto-enable CTS0, and the pin is negated (High), the TDRE bit is inhibited (forced to 0). Bit 5 of CNTLB1 reads back as 0. If the SS2-0 bits in this register are not 111, and the BRG mode bit in the ASEXT register is 0, then writing to this bit sets the prescale (PS) control. Under these circumstances, a 0 indicates a divide-by10 prescale function, while a 1 indicates divide-by-30. The bit resets to 0. PEO: Parity Even Odd (bit 4). PEO selects oven or odd parity. PEO does not affect the enabling/disabling of parity (MOD1 bit of CNTLA). If PEO is cleared to 0, even parity is selected. If PEO is set to 1, odd parity is selected. PEO is cleared to 0 during RESET. DR: Divide Ratio (bit 3). If the X1 bit in the ASEXT register is 0, this bit specifies the divider used to obtain baud rate from the data sampling clock. If DR is reset to 0, divide- by-16 is used, while if DR is set to 1, divide-by-64 is used. DR is cleared to 0 during RESET. SS2,1,0: Source/Speed Select 2,1,0 (bits 2-0). If these bits are 111, as they are after RESET, the CKA pin is used as a clock input, and is divided by 1, 16, or 64 depending on the DR bit and the X1 bit in the ASEXT register. If these bits are not 111 and the BRG mode bit is ASEXT is 0, these bits specify a power-of-two divider for the PHI clock as indicated in Divide Ratio. Setting or leaving these bits as 111 makes sense for a channel only when its CKA pin is selected for the CKA function. CKAO/CKS features the CKAO function when bit 4 of the System Configuration
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Functional Description
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Register is 0. DCD0/CKA1 features the CKA1 function when bit 0 of the Interrupt Edge register is 1.
Table 12. Divide Ratio SS2 0 0 0 0 1 1 1 1 SS1 0 0 1 1 0 0 1 1 SS0 0 1 0 1 0 1 0 1 Divide Ratio 1 2 4 8 16 32 64 External Clock
ASCI Status Register 0, 1 (STAT0, 1)
Each channel status register allows interrogation of ASCI communication, error and modem control signal status, and enabling or disabling of ASCI interrupts.
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ASCI Status Registers
ASCI Status Register 0 (STAT0: I/O Address = 04h) Bit 7 RDRF R 6 OVRN R 5 PE R 4 FE R 3 RE R/W 2 DCD0 R 1 TDRE R 0 TIE R/W
ASCI Status Register 1 (STAT1: I/O Address = 05h) Bit 7 RDRF R 6 OVRN R 5 PE R 4 FE R 3 RE R/W 2 __ 1 TDRE R 0 TIE R/W
Figure 34. ASCI Status Registers
RDRF: Receive Data Register Full (bit 7). RDRF is set to 1 when an incoming data byte is loaded into an empty RxFIFO. Note: If a framing or parity error occurs, RDRF is still set and the receive data (which generated the error) is still loaded into the FIFO.
RDRF is cleared to 0 by reading RDR and most recent character in the FIFO from IOSTOP mode, during RESET and for ASCI0 if the DCD0 input is auto-enabled and is negated (High).
OVRN: Overrun Error (bit 6). An overrun condition occurs when the receiver finishes assembling a character, but the RxFIFO is full so that there is no room for the character. However, this status bit is not set until the most recent character received before the overrun becomes the oldest byte in the FIFO. This bit is cleared when software writes a 1 to the EFR bit in the CNTLA register, and also by
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RESET, in IOSTOP mode, and for ASCI0 if the DCD0 pin is auto
enabled and is negated (High). When an overrun occurs, the receiver does not place the character in the shift register into the FIFO, nor any subsequent characters, until the last good character comes to the top of the FIFO so that OVRN is set, and software then writes a 1 to EFR to clear it. PE: Parity Error (bit 5). A parity error is detected when parity checking is enabled by the MOD1 bit in the CNT1LA register being 1, and a character is assembled in which the parity does not match the PEO bit in the CNTLB register. However, this status bit is not set until or unless the error character becomes the oldest one in the RxFIFO. PE is cleared when software writes a 1 to the EFR bit in the CNTRLA register, and also by RESET, in IOSTOP mode, and for ASCI0 if the DCD0 pin is auto-enabled and is negated (High). FE: Framing Error (bit 4). A framing error is detected when the stop bit of a character is sampled as 0/SPACE. However, this status bit is not set until or unless the error character becomes the oldest one in the RxFIFO. FE is cleared when software writes a 1 to the EFR bit in the CNTLA register, and also by RESET, in IOSTOP mode, and for ASCIO if the DCDO pin is auto-enabled and is negated (High). REI: Receive Interrupt Enable (bit 3). RIE should be set to 1 to enable ASCI receive interrupt requests. When RIE is 1, the receiver requests an interrupt when a character is received and RDRF is set, but only if neither DMA channel sets its request-routing field to receive data from this ASCI. That is, if SM1-0 are 11 and SAR17-16 are 10, or DIM1 is 1 and IAR17-16 are 10, then ASCI1 does not request an interrupt for RDRF. If RIE is 1, either ASCI requests an interrupt when OVRN, PE or FE is set, and ASCI0 requests an interrupt when DCD0 goes High. RIE is cleared to 0 by RESET.
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DCD0: Data Carrier Detect (bit 2 STAT0). If bit 0 of the Interrupt Edge Register (IER0) is 0, the DCD0/CKA1 pin features the DCD0 function, and this bit is set to 1 when the pin is High. It is cleared to 0 on the first READ of STAT0 following the pin's transition from High to Low and during RESET. When IER0 is 0, bit 6 of the ASEXT0 register is 0 to select auto-enabling, and the pin is negated (High), the bit 2 of STAT1 is not used. TDRE: Transmit Data Register Empty (bit 1). TDRE = 1 indicates that the TDR is empty and the next transmit data byte is written to TDR. After the byte is written to TDR, TDRE is cleared to 0 until the ASCI transfers the byte from TDR to the TSR and then TDRE is again set to 1. TDRE is set to 1 in IOSTOP mode and during RESET. On ASCIO, if the CTS0 pin is auto-enabled in the ASEXT0 registers and the pin is High, TDRE is reset to 0. TIE: Transmit Interrupt Enable (bit 0). TIE should be set to 1 to enable ASCI transmit interrupt requests. If TIE = 1, an interrupt is requested when TDRE = 1. TIE is cleared to 0 during RESET.
CSIO Control/Status Register
CNTR: I/O Address = 0Ah. CNTR is used to monitor CSIO status, enable and disable the CSIO, enable and disable interrupt generation, and select the data clock speed and source.
CSIO Control Register
Bit
7 EF R
6 EIE R/W
5 RE R/W
4 TE R/W
3 __
2 SS2 R/W
1 SS1 R/W
0 SS0 R/W
Figure 35. CSIO Control Register
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EF: End Flag (bit 7). EF is set to 1 by the CSIO to indicate completion of an 8-bit data transmit or receive operation. If the End Interrupt Enable (EIE) bit = 1 when EF is set to 1, a CPU interrupt request is generated. Program access of TRDR only occurs if EF = 1. The CSIO clears EF to 0 when TRDR is read or written. EF is cleared to 0 during RESET and IOSTOP mode. EIE: End Interrupt Enable (bit 6). EIE is set to 1 to generate a CPU interrupt request. The interrupt request is inhibited if EIE is reset to 0. EIE is cleared to 0 during RESET. RE: Receive Enable (bit 5). A CSIO receive operation is started by setting RE to 1. When RE is set to 1, the data clock is enabled. In internal clock mode, the data clock is output from the CKS pin. In external clock mode, the clock is input on the CKS pin. In either case, data is shifted in on the RXS pin in synchronization with the (internal or external) data clock. After receiving 8 bits of data, the CSIO automatically clears RE to 0, EF is set to 1, and an interrupt (if enabled by EIE = 1) is generated. RE and TE are never both set to 1 at the same time. RE is cleared to 0 during RESET and ISTOP mode. Transmit Enable (bit 4). A CSIO transmit operation is started by setting TE to 1. When TE is set to 1, the data clock is enabled. When in internal clock mode, the data clock is output from the CKS pin. In external clock mode, the clock is input on the CKS pin. In either case, data is shifted out on the TXS pin synchronous with the (internal or external) data clock. After transmitting 8 bits of data, the CSIO automatically clears TE to 0, EF is set to 1, and an interrupt (if enabled by EIE = 1) is generated. TE and RE are never both set to 1 at the same time. TE is cleared to 0 during RESET and IOSTOP mode. SS2, 1, 0: Speed Select 2, 1, 0 (bits 2-0). SS2, SS1 and SS0 select the CSIO transmit/receive clock source and speed. SS2, SS1 and
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SS0 are all set to 1 during RESET. Table 13 shows CSIO Baud Rate
Selection.
Table 13. CSIO Baud Rate Selection SS2 0 0 0 0 1 1 1 1 SS1 0 0 1 1 0 0 1 1 SS0 0 1 0 1 0 1 0 1 Divide Ratio 20 40 80 160 320 640 1280 External Clock Input(less than 20)
After RESET, the CKS pin is configured as an external clock input (SS2, SS1, SS0 = 1). Changing these values causes CKS to become an output pin and the selected clock is output when transmit or receive operations are enabled.
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Functional Description
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CSIO Transmit/Receive Data Register
(TRDR: I/O Address = 0Bh)
ASCI Receive Register Channel 1R
7 --
6 --
5 --
4 --
3 --
2 --
1 --
CSIO Transmit/Receive Data
Figure 36. ASCI Receive Register Channel 1R
Timer Data Register Channel 0L
TMDR0L: OCH
0Ch ASCI Receive Register Channel 1R
7 --
6 --
5 --
4 --
3 --
2 --
1 --
Timer Data
Figure 37. ASCI Receive Register Channel 1R
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Timer Data Register Channel 0H
TMDR0H: ODH
Timer Data Register Channel High
0Dh
7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 --
Timer Data
Figure 38. Timer Data Register Channel High
Timer Reload Register 0L
RLDR0L: 0EH
0Eh Timer Reload Register Low
7 --
6 --
5 --
4 --
3 --
2 --
1 --
Timer Reload Data
Figure 39. Timer Reload Register Low
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Timer Reload Register 0H
RLDR0H
0Fh Timer Reload Register
7 --
6 --
5 --
4 --
3 --
2 --
1 --
Timer Reload Data
Figure 40. Timer Reload Register
Timer Control Register (TCR)
TCR monitors both channels (PRT0, PRT1) TMDR status. It also
controls enabling and disabling of down counting and interrupts along with controlling output pin A18/TOUT for PRT1.
Timer Control Register (TCR: I/O Address = 10h)
Bit
7 TIF1 R
6 TIF0 R
5 TIE1 R/W
4 TIE0 R/W
3 TOC1 R/W
2 TOC0 R/W
1 TDE1 R/W
0 TDE0 R/W
Figure 41. Timer Control Register (TCR: I/O Address = 10h)
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TIF1: Timer Interrupt Flag 1 (bit 7). When TMDR1 decrements to 0, TIF1 is set to 1, and, when enabled by TIE1 = 1, an interrupt request is generated. TIF1 is reset to 0 when TCR is read and the higher or lower byte of TMDR1 is read. During RESET, TIF1 is cleared to 0. TIF0: Timer Interrupt Flag 0 (bit 6). When TMDR0 decrements to 0, TIF0 is set to 1, and, when enabled by TIE0 = 1, an interrupt request is generated TIF0 is reset to 0 when TCR is read and the higher or lower byte of TMDR0 is read. During RESET, TIF0 is cleared to 0. TIE1: Timer Interrupt Enable 1 (bit 5). When TIE0 is set to 1, TIF1 = 1 generates a CPU interrupt request. When TIE0 is reset to 0, the interrupt request is inhibited. During RESET, TIE0 is cleared to 0. TOC1, 0: Timer Output Control (bits 3, 2). TOC1 and TOC0 control the output of PRT1 using the multiplexed TOUT/DREQ pin as indicated in Timer Output Control. During RESET, TOC1 and TOC0 are cleared to 0. If bit 3 of the IAR1B register is 1, the TOUT function is selected. By programming TOC1 and TOC0, the TOUT/DREQ pin can be forced High, Low, or toggled when TMDR1 decrements to 0.
Table 14. Timer Output Control TOC1 0 0 1 1 TOC0 0 1 0 1 Output Inhibited Toggled 0 1 The TOUT/DREQ pin is not affected by the PRT. If bit 3 of IAR1B is 1, the TOUT/DREQ pin toggles or is set Low or High as indicated.
TDE1, 0: Timer Down Count Enable (bits 1, 0). TDE1 and TDE0 enable and disable down counting for TMDR1 and TMDR0, respectively. When TDEn (N = 0,1) is set to 1, down counting is stopped
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and TMDRn is freely read or written. TDE1 and TDE0 are cleared to 0 during RESET and TMDRn do not decrement until TDEn is set to 1.
ASCI Extension Control Register Channels 0 and 1
ASEXT0 and ASEXT1
The ASCI Extension Control Register controls functions newly added to the ASCIs in the Z80180 family. Note: All bits in this register reset to 0.
ASCI Extension Control Registers, Channel 0 and 1
ASCI Extension Control Register 0(ASEXT0 I/O Address = 12h) Bit 7 6 DCDO 5 CTSO 4 XI 3 BRGO Mode 2 Break Nab 1 Break 0 Send Break 0 Send Break
Reserved
Bit
7
ASCI Extension Control Register 1 (ASEXT1 I/O Address = 13h) 3 5 6 4 2 1 Reserved Reserved XI BRGI Mode Break Enab Break
Reserved
Figure 42. ASCI Extension Control Registers, Channel 0 and 1
DCD0 dis (bit 6, ASCI0 only). If bit 0 of the Interrupt Edge Register is 0 to select the DCD0 function for the DCD0/CKA1 pin, and this bit is 0, the DCD0 pin auto-enables the ASCI0 receiver. When the pin is negated/High, the Receiver is held in a RESET state. If bit 0 of
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Functional Description
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the IER is 0 and this bit is 1, the state of the DCD-pin has no effect on receiver operation. In either state of this bit, software can read the state of the DCD0 pin in the STAT0 register, and the receiver interrupts on a rising edge of DCD0. CTS0 dis (bit 5, ASCI0 only). If bit 5 of the System Configuration Register is 0 to select the CTS0 function of the CTS0/RXS pin, and this bit is 0, then the CTS0 pin auto-enables the ASCIO transmitter, in that when the pin is negated (High), the TDRE bit in the STAT0 register is forced to 0. If bit 5 of the System Configuration Register is 0 and this bit is 1, the state of the CTS0 pin exhibits no effect on the transmitter. Regardless of the state of this bit, software can read the state of the CTS0 pin the CNTLB0 register. X1 (bit 4). If this bit is 1, the clock from the Baud Rate Generator or CKA pin is received as a 1X bit clock (sometimes called isochronous mode). In this mode, receive data on the RXA pin must be synchronized to the clock on the CKA pin, regardless of whether CKA is an input or an output. If this bit is 0, the clock from the Baud Rate Generator or CKA pin is divided by 16 or 64 per the DR bit in CNTLB register, to obtain the actual bit rate. In this mode, receive data on the RXA pin is not required to be synchronized to a clock. BRG Mode (bit 3). If the SS2-0 bits in the CNTLB register are not 111, and this bit is 0, the ASCI Baud Rate Generator divides PHI by 10 or 30, depending on the DR bit in CNTLB, and then by a power of two selected by the SS2-0 bits, to obtain the clock that is presented to the transmitter and receiver and that can be output on the CKA pin. If SS2-0 are not 111, and this bit is 1, the Baud Rate Generator divides PHI by twice (the 16-bit value programmed into the Time Constant Registers, plus 2). This mode is identical to the operation of the baud rate generator in the ESCC. Break Enable (bit 2). If this bit is 1, the receiver detects break conditions and report them in bit 1, and the transmitter sends breaks under the control of bit 0.
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Functional Description
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Break Detect (bit 1). The receiver sets this READ-ONLY bit to 1 when an all-zero character with a Framing Error becomes the oldest character in the RxFIFO. The bit is cleared when software writes a 0 to the EFR bit in CNTLA register, also by RESET, by IOSTOP mode, and for ASCIO if the DCD0 pin is auto-enabled and is negated (High). Send Break (bit 0). If this bit and bit 2 are both 1, the transmitter holds the TXA pin Low to send a break condition. The duration of the break is under software control (one of the PRTs or CTCs can be used to time it). This bit resets to 0, in which state TXA carries the serial output of the transmitter.
Timer Data Register Channel 1L
Mnemonic TMDR1L:14H
Address 14 Timer Data Register
7
6
5
4
3
2
1
0
Timer Data
Figure 43. Timer Data Register
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Timer Data Register Channel 1H
Mnemonic TMDR1H: 15H
Address 15 Timer Data Register
7
6
5
4
3
2
1
0
Timer Data
Figure 44. Timer Data Register
Timer Reload Register Channel 1L
Mnemonic RLDR1L: 16H
Address 16 Timer Data Register
7
6
5
4
3
2
1
0
Reload Data
Figure 45. Timer Data Register
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Timer Reload Register Channel 1L
Mnemonic RLDR1L: 16H
Address 17 Timer Data Register
7
6
5
4
3
2
1
0
Reload Data
Figure 46. Timer Data Register
Free Running Counter I/O Address = 18H
Mnemonic FRC: 18H If data is written into the free running counter, the interval of DRAM refresh cycle and baud rates for the ASCI and CSI/O are not guar-
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anteed. In IOSTOP mode, the free running counter continues counting down. It is initialized to FFH,during RESET.
Timer Data Register
7
6
5
4
3
2
1
0
Counting Data
Figure 47. Timer Data Register
DMA Source Address Register Channel 0
(SAR0: I/O ADDRESS = 20h to 22h) specifies the physical source address for channel 0 transfers. The register contains 20 bits and can specify up to 1024-KB memory addresses or up to 64-KB I/O addresses. Channel 0 source can be memory, I/O, or memory mapped I/O. For I/O, the MS bits of this register identify the REQUEST HANDSHAKE signal.
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Functional Description
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DMA Source Address Register, Channel 0L
Mnemonic SAR0L
Address 20 Timer Data Register
7
6
5
4
3
2
1
0
--
--
--
--
--
--
--
--
DMA Channel 0 Address
Figure 48. DMA Channel 0L
DMA Source Address Register, Channel 0H
Mnemonic SAR0H
Address 21 Timer Data Register
7 --
6 --
5 --
4 --
3 --
2 --
1 --
0 --
DMA Channel 0 Address
Figure 49. DMA Channel 0H
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DMA Source Address Register Channel 0B
Mnemonics SAR0B
Address 22 Timer Data Register
7 --
6 --
5 --
4 --
3 --
2 --
1 --
0 --
DMA Channel B Address
Figure 50. DMA Channel 0B
DMA Destination Address Register Channel 0
(DAR0: I/O ADDRESS = 23h to 25h) specifies the physical destination address for channel 0 transfers. The register contains 20 bits and can specify up to 1024-KB memory addresses or up to 64-KB I/O addresses. Channel 0 destination can be memory, I/O, or memory mapped I/O. For I/O, the MS bits of this register identify the REQUEST HANDSHAKE signal for channel 0.
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Functional Description
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DMA Destination Address Register Channel 0L
Mnemonic DAR0L
Address 23 DMA Destination Address Register Channel 0L
Figure 51. DMA Destination Address Register Channel 0L
DMA Destination Address Register Channel 0H
Mnemonic DAR0H
Address 24 DMA Destination Address Register Channel 0H
Figure 52. DMA Destination Address Register Channel 0H
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DMA Destination Address Register Channel 0B
Mnemonic DAR0B
Address 25 DMA Destination Address Register Channel 0B
Figure 53. DMA Destination Address Register Channel 0B
Note: In the R1 and Z Mask, these DMA registers are expanded from 4 bits to 3 bits in the package version of CP-68.
Table 15. DMA Transfer Requests A19* X X X X A18 X X X X A17 0 0 1 1 A16 0 1 0 1 DMA Transfer Request DREQ0 TDR0 (ASCI0) TDR1 (ASCI1) Not Used
DMA Byte Count Register Channel 0
(BCRO: I/O ADDRESS = 26h to 27h) specifies the number of bytes to be transferred. This register contains 16 bits and may specify up to 64-KB transfers. When one byte is transferred, the register is decremented by 1. If n bytes should be transferred, n must be stored before the DMA operation.
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Note: All DMA Count Register channels are undefined during RESET.
DMA Byte Count Register Channel 0L
Mnemonic BCR0L
Address 26 DMA Byte Count Register 0L
Figure 54. DMA Byte Count Register 0L
DMA Byte Count Register Channel 0H
Mnemonic BCR0H
Address 27 DMA Byte Count Register 0H
Figure 55. DMA Byte Count Register 0H
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DMA Byte Count Register Channel 1L
Mnemonic BCR1L
Address 2E DMA Byte Count Register 1L
Figure 56. DMA Byte Count Register 1L
DMA Byte Count Register Channel 0H
Mnemonic BCR1H
Address 2F DMA Byte Count Register 0H
Figure 57. DMA Byte Count Register 0H
DMA Memory Address Register Channel 1
(MAR1: I/O ADDRESS = 28h to 2Ah) specifies the physical memory address for channel 1 transfers, which may also be a destination or
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Functional Description
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source memory address. The register contains 20 bits and may specify up to 1024-KB memory address.
DMA Memory Address Register, Channel 1L
Mnemonic MAR1L
Address 28 DMA Memory Address Register, Channel 1L
Figure 58. DMA Memory Address Register, Channel 1L
DMA Memory Address Register, Channel 1H
Mnemonic MAR1H
Address 29DMA Memory Address Register, Channel 1B DMA Memory Address Register, Channel 1H
Figure 59. DMA Memory Address Register, Channel 1H
Mnemonic MAR1B
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Address 2A ory Address Register, Channel 1B DMA Mem
Figure 60. DMA Memory Address Register, Channel 1B
DMA I/O Address Register Channel 1
(IAR1: I/O ADDRESS = 2Bh to 2Dh) specifies the I/O address for channel 1 transfers, which may also be a destination or source I/O address. The register contains 16 bits of I/O address; its most significant byte identifies the REQUEST HANDSHAKE signal and controls the Alternating Channel feature. All bits in IAR1B reset to 0.
IAR MS Byte Register (IARIB: I/O Address 2Dh)
Bit
7 A/T F
6 A/T C
5
4
3 TOUT DREQ
2
1 Req 1 Sel
0
Figure 61. IAR MS Byte Register (IARIB: I/O Address 2Dh
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DMA I/O Address Register Channel 1L
Mnemonic IAR1L
Address 2B DMA I/O Address Register Channel 1L
Figure 62. DMA I/O Address Register Channel 1L
DMA I/O Address Register Channel 1H
Mnemonic IAR1H
Address 2C DMA I/O Address Register Channel 1H
Figure 63. DMA I/O Address Register Channel 1H
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DMA I/O Address Register Channel 1B
Mnemonic IAR1B
Address 2D DMA I/O Address Register Channel 1B
Figure 64. DMA I/O Address Register Channel 1B
DMA Status Register (DSTAT)
DSTAT is used to enable and disable DMA transfer and DMA termination interrupts. DSTAT also indicates DMA transfer status, in
other words, completed or in progress.
Mnemonic DSTAT
Address 30
DMA Status Register (DSTAT: I/O Address = 30h)
Bit
7 DE1 R/W
6 DE0 R/W
5 DWE1 W
4 DWE0 W
3 DIE1 R/W
2 DIE0 R/W
1
0 DME R
Figure 65. DMA Status Register (DSTAT: I/O Address = 30h)
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Functional Description
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DE1: DMA Enable Channel 1 (bit 7). When DE1 = 1 and DME = 1, channel 1 DMA is enabled. When a DMA transfer terminates (BCR1 = 0), DE1 is reset to 0 by the DMAC. When DE1 = 0 and the DMA interrupt is enabled (DIE1 = 1), a DMA interrupt request is made to the CPU. To perform a software WRITE to DE1, DWE1 should be written with 0 during the same register WRITE access. Writing DE1 to 0 disables channel 1 DMA, but DMA is restartable. Writing DE1 to 1 enables channel 1 DMA and automatically sets DME (DMA Main Enable) to 1. DE1 is cleared to 0 during RESET. DE0: DMA Enable Channel 0 (bit 6). When DE0 = 1 and DME = 1, channel 0 DMA is enabled. When a DMA transfer terminates (BCR0 = 0), DE0 is reset to 0 by the DMAC. When DE0 = 0 and the DMA interrupt is enabled (DIE0 = 1), a DMA interrupt request is made to the CPU. To perform a software WRITE to DE0, DWE0 should be written with 0 during the same register WRITE access. Writing DE0 to 0 disables channel 0 DMA. Writing DE0 to 1 enables channel 0 DMA and automatically sets DME (DMA Main Enable) to 1. DE0 is cleared to 0 during RESET. DWE1: DE1 Bit WRITE Enable (bit 5). When performing any software WRITE to DE1, DWE1 should be written with 0 during the same access. DWE1 always reads as 1. DWE0: DE0 Bit WRITE Enable (bit 4). When performing any software WRITE to DE0, DWE0 should be written with 0 during the same access. DWE0 always reads as 1. DIE1: DMA Interrupt Enable Channel 1 (bit 3). When DIE0 is set to 1, the termination channel 1 DMA transfer (indicated when DE1 = 0) causes a CPU interrupt request to be generated. When DIE0 = 0, the channel 0 DMA termination interrupt is disabled. DIE0 is cleared to 0 during RESET.
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Functional Description
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DIE0: DMA Interrupt Enable Channel 0 (bit 2). When DIE0 is set to 1, the termination channel 0 of DMA transfer (indicated when DE0 = 0) causes a CPU interrupt request to be generated. When DIE0 = 0, the channel 0 DMA termination interrupt is disabled. DIE0 is cleared to 0 during RESET. DME: DMA Main Enable (bit 0). A DMA operation is only enabled when its DE bit (DE0 for channel 0, DE1 for channel 1) and the DME bit is set to 1. When NMI occurs, DME is reset to 0, disabling DMA activity during the NMI interrupt service routine. To restart DMA, DE- and/or DE1 should be written with a 1 (even if the contents are already 1). This WRITE automatically sets DME to 1, allowing DMA operations to continue. Note: DME cannot be directly written. It is cleared to 0 by NMI or indirectly set to 1 by setting DE0 and/or DE1 to 1. DME is cleared to 0 during RESET.
DMA Mode Register (DMODE)
DMODE is used to set the addressing and transfer mode for chan-
nel 0.
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Functional Description
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Mnemonic DMODE
Address 31h
DMA Mode Register (DMODE: I/O Address = 31h)
Bit
7
6
5 DM1 R/W
4 DM0 R/W
3 SM1 R/W
2 SM0 R/W
1 MMOD R/W
0
Figure 66. DMA Mode Register (DMODE: I/O Address = 31h)
DM1, DM0: Destination Mode Channel 0 (bits 5,4). Specifies whether the destination for channel 0 transfers is memory or I/O, and whether the address should be incremented or decremented for each byte transferred. DM1 and DM0 are cleared to 0 during RESET. See Table 16.
Table 16. Channel 0 Destination DM1 0 0 1 1 DM0 0 1 0 1 Memory I/O Memory Memory Memory I/O Memory Increment/Decrement +1 -1 fixed fixed
SM1, SM0: Source Mode Channel 0 (bits 3, 2). Specifies whether the source for channel 0 transfers is memory or I/O, and whether
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the address should be incremented or decremented for each byte transferred. See Table 17.
Table 17. Channel 0 Source SM1 0 0 1 1 SM0 0 1 0 1 Memory I/O Memory Memory Memory I/O Memory Increment/Decrement +1 -1 fixed fixed
Channel 1 Transfer Mode describes all DMA transfer mode combinations of DM0, DM1, SM0, and SM1. Because I/O to/from I/O transfers are not implemented, 12 combinations are available. MMOD: Memory Mode Channel 0 (bit 1). When channel 0 is configured for memory to/from memory transfers there is no REQUEST HANDSHAKE signal to control the transfer timing. Instead, two automatic transfer timing modes are selectable: burst (MMOD = 1) and cycle steal (MMOD = 0). For burst memory to/from memory transfers, the DMAC takes control of the bus continuously until the DMA transfer completes (the byte count register is 0). In CYCLE STEAL mode, the CPU is provided a cycle for each DMA byte transfer cycle until the transfer is completed. For channel 0 DMA with I/O source or destination, the selected
REQUEST HANDSHAKE signal times the transfer and MMOD is ignored. MMOD is cleared to 0 during RESET.
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DMA/WAIT Control Register (DCNTL)
DCNTL controls the insertion of wait states into DMAC (and CPU)
accesses of memory or I/O. DCNTL also defines the Request signal for each channel as level or edge sense. DCNTL also sets the DMA transfer mode for channel 1, which is limited to memory to/ from I/O transfers.
DMA/WAIT Control Register (DCNTL: I/O Address = 32h)
Bit
7 MWI1 R/W
6 MWI0 R/W
5 IWI1 R/W
4 IWI0 R/W
3
2
1 DIM1 R/W
0 DIM0 R/W
DMS1 DMS0 R/W R/W
Figure 67. DMA/WAIT Control Register (DCNTL: I/O Address = 32h
MWI1, MWI0: Memory Wait Insertion (bits 7-6). Specifies the number of wait states introduced into CPU or DMAC memory access cycles. MWI1 and MWI0 are set to 1 during RESET. (See Wait-State Generator for details.) IWI1, IWI0: I/O Wait Insertion (bits 5-4). Specifies the number of wait states introduced into CPU or DMAC I/O access cycles. IWI1 and IWI0 are set to 1 during RESET. See Wait-State Generator for details. DMS1, DMS0: DMA Request Sense (bits 3-2). DMS1 and DMS0 specify the DMA request sense for channel 0 and channel 1 respectively. When reset to 0, the input is level sense. When set to 1, the input is edge sense. DMS1 and DMS0 are cleared to 0 during
RESET.
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Typically, for an input/source device, the associated DMS bit should be programmed as 0 for level sense because the device undertakes a relatively long period to update its REQUEST signal after the DMA channel reads data from it in the first of the two machine cycles involved in transferring a byte. An output/destination device takes much less time to update its
REQUEST signal, after the DMA channel starts a WRITE operation
to it, as the second machine cycle of the two cycles involved in transferring a byte. With zero-wait state I/O cycles, which apply only to the ASCIs, it is impossible for a device to update its REQUEST signal in time, and edge sensing must be used. With one-wait-state I/O cycles (the fastest possible except for the ASCIs), it is unlikely that an output device is able to update its REQUEST in time, and edge sense is required for output to the ESCC and bidirectional Centronics controller, and is recommended for external output devices connected to TOUT/DREQ. With two or more wait states in I/O cycles, external output devices on TOUT/DREQ can use edge or level sense depending on their characteristics; edge sense is still recommended for output on the ESCC and bidirectional Centronics controller. DIM1, DIM0: DMA Channel 1 I/O and Memory Mode (bits 1-0). Specifies the source/destination and address modifier for channel 1 memory to/from I/O transfer modes. DIM1 and DIM0 are cleared to 0 during RESET.
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Interrupt Vector Low Register
Table 18. Channel 1 Transfer Mode DIM1 0 0 1 1 DMI0 0 1 0 1 Transfer Mode Memory(R)I/O Memory(R)I/O I/O(R)Memory I/O(R)Memory Address Increment/Decrement MAR1 +1, IAR1 fixed MAR1-1, IAR1 fixed IAR1 fixed, MAR1 + 1 IAR1 fixed, MAR1 -1
Mnemonic: IL
Address 33 Bits 7-5 of IL are used as bits 7-5 of the synthesized interrupt vector during interrupts for the INT1 and INT2 pins and for the DMAs, ASCIs, PRTs, and CSIO. These three bits are cleared to 0 during RESET (Figure ).
Interrupt Vector Low Register (IL: I/O Address = 33h)
Bit
7 IL 7 R/W
6 IL 6 R/W
5 IL 5 R/W
4 --
3 --
2 --
1 --
0 --
Programmable
Interrupt Source Dependent Code
Figure 68. Interrupt Vector Low Register (IL: I/O Address = 33h)
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Int/TRAP Control Register
Mnemonics ITC
Address 34 INT/TRAP Control Register (ITC, I/O Address 34h) This register is used in handling TRAP interrupts and to enable or disable Maskable Interrupt Level 0 and the INT1 and INT2 pins.
Bit 7 TRAP R/W 6 UFO R 5 -- 4 -- 3 -- 2 ITE2 R/W 1 ITE1 R/W 0 ITE0 R/W
Figure 69. Int/TRAP Control Register
TRAP (bit 7). This bit is set to 1 when an undefined op code is fetched. TRAP can be reset under program control by writing it with a 0, however, it cannot be written with 1 under program control. TRAP is reset to 0 during RESET. UFO: Undefined Fetch Object (bit 6). When a TRAP interrupt occurs, the contents of a UFO allow the starting address of the undefined instruction to be determined. However, the TRAP may occur on either the second or third byte of the op code. A UFO allows the stacked Program Counter (PC) value to be correctly adjusted. If UFO = 0, the first op code should be interpreted as the stacked PC-1. If UFO = 1, the first op code address is stacked PC-2. UFO is READ-ONLY.
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ITE2, 1, 0: Interrupt Enable 2, 1, 0 (bits 2-0). ITE2 and ITE1 enable and disable the external interrupt inputs INT2 and INT1, respectively. ITE0 enables and disables interrupts from the on-chip ESCC, CTCs and bidirectional Centronics controller as well as the external interrupt input INT0. A 1 in a bit enables the corresponding interrupt level while a 0 disables it. A RESET clears ITE0 to 1 and clears ITE1 and ITE2 to 0. TRAP Interrupt The Z80180 generates a nonmaskable (not affected by the state of IEF1) TRAP interrupt when an undefined op code fetch occurs. This feature can be used to increase software reliability, implement an extended instruction set, or both. TRAP may occur during op code fetch cycles and also if an undefined op code is fetched during the interrupt acknowledge cycle for INT0 when Mode 0 is used. When a TRAP interrupt occurs, the Z80180 operates as follows: 1. The TRAP bit in the Interrupt TRAP/Control (ITC) register is set to 1. 2. The current Program Counter (PC) value, reflecting the location of the undefined op code, is saved on the stack. 3. The Z80180 vectors to logical address 0. Note: If logical address 0000h is mapped to physical address 00000h, the vector is the same as for RESET. In this case, testing the TRAP bit in ITC reveals whether the restart at physical address 00000h was caused by RESET or TRAP. All TRAP interrupts occur after fetching an undefined second op code byte following one of the prefix op codes CBh, DDh, EDh, or FDh, or after fetching an undefined third op code byte following one of the double-prefix op codes DDCBh or FDCBh.
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The state of the Undefined Fetch Object (UFO) bit in ITC allows TRAP software to correctly adjust the stacked PC, depending on whether the second or third byte of the op code generated the TRAP. If UFO = 0, the starting address of the invalid instruction is equal to the stacked PC-1. If UFO = 1, the starting address of the invalid instruction is equal to the stacked PC-2.
Restart from 0000h 2nd Op Code Fetch Cycle PC Stacking TTP Ti Ti PC Ti Ti Ti T1 T2 T3 T1 T2 T3 T1 Op Code Fetch Cycle T2 T3
f
A0-A18 (A19) D0-D7
T1
T2
T3
SP-1 PCH
SP-2 PCL
0000h
Undefined Op Code M1 MREQ RD WR
Figure 70. TRAP Timing--2nd Op Code Undefined
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TRAP Timing--2nd Op Code Undefined
TRAP Timing--3rd Op Code Undefined
Restart from 0000h 3nd Op Code Fetch Cycle Memory READ Cycle TTP T3 Ti Ti Ti Ti PC Stacking T1 T2 T3 SP-1 PC-1H Undefined Op Code T1 T2 T3 SP-2 PC-1L Op Code Fetch Cycle T1 T2 T3
f
A0-A18 (A19) D0-D7 M1 MREQ RD WR
T1 T2 T3 T1 T2 PC
IX + d, IY + d
0000h
Figure 71. TRAP Timing--3rd Op Code Undefined
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Refresh Control Register
Mnemonic RCR
Address 36 Refresh Control Register (RCA: I/O Address = 36h)
7 -- REFE REFW
6 --
5 --
4 --
3 --
2 --
1 --
0 -- Cyc0 Cyc1
Reserved
Figure 72. Refresh Control Register (RCA: I/O Address = 36h)
The RCR specifies the interval and length of refresh cycles, while enabling or disabling the refresh function. REFE: Refresh Enable (bit 7). REFE = 0 disables the refresh controller, while REFE = 1 enables refresh cycle insertion. REFE is set to 1 during RESET. REFW: Refresh Wait (bit 6). REFW = 0 causes the refresh cycle to be two clocks in duration. REFW = 1 causes the refresh cycle to be three clocks in duration by adding a refresh wait cycle (TRW). REFW is set to 1 during RESET. CYC1, 0: Cycle Interval (bit 1,0). CYC1 and CYC0 specify the interval (in clock cycles) between refresh cycles. In the case of dynamic RAMs requiring 128 refresh cycles every 2 ms (or 256 cycles in every 4 ms), the required refresh interval is less than or
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equal to 15.625 s. The underlined values indicate the best refresh interval depending on CPU clock frequency. CYC0 and CYC1 are cleared to 0 during RESET (see DRAM Refresh Intervals).
Table 19. DRAM Refresh Intervals Time Interval CYC1 CYC0 Insertion Interval O: 10 MHz 0 0 1 1 0 1 0 1 10 states 20 states 40 states 80 states (1.0 s)* (2.0 s)* (4.0 s)* (8.0 s)* 8 MHz (2.5 s)* (5.0 s)* 6 MHz 3.3 s 6.6 s 4 MHz 5.0 s 2.5 MHz 4.0 s 8.0 s
(1.25 s)* 1.66 s 2.5 s
10.0 s 16.0 s
(10.0 s)* 13.3 s 20.0 s 32.0 s
NOTE: *Calculated interval.
Refresh Control and RESET After RESET, based on the initialized value of RCR, refresh cycles occur with an interval of 10 clock cycles and be 3 clock cycles in duration. Dynamic RAM Refresh Operation 1. REFRESH CYCLE insertion is stopped when the CPU is in the following states: a. During RESET b. When the bus is released in response to BUSREQ c. During SLEEP mode d. During WAIT states 2. Refresh cycles are suppressed when the bus is released in response to BUSREQ. However, the refresh timer continues to
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operate. The time at which the first refresh cycle occurs after the Z80180 reacquires the bus depends on the refresh timer, and possesses no timing relationship with the bus exchange. 3. Refresh cycles are suppressed during SLEEP mode. If a refresh cycle is requested during SLEEP mode, the refresh cycle request is internally latched (until replaced with the next refresh request). The latched refresh cycle is inserted at the end of the first machine cycle after SLEEP mode is exited. After this initial cycle, the time at which the next refresh cycle occurs depends on the refresh time and carries no relationship with the exit from SLEEP mode. 4. The refresh address is incremented by one for each successful refresh cycle, not for each refresh. Independent of the number of missed refresh requests, each refresh bus cycle uses a refresh address incremented by one from that of the previous refresh bus cycles.
MMU Common Base Register
Mnemonic CBR
Address 38
MMU Common Base Register (CBR). CBR specifies the base
address (on 4-KB boundaries) used to generate a 20-bit physical address for Common Area 1 accesses. All bits of CBR are reset to 0 during RESET.
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MMU Bank Base Register (BBR: I/O Address = 39h)
Bit
7 CB7 R/W
6 CB6 R/W
5 CB5 R/W
4 CB4 R/W
3 CB3 R/W
2 CB2 R/W
1 CB1 R/W
0 CB0 R/W
Figure 73. MMU Bank Base Register (BBR: I/O Address = 39h)
MMU Bank Base Register (BBR)
Mnemonic BBR
Address 39
BBR specifies the base address (on 4-KB boundaries) used to gen-
erate a 19-bit physical address for Bank Area accesses. All bits of
BBR are reset to 0 during RESET.
MMU Bank Base Register (BBR: I/O Address = 39h)
Bit
7 BB7 R/W
6 BB6 R/W
5 BB5 R/W
4 BB4 R/W
3 BB3 R/W
2 BB2 R/W
1 BB1 R/W
0 BB0 R/W
Figure 74. MMU Bank Base Register (BBR: I/O Address = 39h)
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MMU Common/Bank Area Register (CBAR)
Mnemonic CBAR
Address 3A
CBAR specifies boundaries within the Z80180 64-KB logical address space for up to three areas: Common Area, Bank Area and Common Area 1.
MMU Common/Bank Area Register (CBAR: I/O Address = 3 AH
Bit
7 CA3 R/W
6 CA2 R/W
5 CA1 R/W
4 CA0 R/W
3 BA3 R/W
2 BA2 R/W
1 BA1 R/W
0 BA0 R/W
Figure 75. MMU Common/Bank Area Register (CBAR: I/O Address = 3 AH
CA3-CA0:CA (bits 7-4). CA specifies the start (Low) address (on 4-KB boundaries) for the Common Area 1, and also determines the most recent address of the Bank Area. All bits of CA are set to 1 during RESET. BA-BA0 (bits 3-0). BA specifies the start (Low) address (on 4-KB boundaries) for the Bank Area, and also determines the most recent address of the Common Area 0. All bits of BA are set to 1 during RESET.
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Operation Mode Control Register
Mnemonic OMCR
Address 3E The Z80180 is descended from two different ancestor processors, ZiLOG's original Z80 and the Hitachi 64180. The Operating Mode Control Register (OMCR) can be programmed to select between certain differences between the Z80 and the 64180.
Operating Control Register(OMCR: I/O Address = 3Eh)
D7 D6 D5 -- -- -- -- -- Reserved IOC (R/W) M1TE (W) M1E (R/W)
Figure 76. Operating Control Register(OMCR: I/O Address = 3Eh
M1E (M1 Enable). This bit controls the M1 output and is set to a 1 during reset. When M1E = 1, the M1 output is asserted Low during the op code fetch cycle, the INT0 acknowledge cycle, and the first machine cycle of the NMI acknowledge. On the Z80180, this choice makes the processor fetch a RETI instruction one time only, and when fetching a RETI from zero-wait-
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state memory, uses three clock machine cycles which are not fully Z80-timing compatible, but are compatible with the on-chip CTCs. When MIE = 0, the processor does not drive M1 Low during instruction fetch cycles. After fetching a RETI instruction one time only with normal timing, the processor refetches the instruction using fully Z80-compatible cycles that include driving M1 Low. As a result, some external Z80 peripherals may require properly decoded RETI instruction.
I Instruction Sequence with MIE=0 RET
f
A0-A18 (A19) D0-D7 M1 MREQ RD ST
T1
T2
T3
T1
T2
T3
TI
TI
TI
T1
T2
T3
TI
T1
T2
T3
TI
PC EDh 4Dh
PC+1
PC EDh
PC+1 4Dh
Figure 77. RETI Instruction Sequence with MIE=0
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I/O Control Register (ICR)
ICR allows relocating of the internal I/O addresses. ICR also controls enabling/disabling of the IOSTOP mode (Figure ).
I/O Control Register (ICR: I/O Address = 3Fh)
Bit
7 IOA7 R/W
6 IOA6 R/W
5 IOSTP R/W
4 --
3 --
2 --
1 --
0 --
Figure 78. I/O Control Register (ICR: I/O Address = 3Fh)
IOA7, 6: I/O Address Relocation (bits 7,6)
IOA7 and IOA6 relocate internal I/O as illustrated in Figure 74.
Note: The high-order 8 bits of 16-bit internal I/O address are always 0. IOA7 and IOA6 are cleared to 0 during RESET.
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00FFh IOA7-IOA6 = 1 1 00COh 00BFh IOA7-IOA6 = 1 0 008Oh 007Oh IOA7- IOA6 = 0 1 004Oh 003Fh IOA7-IOA6 = 0 0 000Oh
Figure 79. I/O Address Relocation
IOSTP: IOSTOP Mode (bit 5) IOSTOP mode is enabled when IOSTP is set to 1. Normal I/O operation resumes when IOSTOP is reprogrammed or RESET to 0.
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Package Information
Figure 80. 80-Pin QFP Package Diagram
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Figure 81. 64-Pin DIP Package Diagram
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68-Pin PLCC Package Diagram
Figure 82. 68-Pin PLCC Package Diagram
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Ordering Information
Table 20. Ordering Information Z80180 6, 8, 10, 20, 33 MHz Z8018010FSC Z8018010PSC Z8018010VSC
For fast results, contact your local ZiLOG sales office for assistance in ordering the part required.
Codes
Package F = Plastic Quad Flatpack P = Plastic Dual In Line V = Plastic Leaded Chip Carrier S = 0C to +70C 6 = 6 MHz 8 = 8 MHz 10 = 10 MHz C = Plastic Standard
Temperature Speed
Environmental
Example: The Z80180 is a 10-MHz DIP, 0C to 70C, with Plastic Standard Flow.
Functional Description
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Z 80180 10 P S C
ZiLOG Prefix Product Number Speed Package Temperature Environmental Flow
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Functional Description

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