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M41T80
SERIAL ACCESS RTC WITH ALARMS
FEATURES SUMMARY s 2.0 TO 5.5V CLOCK OPERATING VOLTAGE
s
Figure 2. 8-pin SOIC Package
COUNTERS FOR TENTHS/HUNDREDTHS OF SECONDS, SECONDS, MINUTES, HOURS, DAY, DATE, MONTH, YEAR, and CENTURY SERIAL INTERFACE SUPPORTS I2C BUS (400KHz) PROGRAMMABLE ALARM and INTERRUPT FUNCTION LOW OPERATING CURRENT OF 200A OPERATING TEMPERATURE OF -40 TO 85C Table 1. Signal Names
XI XO IRQ/OUT/ SQW
IRQ/OUT/SQW M41T80 SCL SDA F32k
s
8 1
s
SO8 (M)
s s
Figure 1. Logic Diagram
VCC
Oscillator Input Oscillator Output Interrupt / Output Driver / Square Wave (Open Drain) Serial Data Input/Output Serial Clock Input 32kHz Square Wave Output (Open drain) Supply Voltage Ground
XI XO
SDA SCL F32k VCC
VSS
AI07005
VSS
October 2002
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M41T80
TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8-pin SOIC Connections (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Block Diagram (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Absolute Maximum Ratings (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operating and AC Measurement Conditions (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 AC Measurement I/O Waveform (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Capacitance (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DC Characteristics (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Crystal Electrical Characteristics (Table 6.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2-Wire Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Serial Bus Data Transfer Sequence (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Acknowledgement Sequence (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Bus Timing Requirements Sequence (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 AC Characteristics (Table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 READ Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Slave Address Location (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 READ Mode Sequence (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Alternative READ Mode Sequence (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 WRITE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 WRITE Mode Sequence (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 TIMEKEEPER(R) Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 TIMEKEEPER(R) Register Map (Table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Full-time 32kHz Square Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Century Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Alarm Interrupt Reset Waveform (Figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Alarm Repeat Modes (Table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Square Wave Output Frequency (Table 10.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Century Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Output Driver Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Preferred Power-on Default. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Preferred Power-on Default Values (Table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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M41T80
SUMMARY DESCRIPTION The M41T80 Serial Access TIMEKEEPER (R) SRAM is a low power Serial RTC with a built-in 32.768 KHz oscillator (external crystal controlled). Eight registers (see Table 8, page 13) are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. An additional 12 registers provide status/control of Alarm, 32kHz output, and Square Wave functions. Addresses and data are transferred serially via a two line, bidirectional I2C interface. The built-in address register is incremented automatically after each WRITE or READ data byte.
Functions available to the user include a time-ofday clock/calendar, Alarm interrupts, 32kHz output, and programmable Square Wave output. The eight clock address locations contain the century, year, month, date, day, hour, minute, second and tenths/hundredths of a second in 24 hour BCD format. Corrections for 28, 29 (leap year - valid until year 2100), 30 and 31 day months are made automatically. The M41T80 is supplied in an 8-pin SOIC.
Figure 3. 8-pin SOIC Connections
VCC IRQ/OUT/SQW(1) SCL SDA
AI07006
XI XO F32k(1) VSS
1 2 3 4
M41T80
8 7 6 5
Note: 1. Open drain output.
Figure 4. Block Diagram
REAL TIME CLOCK CALENDAR 32KHz OSCILLATOR
CRYSTAL
RTC W/ALARM
AF IRQ/OUT/SQW(1)
SDA
I2C INTERFACE
SQUARE WAVE
SCL
F32k(1)
AI07007
Note: 1. Open Drain output
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M41T80
MAXIMUM RATING Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 2. Absolute Maximum Ratings
Sym TSTG VCC TSLD(1) VIO IO PD Parameter Storage Temperature (VCC Off, Oscillator Off) Supply Voltage Lead Solder Temperature for 10 Seconds Input or Output Voltages Output Current Power Dissipation Value -55 to 125 -0.3 to 7 260 -0.3 to Vcc+0.3 20 1 Unit C V C V mA W
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. Reflow at peak temperature of 215C to 225C for < 60 seconds (total thermal budget not to exceed 180C for between 90 to 120 seconds).
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M41T80
DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Table 3. Operating and AC Measurement Conditions
Parameter Supply Voltage (VCC) Ambient Operating Temperature (TA) Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages
Note: Output Hi-Z is defined as the point where data is no longer driven.
M41T80 2.0 to 5.5V -40 to 85C 100pF 50ns 0.2VCC to 0.8 VCC 0.3VCC to 0.7 VCC
Figure 5. AC Measurement I/O Waveform
0.8VCC
0.7VCC 0.3VCC
AI02568
0.2VCC
Table 4. Capacitance
Symbol CIN COUT(3) tLP Input Capacitance Output Capacitance Low-pass filter input time constant (SDA and SCL) Parameter(1,2) Min Max 7 10 50 Unit pF pF ns
Note: 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested. 2. At 25C, f = 1MHz. 3. Outputs deselected.
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M41T80
Table 5. DC Characteristics
Symbol ILI ILO ICC1 Parameter Input Leakage Current Output Leakage Current Supply Current Test Condition(1) 0V VIN VCC 0V VOUT VCC 3.0V Switch Freq (SCL) = 400kHz 5.5V 32KE = 1 or SQWE = 1 3.0V 5.5V 1.5 1.8 200 3.0 35 2.4 31 -0.3 0.7VCC IOL = 3.0mA IOL = 10mA 0.3VCC VCC + 0.3 0.4 0.4 Min Typ Max 1 1 30 Unit A A A A A A A A V V V V
ICC2(2)
Supply Current (standby)
All Inputs = VCC - 0.2V Switch Freq (SCL) = 0Hz
3.0V 32KE = 0 and SQWE = 0 5.5V
VIL VIH
Input Low Voltage Input High Voltage Output Low Voltage
VOL
Output Low Voltage (Open Drain)(3)
Note: 1. Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 2.0 to 5.5V (except where noted). 2. At 25C. 3. For IRQ/FT/OUT, RST, and 32kHz pins (Open Drain)
Table 6. Crystal Electrical Characteristics
Sym fO RS CL Parameter(1,2) Resonant Frequency Series Resistance Load Capacitance 12.5 Min Typ 32.768 60 Max Units kHz k pF
Note: 1. Externally supplied if using the SO8 package. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork Type (thru-hole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. KDS can be contacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp for further information on this crystal type. 2. Load capacitors are integrated within the M41T80. Circuit board layout considerations for the 32.768 kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account.
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M41T80
OPERATION The M41T80 clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 20 bytes contained in the device can then be accessed sequentially in the following order: 1. Tenths/Hundredths of a Second Register 2. Seconds Register 3. Minutes Register 4. Century/Hours Register 5. Day Register 6. Date Register 7. Month Register 8. Year Register 9. Control Register 10. 32kE Bit 11 - 16. Alarm Registers 17 - 19. Reserved 20 - Square Wave Register 2-Wire Bus Characteristics The bus is intended for communication between different IC's. It consists of two lines: a bi-directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined: - Data transfer may be initiated only when the bus is not busy. - During data transfer, the data line must remain stable whenever the clock line is High. - Changes in the data line, while the clock line is High, will be interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy. Both data and clock lines remain High.
Start data transfer. A change in the state of the data line, from high to Low, while the clock is High, defines the START condition. Stop data transfer. A change in the state of the data line, from Low to High, while the clock is High, defines the STOP condition. Data Valid. The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit. By definition a device that gives out a message is called "transmitter," the receiving device that gets the message is called "receiver." The device that controls the message is called "master." The devices that are controlled by the master are called "slaves." Acknowledge. Each byte of eight bits is followed by one Acknowledge Bit. This Acknowledge Bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable Low during the High period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case the transmitter must leave the data line High to enable the master to generate the STOP condition.
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M41T80
Figure 6. Serial Bus Data Transfer Sequence
DATA LINE STABLE DATA VALID
CLOCK
DATA
START CONDITION
CHANGE OF DATA ALLOWED
STOP CONDITION
AI00587
Figure 7. Acknowledgement Sequence
START SCL FROM MASTER 1 2 8 CLOCK PULSE FOR ACKNOWLEDGEMENT 9
DATA OUTPUT BY TRANSMITTER
MSB
LSB
DATA OUTPUT BY RECEIVER
AI00601
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M41T80
Figure 8. Bus Timing Requirements Sequence
SDA tBUF tHD:STA tR SCL tHIGH P S tLOW tSU:DAT tHD:DAT tSU:STA SR P tSU:STO tF tHD:STA
AI00589
Table 7. AC Characteristics
Sym fSCL tLOW tHIGH tR tF tHD:STA tSU:STA tSU:DAT(2) tHD:DAT tSU:STO tBUF Parameter(1) SCL Clock Frequency Clock Low Period Clock High Period SDA and SCL Rise Time SDA and SCL Fall Time START Condition Hold Time (after this period the first clock pulse is generated) START Condition Setup Time (only relevant for a repeated start condition) Data Setup Time Data Hold Time STOP Condition Setup Time Time the bus must be free before a new transmission can start 600 600 100 0 600 1.3 Min 0 1.3 600 300 300 Typ Max 400 Units kHz s ns ns ns ns ns ns s ns s
Note: 1. Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 2.0 to 5.5V (except where noted). 2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.
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M41T80
READ Mode In this mode the master reads the M41T80 slave after setting the slave address (see Figure 10, page 10). Following the WRITE Mode Control Bit (R/W=0) and the Acknowledge Bit, the word address 'An' is written to the on-chip address pointer. Next the START condition and slave address are repeated followed by the READ Mode Control Bit (R/W=1). At this point the master transmitter becomes the master receiver. The data byte which was addressed will be transmitted and the master receiver will send an Acknowledge Bit to the slave transmitter. The address pointer is only incremented on reception of an Acknowledge Clock. The M41T80 slave transmitter will now place the data byte at address An+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to "An+2." Figure 9. Slave Address Location
R/W
This cycle of reading consecutive addresses will continue until the master receiver sends a STOP condition to the slave transmitter. The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume due to a Stop Condition or when the pointer increments to any non-clock address (08h-13h). Note: This is true both in READ Mode and WRITE Mode. An alternate READ Mode may also be implemented whereby the master reads the M41T80 slave without first writing to the (volatile) address pointer. The first address that is read is the last one stored in the pointer (see Figure 11, page 11).
START
SLAVE ADDRESS
A
MSB
1
1
0
1
0
0
LSB 0
AI00602
Figure 10. READ Mode Sequence
START START R/W BUS ACTIVITY: MASTER R/W
SDA LINE
S
WORD ADDRESS (An) ACK
S
DATA n
DATA n+1
ACK
ACK
ACK
BUS ACTIVITY: SLAVE ADDRESS
SLAVE ADDRESS STOP
DATA n+X
P
AI00899
10/20
NO ACK
ACK
M41T80
Figure 11. Alternative READ Mode Sequence
START STOP DATA n ACK ACK DATA n+1 ACK ACK DATA n+X P NO ACK
AI00895
BUS ACTIVITY: MASTER SDA LINE
S
BUS ACTIVITY: SLAVE ADDRESS
WRITE Mode In this mode the master transmitter transmits to the M41T80 slave receiver. Bus protocol is shown in Figure 12, page 11. Following the START condition and slave address, a logic '0' (R/W=0) is placed on the bus and indicates to the addressed device that word address "An" will follow and is to be written to the on-chip address pointer. The data word to be written to the memory is strobed in next Figure 12. WRITE Mode Sequence
START BUS ACTIVITY: MASTER R/W
R/W
and the internal address pointer is incremented to the next address location on the reception of an acknowledge clock. The M41T80 slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address see Figure 9, page 10 and again after it has received the word address and each data byte.
SDA LINE
S
WORD ADDRESS (An) ACK ACK
DATA n
DATA n+1
DATA n+X
P
ACK
ACK
BUS ACTIVITY: SLAVE ADDRESS
AI00591
ACK
STOP
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M41T80
CLOCK OPERATION The M41T80 is driven by a quartz-controlled oscillator with a nominal frequency of 32,768Hz. The accuracy of the Real Time Clock depends on the frequency of the quartz crystal that is used as the time-base for the RTC. The 20-byte Register Map (see Table 8, page 13) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. Tenths/Hundredths of Seconds, Seconds, Minutes, and Hours are contained within the first four registers. Note: A WRITE to any clock register will result in the Tenths/Hundredths of Seconds being reset to "00," and Tenths/Hundredths of Seconds cannot be written to any value other than "00." Bits D6 and D7 of Clock Register 03h (Century/ Hours Register) contain the CENTURY ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle. Bits D0 through D2 of Register 04h contain the Day (day of week). Registers 05h, 06h, and 07h contain the Date (day of month), Month and Years. The ninth clock register is the Control Register. Bit D7 of Register 01h contains the STOP Bit (ST). Setting this bit to a '1' will cause the oscillator to stop. If the device is expected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain.
When reset to a '0' the oscillator restarts within four seconds (typically one second). The eight Clock Registers may be read one byte at a time, or in a sequential block. Provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read. If a clock address is being read, an update of the clock registers will be halted. This will prevent a transition of data during the READ. TIMEKEEPER (R) Registers The M41T80 offers 20 internal registers which contain Clock, Alarm, 32kHz, Flag, Square Wave, and Control data. These registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as BiPORTTM TIMEKEEPER cells). The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. The internal divider (or clock) chain will be reset upon the completion of a WRITE to any clock address. The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume either due to a Stop Condition or when the pointer increments to any non-clock address (08h-13h). TIMEKEEPER and Alarm Registers store data in BCD. Control, 32kHz, and Square Wave Registers store data in Binary Format.
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M41T80
Table 8. TIMEKEEPER(R) Register Map
Addr D7 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h OUT 32kE AFE RPT4 RPT3 RPT2 RPT1 0 0 0 0 RS3 AF 0 0 0 RS2 0 0 SQWE RPT5 0 ST 0 CEB 0 0 0 CB 0 0 0 10 Years 0 0 0 0 0 Al 10M 0 0 10 Date 10M D6 D5 D4 D3 D2 D1 D0 Function/Range BCD Format 10s/100s of Seconds Seconds Minutes Century/ Hours Day Date Month Year 00-99 00-59 00-59 0-1/00-23 01-7 01-31 01-12 00-99
0.1 Seconds 10 Seconds 10 Minutes 10 Hours 0 0
0.01 Seconds Seconds Minutes Hours (24 Hour Format) Day of Week Date: Day of Month Month Year
0
0
0
0
0
0
0
0
Control 32kHz Al Month Al Date Al Hour Al Min Al Sec 01-12 01-31 00-23 00-59 00-59
Alarm Month Alarm Date Alarm Hour Alarm Minutes Alarm Seconds
AI 10 Date AI 10 Hour
Alarm 10 Minutes Alarm 10 Seconds 0 0 0 0 RS1 0 0 0 0 RS0 0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
Flags Reserved Reserved Reserved SQW
Keys: ST = Stop Bit 0 = Must be set to '0' 32kE = 32kHz Enable Bit CEB = Century Enable Bit CB = Century Bit OUT = Output level
AFE = Alarm Flag Enable Flag RPT1-RPT5 = Alarm Repeat Mode Bits AF = Alarm Flag (Read only) SQWE = Square Wave Enable RS0-RS3 = SQW Frequency
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M41T80
Setting Alarm Clock Registers Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second or repeat every year, month, day, hour, minute, or second. Bits RPT5-RPT1 put the alarm in the repeat mode of operation. Table 9, page 14 shows the possible configurations. Codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. When the clock information matches the alarm clock settings based on the match criteria defined by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE (Alarm Flag Enable) is also set (and SQWE is '0.'),
the alarm condition activates the IRQ/OUT/SQW pin. Note: If the address pointer is allowed to increment to the Flag Register address, an alarm condition will not cause the Interrupt/Flag to occur until the address pointer is moved to a different address. It should also be noted that if the last address written is the "Alarm Seconds," the address pointer will increment to the Flag address, causing this situation to occur. The IRQ/OUT/SQW output is cleared by a READ to the Flags Register as shown in Figure 13. A subsequent READ of the Flags Register is necessary to see that the value of the Alarm Flag has been reset to '0.'
Figure 13. Alarm Interrupt Reset Waveform
0Eh 0Fh 10h
ACTIVE FLAG
IRQ/OUT/SQW
HIGH-Z
AI07021
Table 9. Alarm Repeat Modes
RPT5 1 1 1 1 1 0 RPT4 1 1 1 1 0 0 RPT3 1 1 1 0 0 0 RPT2 1 1 0 0 0 0 RPT1 1 0 0 0 0 0 Alarm Setting Once per Second Once per Minute Once per Hour Once per Day Once per Month Once per Year
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M41T80
Table 10. Square Wave Output Frequency
Square Wave Bits RS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Square Wave Frequency None 32.768 8.192 4.096 2.048 1.024 512 256 128 64 32 16 8 4 2 1 Units kHz kHz kHz kHz kHz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz
Full-time 32kHz Square Wave Output The M41T80 offers the user a special 32kHz square wave function which defaults to output on the F32k pin (Pin 3) as long as VCC is valid, and the oscillator is running (ST Bit = '0'). This function is available within four seconds of initial power-up and can only be disabled by setting the 32kE Bit to
'0' or the ST Bit to '1.' If not used, the F32k pin should be disconnected and allowed to float. Note: The F32k pin is an open drain which requires an external pull-up resistor.
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M41T80
Century Bit Bits D7 and D6 of Clock Register 03h contain the CENTURY ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle. Output Driver Pin When the AFE Bit and SQWE Bit are not set, the IRQ/OUT/SQW pin becomes an output driver that reflects the contents of D7 of the Control Register. In other words, when D7 (OUT Bit) of address loTable 11. Preferred Power-on Default Values
Condition Power-up(1) ST 0 Out 1 AFE 0 SQWE 0 32kE 1
cation 08h is a '0,' then the IRQ/OUT/SQW pin will be driven low. Note: The IRQ/OUT/SQW pin is an open drain which requires an external pull-up resistor. Preferred Power-on Default When powering the device up from ground (0V), the following register bits are set to a '0' state: ST; AFE; and SQWE. The following bits are set to a '1' state: OUT and 32kE (see Table 11, page 16).
Note: 1. If VCC falls to a voltage, 0V < VCC < 2.0V, these bits should be rewritten by the user.
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M41T80
PART NUMBERING Table 12. Ordering Information Scheme
Example: M41T 80 M 6 TR
Device Type M41T
Supply Voltage and Write Protect Voltage 80 = VCC = 2.0 to 5.5V
Package M = SO8
Temperature Range 6 = -40C to 85C
Shipping Method for SOIC blank = Tubes TR = Tape & Reel
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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M41T80
PACKAGE MECHANICAL INFORMATION Figure 14. SO8 - 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Drawing
h x 45 A2 B e D A C ddd
8
E
1
H A1 L
SO-A
Note: Drawing is not to scale.
Table 13. SO8 - 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
mm Symb Typ A A1 B C D ddd E e H h L N - - - - - - - 1.27 - - - - Min 1.35 0.10 0.33 0.19 4.80 - 3.80 - 5.80 0.25 0.40 0 8 Max 1.75 0.25 0.51 0.25 5.00 0.10 4.00 - 6.20 0.50 0.90 8 Typ - - - - - - - 0.050 - - - - Min 0.053 0.004 0.013 0.007 0.189 - 0.150 - 0.228 0.010 0.016 0 8 Max 0.069 0.010 0.020 0.010 0.197 0.004 0.157 - 0.244 0.020 0.035 8 inches
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M41T80
REVISION HISTORY Table 14. Document Revision History
Date October 2002 Rev. # 1.0 First Issue Revision Details
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M41T80
M41T80, 41T80, T80, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, vIndustrial, Industrial, Industrial, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. (c) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. www.st.com
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