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| CPAD-WALTZ(S5L840F) Internet Audio Decoder for Flash Memory Media Data Sheet INTRODUCTION S5L840F is a single chip digital audio player IC supporting various compressed audio format on Flash Memory Media. S5L840F provides 2Mbits of embedded NOR flash memory and 76Kbytes of SRAM requiring no external memory. A 16bit RISC processor (CALMRISC16TM) and 24bit MAC(MAC2424 TM) are provided as a CPU and DSP function. FEATURES * Supply voltage range: * * Supply Voltage (Core) : 1.8V Supply Voltage (IO) : 3.0V * * * * * * * * * IO DMA Supports SMC/MMC/SD/Memory Stic LCD Controller Interface 2 Channels of IIS IIC / SPDIF Output / UART / SPI USB1.1 5 channel 10bit ADC RTC GPIO X-tal Oscillator: 32.768 KHz 16bit RISC(CalmRISC16) & 24bit MAC with 4KB of Instruction Cache 6KB of X Cache 6KB of Y Cache * 2Mbit NOR Flash & 76KB SRAM TYPICAL APPLICATION * MP3/WMA/etc Player ORDERING INFORMATION Device S5L840F Package 128-TQFP-1414 Operating Temperature -40 C - +85 C 1 BLOCK DIAGRAM 76KB SRAM 2Mbit NOR-Flash Timer RTC 10bit ADC GPIO LCD IF Memory Controller CalmADM3 WDT 4KB ROM Interrupt Controller 3 2 b i t A H B P L U S IO DMA Clock Gen UART AHB to APB Bridge 3 2 b i t A P B Memory stick I/F SD/MMC I/F SMC I/F IIC(M/S) SPI IIS In IIS Out USB1.1 SPDIF Out CPAD-WALTZ S5L840F PIN CONFIGURATION TEST2/ DEBUG TEST1 TEST_CLK TCK TMS TDI TDO EXHV VCC3F nERR/SDAT/ EINT4 / P1.6 SCLK/ EINT5 / P1.7 VDDF VSSF Xout Xin TEST0/TOOL EXHVEN LD0/P8.0 NRST_ADM PADVSS1 PADVDD1 INTVSS1 INTVDD1 LD1 / P8.1 LD2 / P8.2 LD3 / P8.3 LD4 / P8.4 LD5 / P8.5 LD6 / P8.6 LD7 / P8.7 Rx/P0.4 Tx/P0.5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 LD_RE/P9.0 LD_WE/P9.1 LD_CS/P9.2 LD_REG/P9.3 LD_RST/P9.4 TACK/TACAP/P0.0 TAOUT/P0.1 TCCK/P0.2 SPDIF/P0.3 EINT6/P0.6/SDWP EINT7/P0.7/RBN PADVDD2 PADVSS2 INTVSS2 INTVDD2 EINT0/P2.0 EINT1/P2.1 EINT2/P2.2 EINT3/P2.3 DM DP VDDUSB VSSUSB IO0/P4.0 D1(SDC)/IO8/P5.0 IO1/P4.1 D0(SDC)/IO9/P5.1 IO2/P4.2 CLK_MMC_SDC/P3.0 CMD(SDC)/IO10/P5.2 IO3/P4.3 D3(SDC)/IO11/P5.3 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 AVREF AVSS ADC0 ADC1 ADC2 ADC3 ADC4 P10.4 P10.5 P10.6 P10.7 MOSI/P1.0 MISO/P1.1 SPISCK/P1.2 RUNST nRESET INTVSS5 INTVDD5 SCL/P1.3 SDA/P1.4 nSSI/P1.5 PADVDD4 PADVSS4 CLKSEL INTVSS6 INTVDD6 VDDPLL0 VSSPLL0 CP0 VDDPLL1 VSSPLL1 CP1 S5L840F (Ver 35) 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 P10.3 P10.2 P10.1 P10.0 MCLK/P7.4 BCLK/P7.3 SD0/P7.2 INTVDD4 INTVSS4 LRCLK/P7.1 SD1/P7.0 nWP/P6.7 nWE/P6.6 ALE/P6.5 CLE/P6.4 nCE2/P6.3 nCE1/P6.2 nCE0/P6.1 nRE/P6.0 BS(MS)/IO15/P5.7 IO7/P4.7 D0(MS)/IO14/P5.6 IO6/P4.6 P3.1/CLK_MS IO13/P5.5 IO5/P4.5 D2(SDC)/IO12/P5.4 IO4/P4.4 INTVDD3 INTVSS3 PADVSS3 PADVDD3 3 PIN DESCRIPTION Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 I/O I I I I I I O B P B B P P O I I I B I P P P P B Pin Description DEBUG(internal F/F value dump) control Test mode Test clock JTAG clock. Pull-Up. JTAG mode selection. Pull-Up. JTAG input JTAG output Flash high voltage test Flash memory internal 3.3V Power. UART, GPIO UART, GPIO Flash memory internal 1.8V Power. GND for flash core Crystal oscillator signal (~100KHz) Crystal oscillator signal (~100KHz) BUS/Serial Controller Selection. Pull-Down Flash high volatge test enable. Pull-Down LCD I/F Adm reset. Pull-Up. Pad power GND Pad power VDD 3.3V Internal logic GND Internal logic Power VDD 1.8V LCD I/F Pin Assignment TEST2/DEBUG TEST1 TEST_CLK(for debug) TCK TMS TDI TD0 EXHV VCC3F nERR/EINT4/P1.6 EINT5/P1.7 VDDF VSSF Xout Xin TEST0/TOOL_MODE EXHVEN LD0/P8.0 NTRST_ADM PADVSS1 PADVDD1 INTVSS1 INTVDD1 LD1/P8.1 CPAD-WALTZ S5L840F 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 LD2/P8.2 LD3/P8.3 LD4/P8.4 LD5/P8.5 LD6/P8.6 LD7/P8.7 Rx/P0.4 Tx/P0.5 LD_RE/P9.0 LD_WE/P9.1 LD_CS/P9.2 LD_REG/P9.3 LD_RST/P9.4 TACK/TACAP/P0.0 TAOUT/P0.1 TCCK/P0.2 SPDIF/P0.3 EINT6/P0.6/SDWP EINT7/P0.7/RBN PADVDD2 PADVSS2 INTVSS2 INTVDD2 EINT0/P2.0 EINT1/P2.1 EINT2/P2.2 B B B B B B B B B B B B B B B B B B B P P P P B B B LCD I/F LCD I/F LCD I/F LCD I/F LCD I/F LCD I/F INT, GPIO INT, GPIO LCD I/F LCD I/F LCD I/F LCD I/F LCD I/F Timer A, GPIO Timer A, GPIO Timer C, GPIO SPDIF, GPIO INT, GPIO, SDC_WP INT, GPIO, RBN(SMC) Pad power VDD 3.3V Pad power GND Internal logic GND Internal logic Power VDD 1.8V INT, GPIO INT, GPIO INT, GPIO 5 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 EINT3/P2.3 DM DP VDDUSB VSSUSB IO0/P4.0 D1(SDC)/IO8/P5.0 IO1/P4.1 D0(SDC)/IO9/P5.1 IO2/P4.2 CLK_MMC_SDC/P3.0 CMD(SDC)/IO10/P5.2 IO3/P4.3 D3(SDC)/IO11/P5.3 PADVDD3 PADVSS3 INTVSS3 INTVDD3 IO4/P4.4 D2(SDC)/IO12/P5.4 IO5/P4.5 IO13/P5.5 P3.1/CLK_MS IO6/P4.6 D0(MS)/IO14/P5.6 IO7/P4.7 B B B P P B B B B B B B B B P P P P B B B B B B B B INT, GPIO USB transceive/receive port USB transceive/receive port USB Power 3.3V USB Ground IO0 for SMC /Debug scan in IO8 for SMC, D0 for SDC IO1 for SMC IO9 for SMC, D1 for SDC IO2 for SMC CLK for MMC/SDC IO10 for SMC, CMD/RESP for SDC IO3 for SMC IO11 for SMC, D3 for SDC Pad power VDD 3.3V Pad power GND Internal logic GND Internal logic Power VDD 1.8V IO4 for SMC IO12 for SMC, D2 for SDC IO5 for SMC IO13 for SMC GPIO, CLK for MS IO6 for SMC IO14 for SMC, D0 for MS IO7 for SMC CPAD-WALTZ S5L840F 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 BS(MS)/IO15/P5.7 nRE/P6.0 nCE0/P6.1 nCE1/P6.2 nCE2/P6.3 CLE/P6.4 ALE/P6.5 nWE/P6.6 nWP/P6.7 SD1/P7.0 LRCLK/P7.1 INTVSS4 INTVDD4 SD0/P7.2 BCLK/P7.3 MCLK/P7.4 P10.0 P10.1 P10.2 P10.3 AVREF AVSS ADC0 ADC1 ADC2 ADC3 B B B B B B B B B B B P P B B B B B B B P P I I I I IO15 for SMC, BS for MS SMC control SMC control SMC control SMC control SMC control SMC control SMC control /Debug scan out SMC control Serial Data In for IIS Left-Right Clock for IIS Internal logic GND Internal logic Power VDD 1.8V Serial Data Out for IIS Bit Clock for IIS Over-sampling Clock for IIS GPIO GPIO GPIO GPIO ADC VREF,AVDD33A1,AVDD33A2 . 3.3V Power ADC analog GND. avss33a1,avbb33a1,avss33a2 ADC ADC ADC ADC 7 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 ADC4 P10.4 P10.5 P10.6 P10.7 MOSI/P1.0/tclk0 MISO/P1.1/tclk1 SPISCK/P1.2 RUNST nRESET INTVSS5 INTVDD5 SCL/P1.3 SDA/P1.4 nSSI/P1.5 PADVDD4 PADVSS4 CLKSEL INTVSS6 INTVDD6 VDDPLL0 VSSPLL0 CP0 VDDPLL1 VSSPLL1 CP1 I B B B B B B B B I P P B B B P P I P P P P O P P O ADC GPIO GPIO GPIO GPIO SPI, GPIO, TCLK0(not open) SPI, GPIO, TCLK1(not open) SPI, GPIO JTAG RUNID / TEST mode select System RESET. Pull-Up. Internal logic GND Internal logic Power VDD 1.8V IIC, GPIO IIC, GPIO SPI, IIC, UART Pad power VDD 3.3V Pad power GND Clock selection signal. Pull-Up. Internal logic GND Internal logic Power VDD 1.8V PLL Power supply VDD 1.8V PLL GND Low pass filter circuit for pll0 PLL Power supply VDD 1.8V PLL GND Low pass filter circuit for pll1 CPAD-WALTZ S5L840F ABSOLUTE MAXIMUM RATINGS Characteristic Supply Voltage Input Voltage Storage Temperature Range Symbol VDD VIN Tstg Value 3.8 6.5 -65-150 Unit V V C ELECTRICAL CHARACTERISTICS Recommended Operating Conditions Characteristic Supply Voltage Operating Temperature Range Symbol VDD Topr Value 1.65~1.95(Core), 2.7~3.3(IO) -40-85 Unit V C DC Characteristics (Ta = 25C, VDD(IO) = 3.3V, Unless otherwise specified) Symbol VIH VIL VT VT+ VTVOH VOL IOZ Characteristic High level input voltage Low level input voltage Switching threshold Schmitt trigger, positive -going threshold Schmitt trigger, negative-going threshold High level output voltage Low level output voltage Tri-state output leakage current Test Conditions - - CMOS CMOS IOH = -2mA IOL = 2mA Vout = Vss or GND 0.8 2.4 - -10 - - - - 0.4 10 Min 2.0 - Typ - - 1.4 2.0 Max - 0.8 Unit V V V V V V V A NOTES: 9 PACKAGE DIMENSIONS Low-Power & High-Performance RISC Core CalmRISC16 Technical Reference Manual MCU Team LSI Division System LSI Business Samsung Electronics Co. Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual 1. Introduction 1.1 Feature The main features of CalmRISC16, a 16-bit embedded RISC MCU core, are high performance, low power consumption, and efficient coprocessor interface. It can operate up to 100MHz, and consumes 100A/MHz @3.3V. When operating with MAC2424, a 24-bit fixed point DSP coprocessor, CalmRISC16 can operate up to 80MHz. Through efficient coprocessor interface, CalmRISC16 provides a powerful and flexible MCU+DSP solution. The following gives brief summary of main features of CalmRISC16. H/W Feature Power consumption : 100A per MHz @3.3V, 0.35 process Maximum frequency : 100MHz @3.3V 0.78 mm2 die size Architecture Harvard RISC architecture 5-Stage pipeline Registers Sixteen 16-bit general registers Eight 6-bit extension registers 22-bit Program Counter (PC) 16-bit Status Register (SR) Seven saved registers for interrupts. Instruction Set 16-bit instruction width for 1-word instructions 32-bit instruction width for 2-word instructions Load/Store instruction architecture Delayed branch support C-language/OS support Bit operation for I/O process Instruction Execution Time One instruction/cycle for basic instructions Address Space 4M byte for Program Memory 4M byte for Data Memory MCU Team LSI Division System LSI Business -2- April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual 1.2. Registers In CalmRISC16 there are sixteen 16-bit general registers, eight 6-bit extension registers, a 16-bit Status Register(SR), a program counter (PC), and seven saved registers. General Registers & Extension Registers The following figure shows the structure of the general registers and the extension registers. R0 R1 Registers for Byte PC SPC_FIQ SPC_IRQ SR SSR_FIQ SSR_IRQ SSR_SWI R7 E8 E9 R8 R9 Address Registers E14 E15 R14 R15 Link Register Stack Pointer Register Structure in CalmRISC16 The general registers (from R0 to R15) can be either a source register or a destination register for almost all ALU operations, and can be used as an index register for memory load/store instructions (e.g., LDW R3, @[A8+R2]). The 6-bit extension registers (from E8 to E15) are used to form a 22-bit address register (from A8 to A15) by concatenating with a general register (from R8 to R15). The address registers are used to generate 22-bit program and data addresses. Special Registers The special registers consist of 16-bit SR (Status Register), 22-bit PC (Program Counter), and saved registers for IRQ(interrupt), FIQ(fast interrupt), and SWI(software interrupt). When IRQ interrupt occurs, the most significant 6 bits of the return address are saved in SPCH_IRQ, the least significant 16 bits of MCU Team LSI Division System LSI Business -3April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual the return address are saved in SPCL_IRQ, and the status register is saved in SSR_IRQ. When FIQ interrupt occurs, the most significant 6 bits of the return address are saved in SPCH_FIQ, the least significant 16 bits of the return address are saved in SPCL_FIQ, and the status register is saved in SSR_FIQ. When a SWI instruction is executed, the return address is saved in A14 register (E14 concatenated with R14), and the status register is saved in SSR_SWI. The least significant bit of PC, SPCL_IRQ and SPCL_FIQ is read only and its value is always 0. The 16-bit register SR has the following format. 15 T 8 7 PM Z1 Z0 V TE IE 0 FE FE : FIQ enable bit, FIQ is enabled when FE is set. IE : IRQ enable bit, IRQ is enabled when IE is set. TE : TRQ enable bit, Trace is enabled when TE is set. V : overflow flag, set/clear accordingly when arithmetic instructions are executed. Z0 : zero flag of R6, set when R6 equals zero and used as the branch condition when BNZD instruction with R6 is executed. Z1 : zero flag of R7, set when R7 equals zero and used as the branch condition when BNZD instruction with R7 is executed. PM : privilege mode bit. PM = 1 for privilege mode and PM = 0 for user mode T : true flag, set/clear as a result of an ALU operation. FE, IE, TE, and PM bits can be modified only when PM = 1 (privilege mode). The only way to change from user mode to privilege mode is via interrupts including SWI instructions. The reserved bit of SR (from bit 7 to bit 14) can be used for other purposes without any notice. Hence programmers should not depend on the value of the reserved bits in their programming. The reserved bits are read as 0 value. 1.3. Pipeline Structure CalmRISC16 has a 5-stage pipeline architecture. It takes 5 cycles for an instruction to do its operation. In a pipeline architecture, instructions are executed overlapped, hence the throughput is one instruction per cycle. Due to data dependency, control dependency, and 2 word instructions, the throughput is about 1.2 on the average. The following diagram depicts the 5-stage pipeline structure. IF ID EX MEM WB In the first stage, which is called IF (Instruction Fetch) stage, an instruction is fetched from program MCU Team LSI Division System LSI Business -4April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual memory. In the second stage, which is called ID (Instruction Decoding) stage, the fetched instruction is decoded, and the appropriate operands, if any, for ALU operation are prepared. In the case of branch or jump instructions, the target address is calculated in ID stage. In the third stage, which is called EX (Execution) stage, ALU operation and data address calculation are executed. In the fourth stage, which is called MEM (Memory) stage, data transfer from/to data memory or program memory is executed. In the fifth stage, which is called WB (Write Back) stage, a write-back to register file can be executed. The following figure shows an example of pipeline progress when 3 consecutive instructions are executed. I1 : ADD R0, 3 I2 : ADD R1, R0 I3 : LD R2, R0 IF ID IF EX ID IF MEM EX ID WB MEM EX WB MEM WB In the above example, the instruction I2 needs the result of the instruction I1 before I1 completes. To resolve this problem, the EX stage result of I1 is forwarded to ID stage of I2. Similar forwarding mechanism occurs from MEM stage of I1 to ID stage of I3. The pipeline cannot progress (called a pipeline stall) due to a data dependency, a control dependency, or a resource conflict. When a source operand of an ALU instruction is from a register, which is loaded from memory in the previous instruction, 1 cycle of pipeline stall occurs (called load stall). Such load stalls can be avoided by smart reordering of the instruction sequences. CalmRISC16 has 2 classes of branch instructions, those with a delay slot and without a delay slot. Non-delay slot branch instructions incurs a 1 cycle pipeline stall if the branch is taken, due to a control dependency. For branch instructions with a delay slot, no cycle waste is incurred if the delay slot is filled with a useful instruction (or non NOP instruction). Pipeline stalls due to resource conflicts occurs when two different instructions access at the same cycle the same resource such as the data memory and the program memory. LDC (data load from program memory) instruction causes a resource conflict on the program memory. Bit operations such as BITR and BITS (read-modify-write instructions) cause a resource conflict on the data memory. 1.4 Interrupts In CalmRISC16, there are five interrupts: RESET, FIQ, IRQ, TRQ, SWI. The RESET, FIQ, and IRQ interrupts correspond to external requests. TRQ and SWI interrupts are initiated by an instruction (therefore, in a deterministic way). The following table shows a summary of interrupts. Name RESET FIQ Priority 1 3 Address 000000h 000002h MCU Team LSI Division System LSI Business Description Hardware Reset Fast Interrupt Request -5April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual 000004h 000006h 000008h ~ 0000feh Interrupt Request Trace Request Software Interrupt IRQ TRQ SWI 5 2 4 When nRES (an input pin CalmRISC16 core) signal is released (transition from 0 to 1), "JMP addr:22" is automatically executed by CalmRISC16. Among the 22-bit address addr:22, the most significant 6 bits are forced to 0, and the least significant 16 bits are the contents of 000000h (i.e., reset vector address) of the program memory. In other words, "JMP {6'h001, PM[000000h]}" instruction is forced to the pipeline. The initial value of PM bit is 1 (that is, in privilege mode) and the initial values of other bits in SR register are 0. All other registers are not initialized (i.e., unknown). When nFIQ (an input pin CalmRISC16 core) signal is active (transition from 1 to 0), "JMP addr:22" instruction is automatically executed by CalmRISC16. The address of FIQ interrupt service routine is in 000002h (i.e., FIQ vector address) of the program memory (i.e., "JMP {6'h00, PM[000002h]}"). The return address is saved in {SPCH_FIQ, SPCL_FIQ} register pair, and the SR value is saved in SSR_FIQ register. PM bit is set. FE, IE, and TE bits are cleared. When RET_FIQ instruction is executed, SR value is restored from SSR_FIQ, and the return address is restored into PC from {SPCH_FIQ, SPCL_FIQ}. When nIRQ signal (an input pin CalmRISC16 core) is active (transition from 1 to 0), "JMP {6'h00, PM[000004h]}" instruction is forced to the instruction pipeline. The return address is saved in {SPCH_IRQ, SPCL_IRQ} register pair, and the SR value is saved in SSR_IRQ register. PM bit is set. IE and TE bits are cleared. When RET_IRQ instruction is executed, SR value is restored from SSR_IRQ, and return address is restored to PC from {SPCH_IRQ, SPCL_IRQ}. When TE bit is set, TRQ interrupt happens and "JMP {6'h00, PM[000006h]}" instruction is executed right after each instruction is executed. TRQ interrupt uses the saved registers of IRQ(that is, {SPCH_IRQ, SPCL_IRQ} register pair and SSR_IRQ) to save the return address and SR, respectively. PM bit is set. IE, TE bits are cleared. When "SWI imm:62" instruction is executed, the return address is saved in the register A14, and the value of SR is saved in SSR_SWI. Then the program sequence jumps to the address (imm:6 * 4). PM bit is set. IE and TE bits are cleared. "SWI 0" and "SWI 1" are prohibited because the addresses are reserved for other interrupts. When RET_SWI instruction is executed, SR is restored from SSR_SWI, and the return address is restored to PC from A14. 1.5 Memory Formats 1 2 6'h00 is defined as 00 (or zero) in 6 bits imm:6 is defined as 6-bit immediate number MCU Team LSI Division System LSI Business -6April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual CalmRISC16 adopts a big endian memory format. In a big endian memory format, the most significant byte of word data is stored at an even address, and the least significant byte is stored at an odd address. For example let us assume that the word data "1234h" is stored at the address 100h. Then the higher byte "12h" is stored at the address 100h, and the lower byte "34h" is stored at the address 101h. When the 22-bit data "123456h" is stored at the address 100h by "LDW @An, Ai" instruction, "00h" is at the address 100h, "12h" is at the address 101h, "34h" is at the address 102h, and "56h" is at the address 103h. 1.6 Signal Description Name PA[20:0] PD[15:0] nPMCS nLDC DA[21:0] DI[15:0] DO[15:0] nDMCSH nDMCSL DMWR nDME nRES nFIQ nIRQ nEXPACK nWAIT nSYSID MCLK ECLK ICLK nCOPID nCLDID CLDWR Direction O I O O O I O O O O O I I I O I O I O O O O O Description Program Memory Address, equivalent to PC[21:1] Program Data Program Memory Chip Selection Data load from program memory indicator Data Memory Address DA[4:0] is shared with SYS and CLD instructions Input from Data Memory, Input from coprocessor for CLD instruction. Output to Data Memory, Output to coprocessor for CLD instruction. Chip Selection for Higher Byte Data Memory Chip Selection for Lower Byte Data Memory Data Memory Write, 1 means transfer from Core to Memory Data Bus Enable Signal. Hardware Reset Fast Interrupt Request Interrupt Request Exception Acknowledge Wait signal, core is stopped when active. SYS instruction indicator Main Clock Input Early Clock Output Clock Output Coprocessor instruction indicator Coprocessor Load instruction indicator Write to Coprocessor indicator MCU Team LSI Division System LSI Business -7April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual Instruction to coprocessor, 13-bit immediate field in COP instruction. External Conditions from coprocessor or peripherals. Software break indicator Break Acknowledge Break Mode, indicates core state when core breaks. Break Request Global interrupt disable, when active, all interrupt is disabled. Indicates program memory access is permitted. Indicates current program memory access is not complete. Indicates data memory access is permitted. Indicates current data memory access is not complete. Signal asking for data bus permission. Privilege Mode Indicator Indicates that coprocessor may use data bus. Coprocessor indicates that coprocessor pipeline stall occurs. Coprocessor indicates that coprocessor instruction is multiple word. Indicates that the next program address is sequential. If it is 1, PC value is not incremented when sequential execution. Clock output to coprocessor COPIR[12:0] EC[3:0] nBRK nBKACK BKMODE[2:0] BKREQ nGIDIS PDGRANT PDWAIT DBGRANT DBWAIT DBREQ PMODE CGRANT CSTALL CMW nSEQ nINCPC CCLK O I O O O I I I I I I O O O I I O I O 2. Instructions 2.1. ALU instructions In operations between a 16-bit general register and an immediate value, the immediate value is zeroextended to 16-bit. The following figure shows an example of 7-bit immediate numbers. 6 imm:7 15 '0' 7 0 7-bits immediate 7-bits immediate In operations between a 22-bit register and an immediate value, the immediate value is zero-extended to MCU Team LSI Division System LSI Business -8April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual 22-bit. In operations between a 22-bit register and a 16-bit register, the 16-bit register is zero-extended to 22-bit. The overflow flag in a 16-bit arithmetic operation is saved to V flag in SR register. ALU instructions are classified into 3 classes as follows. ALUop Register, Immediate ALUop Register, Register ALUop Register ALUop Register, Immediate ADD/ADC/SUB/SBC/AND/OR/XOR/TST/CMP/CMPU Rn, #imm:16 The instructions perform an ALU operation of which source operands are a 16-bit general register Rn and a 16-bit immediate value. In the instructions TST/CMP/CMPU, only T flag is updated accordingly as the result. In the instructions ADD/ADC/SUB/SBC, the value of T flag is the carry flag of the operations, and the value of V flag indicates whether overflow or underflow occurs. In the instructions AND/OR/XOR/TST, the value of T flag indicates whether the result is zero (T=1). "CMP {GT|GE|EQ}, Rn, #imm:163" instructions are for signed comparison operations (GT for greater than, GE for greater than or equal to and EQ for equal to), and "CMPU {GT|GE}, Rn, #imm:16" instructions are for unsigned comparison operations. ADD/SUB An, #imm:16 The immediate value is zero-extended to 22-bit value. No flag update occurs. ADD/SUB Rn, #imm:7 The immediate value is zero-extended to 16-bit value. T flag is updated to the carry of the operation. V flag is updated. AND/OR/XOR/TST R0, #imm:8 The immediate value is zero-extended to 16-bit value. T flag indicates whether the lower 8-bit of the logical operation result is zero. CMP EQ, Rn, #imm:8 The immediate value is zero-extended to 16-bit value. Rn is restricted to R0 to R7. T flag is updated as the result of the instruction. 3 imm:16 is defined as a 16-bit immediate number MCU Team LSI Division System LSI Business -9April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual CMP GE, Rn, #imm:6 The immediate value is zero-extended to 16-bit value. The instruction is for signed compare. T flag is updated as the result of the instruction. ADD/SUB An, #imm:5 The immediate value is zero-extended to 22-bit value. No flag is updated. ALUop Register, Register ADD/SUB/ADC/SBC/AND/OR/XOR/TST/CMP/CMPU Rn, Ri The instructions perform an ALU operation of which source operands are a pair of 16-bit general registers. In the instructions TST/CMP/CMPU, only T flag is updated as the result. In the instructions ADD/ADC/SUB/SBC, the value of T flag is the carry of the operations, and the value of V flag indicates whether overflow or underflow occurs. In the instructions AND/OR/XOR/TST, the value of T flag indicates whether the result is zero. "CMP {GT|GE|EQ}, Rn, Ri" instructions are for signed comparison, and "CMPU {GT|GE}, Rn, Ri" instructions are for unsigned comparison. ADD/SUB An, Ri 16-bit general register Ri is zero-extended to 22-bit value. The result is saved in the 22-bit register An. No flag update occurs. CMP EQ, An, Ai The instruction compares two 22-bit registers. MUL {SS|SU|US|UU}, Rn, Ri The general registers Rn and Ri can be one of R0 to R7. The instruction multiplies the lower byte of Rn and the lower byte of Ri, and the 16-bit result is saved in Rn. The optional field, SS, SU, US, and UU, indicates whether the source operands are signed value or unsigned value. The first letter of the two letter qualifiers corresponds to Rn, and the second corresponds to Ri. For example, in the instruction "MUL SU, R0, R1", the 8-bit signed value in the lower byte of R0 and the 8-bit unsigned value in the lower byte of R1 are multiplied, and the 16-bit result is saved in R0. RR/RL/RRC/SR/SRA/SLB/SRB/DT/INCC/DECC/COM/COM2/COMC/EXT Rn For "DT Rn"(Decrement and Test) and "COM Rn"(Complement) instructions, T flag indicates whether the result is zero. In the instruction of "EXT Rn"(Sign Extend), no flag update occurs. In all other instructions, carry-out of the operation is transferred to T flag. In the instruction of DT, INCC, and DECC, MCU Team LSI Division System LSI Business - 10 April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual V flag indicates whether overflow or underflow occurs. 2.2. Load instructions "Load instructions" move data from register/memory/immediate to register/memory. When the destination is a memory location, only general registers and extension registers can be the source. We can classify "Load instructions" into the following 4 classes. LD Register, Register LD Register, Immediate LD Data Memory, Register / LD Register, Data Memory LD Register, Program Memory LD Register, Register LD Rn, Ri / LD An, Ai The instructions move 16-bit or 22-bit data from the source register to the destination register. When the destination register is R6/R7, the zero flag Z0/Z1 is updated. In all other cases, no flag update occurs. LD Rn, Ei / LD En, Ri In the instruction "LD Rn, Ei", the 6-bit data in Ei is zero-extended to 16-bit data, and then transferred to Rn. When the destination register is R6/R7, the zero flag Z0/Z1 is updated. In the instruction "LD En, Ri", least significant 6 bits of Ri are transferred to En. Rn/Ri is one of the registers from R0 to R7. LD R0, SPR / LD SPR, R0 SPR : SR, SPCL_FIQ, SPCH_FIQ, SSR_FIQ, SPCL_IRQ, SPCH_IRQ, SSR_IRQ, SSR_SWI The instructions transfer data between SPR (Special Purpose Registers) and R0. No flag update occurs except the case that the destination register is SR. LD An, PC The instruction moves the value of (PC+4) to An. LD Register, Data Memory / LD Data Memory, Register LDW Rn, @[SP+edisp:9] / LDW @[SP+edisp:9], Rn The instructions transfer 16-bit data between a general register Rn and the memory location at the address of (SP+edisp:9). Note SP is another name of A15. edisp:9 is an even positive displacement from 0 to 510. MCU Team LSI Division System LSI Business - 11 April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual edisp:9 is encoded into an 8-bit displacement value in the instruction map because the LSB is always 0. When the address is calculated, the 8-bit displacement field is shifted to the left by one bit, and then the result is added to the value of SP. Even if the address might be specified as odd in assembly mnemonic, the LSB of the address should be truncated to zero for word alignment. LDW Rn, @[Ai+edisp:5] / LDW @[Ai+edisp:5], Rn The instructions transfer 16-bit data between a general register Rn and the memory location at the address of (Ai+edisp:5). edisp:5 is an even positive displacement from 0 to 30. edisp:5 is encoded into an 4-bit displacement value in the instruction map because the LSB is always 0. When the address is calculated, the 4-bit displacement field is shifted to the left by one bit, and then the result is added to the value of Ai. Even if the address might be specified as odd in assembly mnemonic, the LSB of the address should be truncated to zero for word alignment. LDW Rn, @[Ai+disp:16] / LDW @[Ai+disp:16], Rn The instructions transfer 16-bit data between a general register Rn and the memory location at the address of (Ai+disp:16). disp:16 is an positive displacement from 0 to FFFFh. If the address is odd, the LSB of the address is set to zero for word alignment. LDW Rn, @[Ai+Rj] / LDW @[Ai+Rj], Rn The instructions transfer 16-bit data between a general register Rn and the memory location at the address of (Ai+Rj). The value of Rj is zero-extended to 22-bit value. If the address is odd, the LSB of the address is set to zero for word alignment. LDW An, @[Ai+edisp:5] / LDW @[Ai+edisp:5], An The instructions transfer 22-bit data between an address register An and the memory location at the address of (Ai+edisp:5). edisp:5 is an even positive displacement from 0 to 30. edisp:5 is encoded into an 4-bit displacement value in the instruction map because the LSB is always 0. When the address is calculated, the 4-bit displacement field is shifted to the left by one bit, and then the result is added to the value of Ai. Even if the address might be specified as odd in assembly mnemonic, the LSB of the address should be truncated to zero for word alignment. LDW An, @[Ai+disp:16] / LDW @[Ai+disp:16], An The instructions transfer 22-bit data between an address register An and the memory location at the address of (Ai+disp:16). disp:16 is an positive displacement from 0 to FFFFh. If the address is odd, the LSB of the address is set to zero for word alignment. LDW An, @[Ai+Rj] / LDW @[Ai+Rj], An MCU Team LSI Division System LSI Business - 12 April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual The instructions transfer 22-bit data between an address register An and the memory location at the address of (Ai+Rj). The value of Rj is zero-extended to 22-bit value. If the address is odd, the LSB of the address is set to zero for word alignment. PUSH Rn/PUSH Rn, Rm/PUSH An/ PUSH An, Am The instruction "PUSH Rn" transfers 16-bit data from the register Rn to the memory location at the address of SP, and then increments the value of SP by 2. The register Rn should not be R15. The operation of "PUSH R15" is undefined. The instruction "PUSH Rn, Rm" pushes Rn and then Rm. The registers Rn and Rm should not be the same. The registers Rn and Rm should not be R15. The instruction "PUSH An" pushes Rn and then En. When the extension register En is pushed, the value of En is zeroextended to 16-bit data. The register An should not be A15. The instruction "PUSH An, Am" pushes An and then Am. The registers An and Am should not be the same POP Rn/POP Rn, Rm/POP An/ POP An, Am The instruction "POP Rn" decrements the value of SP by 2, and then transfers 16-bit data to the register Rn from the memory location at the address of SP. The register Rn should not be R15. The operation of "POP R15" is undefined. The instruction "POP Rn, Rm" pops Rn and then Rm. The registers Rn and Rm should not be the same. The registers Rn and Rm should not be R15. The instruction "POP An" pops En and then Rn. When the extension register En is popped, the least significant 6 bits are transferred to En. The register An should not be A15. The instruction "POP An, Am" pops An and then Am. The registers An and Am should not be the same LDB Rn, @[Ai+disp:4] / LDB @[Ai+disp:4], Rn The instructions transfer 8-bit data between the general register Rn and the memory location at the address of (Ai+disp:4). disp:4 is a positive displacement from 0 to 15. The general register Rn is one R0 to R7. In the instruction "LDB Rn, @[Ai+disp:4]", the 8-bit data is zero-extended to 16-bit data, and then written into Rn. In the instruction "LDB @[Ai+disp:8], Rn", the least significant byte of Rn is transferred to the memory. LDB Rn, @[Ai+disp:16] / LDB @[Ai+disp:16], Rn The instructions transfer 8-bit data between the general register Rn and the memory location at the address of (Ai+disp:16). disp:16 is a positive displacement from 0 to FFFFh. The general register Rn is one of R0 to R7. In the instruction "LDB Rn, @[Ai+disp:16]", the 8-bit data is zero-extended to 16bit data, and then written into Rn. In the instruction "LDB @[Ai+disp:16], Rn", the least significant byte of Rn is transferred to the memory. LDB R0, @[A8+disp:8] / LDB @[A8+disp:8], Rn MCU Team LSI Division System LSI Business - 13 April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual The instructions transfer 8-bit data between the general register R0 and the memory location at the address of (A8+disp:8). disp:8 is a positive displacement from 0 to 255. In the instruction "LDB R0, @[A8+disp:8]", the 8-bit data is zero-extended to 16-bit data, and then written into R0. In the instruction "LDB @[A8+disp:8], R0", the least significant byte of R0 is transferred to the memory. LDB Rn, @[Ai+Rj] / LDB @[Ai+Rj], Rn The instructions transfer 8-bit data between the general register Rn and the memory location at the address of (Ai+Rj). The value of Rj is zero-extended to 22-bit value. The general register Rn is one of the 8 registers from R0 to R7. In the instruction "LDB Rn, @[Ai+Rj]", the 8-bit data is zero-extended to 16bit data, and then written into R0. In the instruction "LDB @[Ai+Rj], Rn", the least significant byte of Rn is transferred to the memory. LD Register, Program Memory LDC Rn, @Ai The instruction transfers 16-bit data to Rn from program memory at the address of Ai. LD Register, # immediate LD Rn, #imm:8 / LD Rn, #imm:16 / LD An, #imm:22 The instructions move an immediate data to a register. In the instruction "LD Rn, #imm:8", the immediate value is zero-extended to 16-bit value. 2.3. Branch instructions CalmRISC16 has 2 classes of branch instructions: with a delay slot and without a delay slot. If a delay slot is filled with a useful instruction (or an instruction which is not NOP), then the performance degradation due to the control dependency can be minimized. However, if the delay slot cannot be used, then it should be NOP instruction, which can increase the program code size. In this case, the corresponding branch instruction without a delay slot can be used to avoid using NOP. Some instructions are not permitted to be in the delay slot. The prohibited instructions are as follows. All 2-word instructions All branch and jump instructions including SWI, RETD, RET_SWI, RET_IRQ, RET BREAK instructions When a prohibited instruction is in the delay slot, the operation of CalmRISC16 is undefined or unpredictable. BSRD eoffset:13 MCU Team LSI Division System LSI Business - 14 April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual In the instruction, called branch subroutine with a delay slot, the value (PC + 4) is saved into A14 register, the instruction in the delay slot is executed, and then the program sequence is moved to (PC + 2 + eoffset:13), where PC is the address of the instruction "BSRD eoffset:13". The immediate value eoffset:13 is sign-extended to 22-bit and then added to (PC+2). In general, the 13-bit offset field appears as a label in assembly programs. If the instruction in the delay slot reads the value of A14, the value (PC+4) is read. The even offset eoffset:13 is encoded to 12bit signed offset in instruction map by dropping the least significant bit. BRA/BRAD/BRT/BRTD/BRF/BRFD eoffset:11 In the branch instructions, the target address is (PC + 2 + eoffset:11). The immediate value eoffset:11 is sign-extended to 22-bit and then added to (PC+2). The "D" in the mnemonic stands for a delay slot. In general, the 11-bit offset field appears as a label in assembly programs. BRA and BRAD instructions always branch to the target address. BRT and BRTD instructions branch to the target address if T flag is set. BRF and BRFD instructions branch to the target address if T flag is cleared. BRAD/BRTD/BRFD instructions are delay slot branch instructions, therefore the instruction in the delay slot is executed before the branch to the target address or the branch decision is made. The even offset eoffset:11 is encoded to 10-bit signed offset in instruction map by dropping the least significant bit. BRA/BRAD EC:2, eoffset:8 In the branch instructions, the target address is (PC + 2 + eoffset:8). The immediate value eoffset:8 is sign-extended to 22-bit and then added to (PC+2). The EC:2 field indicates one of the 4 external conditions from EC0 to EC3 (input pin signals to CalmRISC16). When the external condition corresponding to EC:2 is set, the program branches to the target address. BRAD has a delay slot. The even offset eoffset:8 is encoded to 7-bit signed offset in instruction map by dropping the least significant bit. BNZD R6/R7, eoffset:8 In the branch instruction, the target address is (PC + 2 + eoffset:8). The immediate value eoffset:8 is signextended to 22-bit and then added to (PC+2). "BNZD R6, eoffset:8" instruction branches to the target address if Z0 flag is cleared. "BNZD R7, eoffset:8" instruction branches if Z1 flag is cleared. Before the branch operation, the instruction decrements R6/R7, updates Z0/Z1 flag according to the decrement result, and then executes the instruction in the delay slot. The instruction is used to manage loop counter with just one cycle overhead. In the end of the loop, the value of R6/R7 is -1. When the instruction in the delay slot read the Z0/Z1 flag, the result after the decrement is read. The even offset eoffset:8 is encoded to 7-bit signed offset in instruction map by dropping the least significant bit. JMP/JPT/JPF/JSR addr:22 MCU Team LSI Division System LSI Business - 15 April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual The target address of the instructions is addr:22. JMP always branches to the target address. JPT branches to the target address if the T flag is set. JPF branches if the T flag is cleared. JSR always branches to the target address with saving the return address (PC+4) into A14. The instructions are 2 word instructions. JMP/JPT/JPF/JSR Ai The target address of the instructions is the value of Ai. JMP always branches to the target address. JPT branches to the target address if the T flag is set. JPF branches if the T flag is cleared. JSR always branches to the target address with saving the return address (PC+2) into A14. SWI #imm:6/ RET_SWI/RET_IRQ/RET_FIQ refer to the section for interrupts. RETD The instruction branches to the address in A14 after the execution of the instruction in the delay slot. When there is no useful instruction adequate to the delay slot, "JMP A14" can be used instead of "RETD". 2.4. Bit Operation The bit operations manipulate a bit in SR register or in a memory location. BITR/BITS/BITC/BITT @[A8+R1], #imm:3 The source as well as the destination is the 8-bit data in the data memory at the address (A8 + R1). The #imm:3 field chooses a bit position among the 8 bits. BITR resets the bit #imm:3 of the source, and then writes the result to the destination, the same memory location. BITS sets the bit #imm:3 of the source, and then writes the result to the destination. BITC complements the bit #imm:3 of the source, and then writes the result to the destination. BITT does not write any data to the destination. T flag indicates whether the bit #imm:3 of the source is zero. In other words, when the bit #imm:3 of the source is zero, T flag is set. BITR and BITS can be used to implement a semaphore mechanism or lock acquisition/release. CLRSR/SETSR/TSTSR bit bit : FE, IE, TE, Z0, Z1, V, PM CLRSR instruction clears the corresponding bit of SR. SETSR instruction sets the corresponding bit of SR. TSTSR tests whether the corresponding bit is zero, and stores the result in T flag. For example, when IE flag is zero, "TSTSR IE" instruction sets the T flag. We can clear the T flag by the instruction "CMP GT, R0, R0". We can set the T flag by the instruction "CMP EQ, R0, R0". MCU Team LSI Division System LSI Business - 16 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual 2.5. Miscellaneous instructions SYS #imm:5 The instruction activates the output port nSYSID. The #imm:5 is transferred to outside on DA[4:0]. The most significant 17 bits remain unchanged. The instruction is for system command to outside such as power down modes. COP #imm:13 The instruction activates the output port nCOPID. The #imm:13 is transferred to outside on COPIR[12:0]. The instruction is used to transfer instruction to coprocessor. The #imm:13 may be from 200h to 1FFFh. CLD Rn, #imm:5 / CLD #imm:5, Rn The instruction activates the output port nCOPID, nCLDID, and CLDWR. The least significant 13 bits of the instruction is transferred to outside on COPIR[12:0]. The #imm:5 is transferred to outside on DA[4:0]. The instructions move 16-bit data between Rn and a coprocessor register implied by the #imm:5 field. CLDWR signal indicates whether the data movement is from CalmRISC16 to coprocessor. The register Rn is one 8 registers from R0 to R7. NOP No operation. BREAK The software break instruction activates nBRK signal, and holds PA for one cycle. It's for debugging operation. 3. CalmRISC16 Instruction Map 15 ADD Rn, #imm:7 SUB Rn, #imm:7 LD Rn, #imm:8 LDW LDW LDW LDW LDW Rn, @[SP + edisp:9] @[SP + edisp:9], Ri Rn, @[Ai + edisp:5] Rn, @[Ai + Rj] @[An + edisp:5], Ri 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 Rn Rn Rn Rn Ri Rn Rn Ri 0 1 0 Ai Ai An 8 7 0 1 Imm:7 Imm:7 Imm:8 Edisp:9 Edisp:9 Edisp:5 Rj Edisp:5 0 MCU Team LSI Division System LSI Business - 17 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 1 1 Ri Dn Dn An An Di Di Ai Ai Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn 0 0 1 1 0 0 1 1 1 1 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 An Ai Ai Ai Ai An An An An 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 Rm Disp:4 Rj Disp:4 Rj Disp:4 Rm Disp:4 Rm Ri Ri Ri Ri Ri Ri Ri Ri Ri Ri Ri Ri Ri Ri Rn Rn Rn Rn Rn Rn Ai Ai Ai Ai Rn Rn April 2000 LDW @[An + Rm], Ri LDB Dn, @[Ai + disp:4] LDB Dn, @[Ai + Rj] LDW An, @[Ai + disp:4] LDW An, @[Ai + Rj] LDB @[An + disp:4], Di LDB @[An + Rm], Di LDW @[An + disp:4], Ai LDW @[An + Rm], Ai ADD Rn, Ri SUB ADC SBC Rn, Ri Rn, Ri Rn, Ri AND Rn, Ri OR XOR TST CMP CMP CMPU CMPU CMP LD Rn, Ri Rn, Ri Rn, Ri GE, Rn, Ri GT, Rn, Ri GE, Rn, Ri GT, Rn, Ri EQ, Rn, Ri Rn, Ri RR Rn RL Rn RRC Rn SRB Rn SR Rn SRA Rn JPF Ai JPT Ai JMP Ai JSR Ai SLB Rn DT Rn MCU Team LSI Division System LSI Business - 18 - Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 Dn 0 0 1 1 0 0 1 1 1 1 1 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Imm:8 Imm:8 Imm:8 Imm:8 Imm:8 Disp:8 Disp:8 0 0 1 1 0 1 0 1 Bs:3 Bs:3 Bs:3 Bs:3 Imm:5 Imm:6 April 2000 INCC Rn DECC Rn COM Rn COM2 Rn Rn Rn Rn Rn Rn Rn Rn 0 1 An An Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn COMC Rn EXT Rn ADD Rn, #imm:16 ADD An, #imm:16 SUB An, #imm:16 ADC Rn, #imm:16 SBC Rn, #imm:16 AND Rn, #imm:16 OR Rn, #imm:16 XOR Rn, #imm:16 TST Rn, #imm:16 CMP GE, Rn, #imm:16 CMP GT, Rn, #imm:16 CMPU GE, Rn, #imm:16 CMPU GT, Rn, #imm:16 CMP EQ, Rn, #imm:16 LD Rn, #imm:16 Reserved CMP EQ, Dn, #imm:8 AND R0, #imm:8 OR R0, #imm:8 XOR R0, #imm:8 TST R0, #imm:8 LDB R0, @[A8+ disp:8] LDB @[A8+ disp:8],R0 BITR @[A8+R1], bs:3 BITS @[A8+R1], bs:3 BITC @[A8+R1], bs:3 BITT @[A8+R1], bs:3 SYS #imm:5 SWI #imm:6 MCU Team LSI Division System LSI Business - 19 - Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 April 2000 CLRSR bs:3 SETSR bs:3 TSTSR bs:3 NOP BREAK LD R0, SR LD SR, R0 RET_FIQ RET_IRQ RET_SWI RETD LD R0, SPCL_FIQ LD R0, SPCH_FIQ LD R0, SSR_FIQ Reserved LD R0, SPCL_IRQ LD R0, SPCH_IRQ LD R0, SSR_IRQ Reserved Reserved LD R0, SSR_SWI Reserved Reserved LD SPCL_FIQ, R0 LD SPCH_FIQ, R0 LD SSR_FIQ, R0 Reserved LD SPCL_IRQ, R0 LD SPCH_IRQ, R0 LD SSR_IRQ, R0 Reserved Reserved LD SSR_SWI, R0 Reserved Reserved Bs:3 Bs:3 Bs:3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 1 0 1 0 1 0 1 0 1 0 1 MCU Team LSI Division System LSI Business - 20 - Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 21 - Reserved Reserved LD An, PC Reserved JPF adr:22 JPT adr:22 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Rn 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1 0 1 Adr[21:16] Adr[21:16] Adr[21:16] Adr[21:16] 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 Imm:6 0 1 imm:5 imm:5 Imm[21:16] Imm[21:16] 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 0 1 0 1 0 1 0 1 1 0 An Rn April 2000 An JMP adr:22 JSR adr:22 LDC Rn, @Ai Reserved LD Dn, Ei LD En, Di CMP EQ, An, Ai LD An, Ai LDW LDW Rn, @[Ai+disp:16] @[An+disp:16], Ri Ai 0 0 1 1 Dn Di An An Rn Ri 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 Ei En Ai Ai Ai An Ai An Ai An LDB Dn, @[Ai+disp:16] LDB @[An+disp:16], Di LDW An, @[Ai+disp:16] LDW @[An+disp:16], Ai CMP GE, Dn, #imm:6 ADD An, #imm:5 SUB An, #imm:5 CMP EQ, An, #imm:22 LD An, #imm:22 ADD An, Ri SUB An, Ri MUL MUL MUL MUL UU, Dn, Di US, Dn, Di SU, Dn, Di SS, Dn, Di 0 0 1 1 0 1 1 0 1 0 1 0 0 1 1 Dn Di An Ai Dn An An An An An An Dn Dn Dn Dn Rm Ri Ri Di Di Di Di Rn POP Rn[, Rm] Reserved POP An[, Am] PUSH Rn[, Rm] 0 1 Am Rm 1 1 MCU Team LSI Division System LSI Business Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 0 1 0 1 0 1 0 0 0 0 0 1 0 1 1 EC:2 H 0 1 Eoffset:11 Eoffset:11 Eoffset:11 Eoffset:11 Eoffset:11 Eoffset:11 imm:5 imm:5 Imm:13 0 1 Dn Di Eoffset:8 Eoffset:8 EC:2 0 1 Am 1 1 1 1 1 1 1 1 1 1 An Reserved PUSH BSRD An[, Am] eoffset:13 Eoffset:13 Eoffset:8 BRA EC:2, eoffset:8 Reserved BRAD EC:2, eoffset:8 BNZD H, eoffset:8 Reserved BRA eoffset:11 BRAD eoffset:11 BRF eoffset:11 BRFD eoffset:11 BRT eoffset:11 BRTD eoffset:11 CLD Dn, imm:5 CLD imm:5, Di COP imm:13 Dn[15:0] An[21:0] En[5:0] EC:2 Eoffset : R0 ~ R7 : A8 ~ A15, concatenation of En and Rn : E8 ~ E15, MS 6-bit of An : EC0,EC1,EC2,EC3 : even signed offset H[15:0] : R6, R7 SP Disp Edisp : equal to A15 : unsigned displacement : even unsigned displacement 4. Quick Reference Instruction ADD SUB op1 Rn op2 #imm:7 Ri #imm:8 LD Rn #imm:16 Ri op1 <- op2 Z0, Z1 operation op1 <- op1 + op2 op1 <- op1 + ~op2 + 1 flag T=C, Z0, Z1,V MCU Team LSI Division System LSI Business - 22 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual @[SP+edisp:9] LDW Rn @[Ai+edisp:5] @[Ai+Rj] @[Ai+disp:16] op1 <- op2 - @[SP+edisp:9] LDW @[An+edisp:5] @[An+Rm] @[Ai+disp:16] @[Ai+edisp:5] LDW An @[Ai+Rj] @[Ai+disp:16] @[An+edisp:5] LDW @[An+Rm] @[Ai+disp:16] @[SP+disp:8] LDB Dn @[Ai+disp:4] @[Ai+Rj] @[Ai+disp:16] LDB R0 @[SP+disp:8] LDB @[An+disp:4] @[Ai+Rj] @[Ai+disp:16] LDB ADC SBC AND OR XOR TST CMP GE CMP GT CMPU GE CMPU GT CMP EQ MCU Team LSI Division System LSI Business - 23 - Ri op1 <- op2 - op1 <- op2 - Ai op1 <- op2 - op1<-{8'h0,op2[7:0]} - @[A8+disp:8] op1<-{8'h0,op2[7:0]} - Di op1 <- op2[7:0] - @[A8+disp:8] Rn R0 Ri #imm:16 Ri #imm:16 Ri #imm:16 op1 <- op2[7:0] op1 <- op1 + op2 + T op1 <- op1 + ~op2 + T op1 <- op1 & op2 op1 <- op1 | op2 op1 <- op1 ^ op2 op1 & op2 op1 + ~op2 + 1, T=~N T=C,V, Z0,Z1 T=Z, Z0,Z1 Rn Rn T=Z Rn Ri #imm:16 op1 + ~op2 + 1, T=~N&~Z op1 + ~op2 + 1, T=C op1 + ~op2 + 1, T=C&~Z op1 + ~op2 + 1, T=Z April 2000 T Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual op1 <- {op1[0],op1[15:1]} op1 <- {op1[14:0],op1[15]} op1 <- {T,op1[15:1]} T=op1[0] T=op1[15] T=op1[0] T=op1[7] T=op1[0] T=op1[0] T= op1[8] T=Z, Z0,Z1,V T=Z,Z0, Z1 RR RL RRC SRB SR SRA SLB DT Rn Rn - op1 <- {8'h00,op1[15:8]} op1 <- {0,op1[15:1]} op1 <- {op1[15],op1[15:1]} op1 <- {op1[7:0],8'h00} op1 <- op1 + 0xffff COM INCC DECC COM2 COMC EXT JPF JPT JMP JSR ADD Rn Op1 <- ~op1 op1 <- op1 + T Rn op1 <- op1 + 0xffff + T op1 <- ~op1 + 1 op1 <- ~op1 + T T=C,Z0, Z1 Rn op1<-{8{op1[7]},op1[7:0]} if(T==0) PC <- op1 Z0, Z1 Ai addr:22 if(T==1) PC <- op1 PC <- op1 A14 <- PC+(2|4), PC<-op1 - Rn #imm:16 #imm:16 op1 <- op1 + op2 T=C, Z0,Z1,V ADD SUB CMP EQ AND OR XOR TST BITR BITS BITC BITT SYS SWI An #imm:5 Ri op1 <- op1 + op2 op1 <- op1 - op2 op1 + ~op2 + 1 Op1 <- op1 & {8'h00,op2} - Dn #imm:8 T=Z R0 #imm:8 op1 <- op1 | {8'h00,op2} op1 <- op1 ^ {8'h00,op2} op1 & {8'h00,op2} op1[op2] <- 0 T=Z8 @[A8+R1] bs:3 op1[op2] <- 1 op1[op2] <- ~op1[op2] op1[op2] <- op1[op2] T= op1[op2] #imm:5 #imm:6 MCU Team LSI Division System LSI Business DA[4:0] <- op1 A14 <- PC+2, PC <- op2*4 - 24 - IE, TE April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual SR[op1] <- 0 CLRSR SETSR TSTSR RETD SR SPCL_FIQ SPCH_FIQ LD R0 SSR_FIQ SPCL_IRQ SPCH_IRQ SSR_IRQ SSR_SWI SR SPCL_FIQ SPCH_FIQ LD SSR_FIQ SPCL_IRQ SPCH_IRQ SSR_IRQ SSR_SWI PC LD An Ai #imm:22 CMP EQ LDC LD LD CMP GE MUL UU MUL US MUL SU MUL SS Dn Di An Rn Rn En Dn Ai #imm:22 @Ai Ei Ri #imm:6 R0 bs:3 - SR[op1] <- 1 T <- ~SR[op1] PC <- A14 - - op1 <- op2 - op1 <- op2 op1 <- op2 + 4 op1 <- op2 op1 <- op2 op1 + ~op2 + 1 op1 <- PM[op2] op1 <- {10'h000, op2} op1 <- op2[5:0] op1 + ~op2 + 1 op1<-{0,op1[7:0]} * {0,op2[7:0]} op1<-{0,op1[7:0]}*{op2[7],op2[7:0]} op1<-{op1[7],op1[7:0]}*{0,op2[7:0]} op1 <-{op1[7],op1[7:0]}* {op2[7],op2[7:0]} T=Z22 T=~N - POP Rn Rm op1<-@[SP+2], op2<-@[SP+4], SP<-SP+4 - 25 - - MCU Team LSI Division System LSI Business April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual Rm Am @[SP]<-op1,@[SP-2]<-op2,SP<-SP-4 En<-@[SP+2], Rn<-@[SP+4], Em<@[SP+6], Rm<-@[SP+8], SP<-SP+8 @[SP]<-Rn, @[SP-2]<-En, @[SP-4] Rn An PUSH BSRD BRA/BRAD BNZD An eoffset:13 EC:2 R6 Am eoffset:8 eoffset:8 Z0 BNZD BRA/BRAD BRF/BRFD BRT/BRTD CLD CLD COP R7 eoffset:11 eoffset:11 eoffset:11 Dn imm:5 imm:13 eoffset:8 imm:5 Di - Z1 - MCU Team LSI Division System LSI Business - 26 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual ADC (1) Add with Carry Register ADC Rn, Ri Description The ADC (Add with Carry Register) instruction is used to synthesize 32-bit addition. If register pairs R0, R1 and R2, R3 hold 32-bit values (R0 and R2 hold the least-significant word), the following instructions leave the 32-bit sum in R0, R1: ADD R0, R2 ADC R1, R3 The instruction ADC R0, R0 produces a single-bit Rotate Left with Carry (17-bit rotate through the carry) on R0. ADC adds the value of register Rn, and the value of the Carry flag (stored in the T bit), and the value of register Ri, and stores the result in register Rn. The T bit and the V flag are updated based on the result. 15 14 13 12 11 8 7 6 5 4 3 0 1 0 0 0 Rn 0 0 1 0 Ri Operation Rn := Rn + Ri + T bit T bit := Carry from (Rn + Ri + T bit) V flag := Overflow from (Rn + Ri + T bit) if(Rn == R6/R7) Z0/Z1 flag := ((Rn + Ri + T) == 0) Exceptions Notes None. None. MCU Team LSI Division System LSI Business - 27 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual ADC (2) Add with Carry Immediate ADC Rn, # Description The ADC (Add with Carry Immediate) instruction is used to synthesize 32-bit addition with an immediate operand. If register pair R0, R1 holds a 32-bit value (R0 holds the least-significant word), the following instructions leave the 32-bit sum with 87653456h in R0, R1: ADD R0, #3456h ADC R1, #8765h ADC adds the value of register Rn, and the value of the Carry flag (stored in the T bit), and the 16-bit immediate operand, and stores the result in register Rd. The T bit and the V flag are updated based on the result. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 0 0 1 0 1 1 1 1 Rn Operation Rn := Rn + Exceptions Notes None. This is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. Unlike 1-word instructions, therefore, fetching of ADC Rn, MCU Team LSI Division System LSI Business - 28 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual ADD (1) Add Register ADD Rn, Ri Description The ADD (Add Register) instruction is used to add two 16-bit values in registers. 32-bit addition can be achieved by executing ADC instruction in pair with this instruction (see page 27). ADD adds the value of register Rn, and the value of register Ri, and stores the result in register Rn. The T bit and the V flag are updated based on the result. 15 14 13 12 11 8 7 6 5 4 3 0 1 0 0 0 Rn := Rn + Ri Rn 0 0 0 0 Ri Operation T bit := Carry from (Rn + Ri) V flag := Overflow from (Rn + Ri) if(Rn == R6/R7) Z0/Z1 flag := ((Rn + Ri) == 0) Exceptions Notes None. None. MCU Team LSI Division System LSI Business - 29 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual ADD (2) Add Small Immediate ADD Rn, # Description This form of ADD instruction is used to add a 7-bit (positive) immediate value to a register ADD adds the value of register Rn, and the value of 15 14 13 12 11 8 7 6 0 0 0 0 0 Rn 0 Operation Rn := Rn + Exceptions Notes None. MCU Team LSI Division System LSI Business - 30 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual ADD (3) Add Immediate ADD Rn, # Description The ADD (Add Immediate) instruction is used to add a 16-bit immediate value to a register. 32-bit addition or subtraction can be achieved by executing ADC or SBC instruction in pair with this instruction (see page 28 and 99 for examples). ADD adds the value of register Rn, and the value of 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 0 0 0 0 1 1 1 1 Rn Operation Rn := Rn + Exceptions Notes None. This is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. Unlike 1-word instructions, therefore, fetching of ADD Rn, MCU Team LSI Division System LSI Business - 31 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual ADD (4) Add Extended Register ADD An, Ri Description The ADD (Add Extended Register) instruction is used to add a 16-bit unsigned register value to a 22-bit register. This instruction adds the value of 16-bit register Ri, and the value of 22-bit register An, and stores the result in register An. 15 14 13 12 11 10 8 7 6 5 4 3 0 1 0 1 0 0 An 1 1 0 0 Ri Operation Exceptions Notes An := An + Ri None. None. MCU Team LSI Division System LSI Business - 32 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual ADD (5) Add Immediate to Extended Register ADD An, # Description This form of ADD instruction is used to add a 16-bit unsigned immediate value to a 22-bit register. This instruction adds the value of 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 1 0 0 0 0 0 0 1 1 1 1 1 0 An Operation Exceptions Notes An := An + MCU Team LSI Division System LSI Business - 33 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual ADD (6) Add 5-bit Immediate to Extended Register ADD An, # Description This form of ADD instruction is used to add a 5-bit unsigned immediate value to a 22-bit register. This instruction adds the value of 5-bit immediate 15 14 13 12 11 10 8 7 6 5 4 0 1 0 1 0 1 An 0 1 0 Operation Exceptions Notes An := An + MCU Team LSI Division System LSI Business - 34 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual AND (1) AND Register AND Rn, Ri Description The AND (AND Register) instruction is used to perform bitwise AND operation on two values in registers, Rn and Ri. The result is stored in register Rn. The T bit is updated based on the result. 15 14 13 12 11 8 7 6 5 4 3 0 1 0 0 0 Rn := Rn & Ri Rn 0 1 0 0 Ri Operation T bit := ((Rn & Ri) == 0) if(Rn == R6/R7) Z0/Z1 flag := ((Rn & Ri) == 0) Exceptions Notes None. None. MCU Team LSI Division System LSI Business - 35 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual AND (2) AND Small Immediate AND R0, # Description The AND (AND Small Immediate) instruction is used to perform an 8-bit bitwise AND operation on two values in register R0 and 15 14 13 12 11 10 9 8 7 0 1 0 0 1 1 0 0 0 Operation Exceptions Notes R0 := R0 & MCU Team LSI Division System LSI Business - 36 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual AND (3) AND Large Immediate AND Rn, # Description This type of AND instruction is used to perform bitwise AND operation on two values in register Rn and 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 0 1 0 0 1 1 1 1 Rn Operation Rn := Rn & Exceptions Notes None. This is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. Unlike 1-word instructions, therefore, fetching of this instruction takes 2 cycles. MCU Team LSI Division System LSI Business - 37 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual BITop BIT Operation BITop @[A8+R1], # Description The BITop (Bit Operation) instruction is used to perform a bit operation on an 8-bit memory value. The allowed operations include reset (BITR), set (BITS), complement (BITC), and test (BITT). BITop fetches the value of memory location specified by @(A8+R1), performs the specified operation on the specified bit, and stores the result back into the same memory location 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 1 0 0 1 1 1 1 0 0 0 0 OP Operation Temp := MEM[A8+R1] T bit := ~Temp[ Exceptions Notes None. The address used to access data memory is obtained from the addition of two registers A8 and R1. No other registers can be used for this address calculation. MCU Team LSI Division System LSI Business - 38 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual BNZD Branch Not Zero with Autodecrement BNZD H, Description The BNZD (Branch Not Zero with Delay Slot) instruction is used to change the program flow when the specified register value does not evaluate to zero. After evaluation, the value in register is automatically decremented. A typical usage of this instruction is as a backward branch at the end of a loop. LOOP: ... BNZD R6, LOOP ADD R4, 3 // if (Z0 != 0) go back to LOOP // delay slot In the above example, R6 is used as the loop counter. After specified loop iterations, BNZD is not taken and the control will come out of the loop, and R6 will have -1. For a loop with "N" iterations, the counter register used should be initially set to is taken or not. 15 14 13 12 11 10 9 8 7 6 0 "(N-1)". BNZD has a single delay slot; the instruction that immediately follows BNZD will be executed always regardless of whether BNZD 1 1 0 0 0 1 1 H 0 Operation if(H == R6) { if(Z0 != 0) PC := PC + 2 + Exceptions Notes None. When BNZD checks if H is zero by looking up the Z0 (for R6) or Z1 (for R7) bit in SR, these flags are updated as BNZD decrements the value of the register. For the first iteration, however, the user is responsible for resetting the flag, Z0 or Z1, before the loop starts execution. MCU Team LSI Division System LSI Business - 39 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual BR Conditional Branch BRtype Description The BR (Conditional Branch) instruction is used to change the program flow conditionally or unconditionally. The allowed forms of the instruction include BRA (always), BRAD (always with delay slot), BRT (when T bit is set), BRTD (when T bit is set, with delay slot), BRF (when T bit is clear), and BRFD (when T bit is clear, with delay slot). The branch target address is calculated by 1. sign-extending 15 14 13 12 11 10 9 0 1 1 0 D Operation PC := PC + 2 + Exceptions Notes None. None. MCU Team LSI Division System LSI Business - 40 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual BRA EC Branch on External Condition BRA(D) EC:2 Description The BRA EC (Branch on External Condition) instruction is used to change the program flow when a certain external condition is set. A typical usage of this instruction is to branch after a coprocessor operation as shown below: COP 15 14 13 12 11 10 9 8 7 6 0 1 1 0 0 0 D 0 Operation if (ExternalCondition_n == True) PC := PC + 2 + Exceptions Notes None. None. MCU Team LSI Division System LSI Business - 41 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual BREAK BREAK BREAK Description The BREAK instruction suspends the CalmRISC core for 1 cycle by keeping PC from increasing. Processor resumes execution after 1 cycle. This instruction is used for debugging purposes only and thus should not be used in normal operating modes. A core signal nBRK is asserted low for the cycle. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 1 1 1 1 0 1 0 0 1 1 0 0 1 Operation Exceptions Notes No operation with PC suspended for a single cycle. None. None. MCU Team LSI Division System LSI Business - 42 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual BSRD Branch Subroutine with Delay Slot BSRD Description The BSRD (Branch Subroutine with Delay slot) instruction is used to change the program flow to a subroutine by assigning the address of the subroutine to PC after saving the return address (PC+4) in the link register, or A14. The address of the subroutine is calculated by: 1. sign-extending 15 14 13 12 11 0 1 0 1 1 A14 := PC + 4 PC := PC + 2 + Operation Exceptions Notes None. None. MCU Team LSI Division System LSI Business - 43 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual CLD Coprocessor Load CLD Dn, Description The CLD (Coprocessor Load) instruction is used to transfer data from and to coprocessor by generating the core signals nCLDID and CLDWR. The content of DA[4:0] is 15 14 13 12 11 10 8 7 6 5 4 0 1 1 1 0 0 0 0 imm:5 M Dn/Di Operation (M == 0, read) DA[4:0] := Exceptions Notes None. None. MCU Team LSI Division System LSI Business - 44 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual CLRSR Clear SR CLRSR bs:3 Description The CLRSR (Clear SR) instruction is used to clear a specified bit in SR as follows: CLRSR FE / IE / TE / V / Z0 / Z1 / PM To clear the T bit, one can do as follows: CMP GT, R0, R0 To turn on a specified bit in SR, the SETSR instruction (in page 100 ) is used. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 1 0 0 1 1 1 1 0 1 0 0 0 0 Operation Exceptions Notes SR[ MCU Team LSI Division System LSI Business - 45 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual CMP (1) Compare Register CMPmode Rn, Ri Description The CMP (Compare Register) instruction is used to compare two values in registers Rn and Ri. The allowed modes include GE (Greater or Equal), GT (Greater Than), UGE (Unsigned Greater or Equal), UGT (Unsigned Greater Than), and EQ (Equal). CMP subtracts the value of Ri from the value of Rn and performs comparison based on the result. The contents of Rn and Ri are not changed after this operation. The T bit is updated for later reference. 15 14 13 12 11 8 7 6 5 4 3 0 1 0 0 0 Temp := Rn - Ri Rn 1 Ri Operation T bit := ~Negative ~Negative && ~Zero Carry Carry && ~Zero Zero if ( Exceptions Notes None. None. MCU Team LSI Division System LSI Business - 46 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual CMP (2) Compare Immediate CMPmode Rn, # Description The CMP (Compare Immediate) instruction is used to compare two values in register Rn and 15 14 13 12 11 10 8 7 6 5 4 3 0 1 0 0 0 1 1 1 1 1 Rn Operation Temp := Rn - Exceptions Notes None. This is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. Unlike 1-word instructions, therefore, fetching of CMPmode # MCU Team LSI Division System LSI Business - 47 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual CMP (3) Compare Short Immediate CMP GE, Dn, # Description The CMP (Compare Immediate) instruction is used to perform signed-comparison of the register Dn and an unsigned immediate value 15 14 13 12 11 10 8 7 6 5 4 3 0 1 0 1 0 0 Dn 0 1 imm:6 Operation Exceptions Notes T bit := ~Negative of (Rn - None. None MCU Team LSI Division System LSI Business - 48 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual CMPEQ (1) Compare Equal Extended Register CMP EQ, An, Ai Description The CMP EQ (Compare Equal Extended Register) instruction is used to compare two values in registers An and Ai. This instruction is a restricted form of more general CMPmode instructions for a 22-bit equality comparison between register values. 15 14 13 12 11 10 8 7 6 5 4 3 2 0 1 0 1 0 1 An 0 0 0 1 0 Ai Operation T bit := (An == Ai) An or Ai refers to registers from A8 to A15 with their 6-bit extensions. Exceptions Notes None. None. MCU Team LSI Division System LSI Business - 49 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual CMPEQ (2) Compare Equal Small Immediate CMP EQ, Dn, # Description The CMP EQ (Compare Equal Small Immediate) instruction is used to compare two values in register Dn and 15 14 13 12 11 10 8 7 0 1 0 0 1 0 Dn Operation T bit := ((Dn - Exceptions Notes None. None. MCU Team LSI Division System LSI Business - 50 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual CMPEQ (3) Compare Equal Large Immediate CMP EQ An, # Description The CMP EQ (Compare Equal Large Immediate) instruction is used to compare two values in register An and 15 14 13 12 11 10 8 7 6 5 0 1 0 1 0 0 An 1 0 Operation T bit := Zero from (An - Exceptions Notes None. This is a 2-word instruction, where the 16-bit immediate ( MCU Team LSI Division System LSI Business - 51 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual COM Complement COMmode Rn Description The COM (Complement) instruction is used to compute 1's or 2's complement of a register value Rn. Utilizing various modes, 32-bit complement operation can be done. If register pair R0, R1 holds a 32-bit value (R0 holds the least-significant word), the following instructions leave the 32-bit 2's complement in R0, R1: COM2 R0 COMC R1 // 2's complement // 2's complement with carry COM computes the 1's complement of the value of register Rn. COM2 computes the 2's complement, and COMC computes the 2's complement value when T bit has been set. If T bit is clear, COM2 is equivalent to COM. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 1 1 1 1 1 0 Rn Operation if ( // COM // COM2 T bit := Carry from (~Rn + 1) } if ( Exceptions Notes None. None. MCU Team LSI Division System LSI Business - 52 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual COP Coprocessor COP Description The COP (Coprocessor) instruction is used to perform a coprocessor operation, specified by 15 14 13 12 0 1 1 1 Operation Exceptions Notes None. None. MCU Team LSI Division System LSI Business - 53 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual DECC Decrement with Carry DECC Rn Description The DECC (Decrement with Carry) instruction is used to synthesize 32-bit decrement. If register pair R0, R1 holds a 32-bit value (R0 holds the leastsignificant word), the following instructions leave the 32-bit decremented value in R0, R1: DEC R0 DECC R1 DECC decrements the value of Rn by 1 only if the Carry flag (stored in the T bit) is clear, and stores the result back in register Rn. The T bit and the V flag are updated based on the result. // this is implemented by ADD R0, -1 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 1 0 1 1 1 1 1 0 Rn Operation Rn := Rn - 1 + T bit T bit := Carry from (Rn - 1 + T bit) V flag := Overflow from (Rn -1 + T bit) if(Rn == R6/R7) Z0/Z1 := ((Rn - 1 + T) == 0) Exceptions Notes None. None. MCU Team LSI Division System LSI Business - 54 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual DT Decrement and Test DT Rn Description The DT (Decrement and Test) instruction is used to decrement the value of a specified register and test it. This instruction provides a compact way to control register indexing for loops. The T bit and the V flag are updated based on the result. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 1 0 0 1 1 1 1 0 Rn Operation Rn := Rn - 1 T bit := ((Rn - 1) == 0) V flag := Overflow from (Rn - 1) if(Rn == R6/R7) Z0/Z1 := ((Rn - 1) == 0) Exceptions Notes None. None. MCU Team LSI Division System LSI Business - 55 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual EXT Sign-Extend EXT Rn Description The EXT (Sign Extend) instruction is used to sign-extend an 8-bit value in Rn. This instruction copies Rn[7] to Rn[15:8]. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 1 1 1 1 1 1 1 0 Rn Operation Exceptions Notes All bits from Rn[15] to Rn[8] := Rn[7] if(Rn == R6/R7) Z0/Z1 := (Result == 0) None. None. MCU Team LSI Division System LSI Business - 56 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual INCC Increment with Carry INCC Rn Description The INCC (Increment with Carry) instruction is used to synthesize 32-bit increment. If register pair R0, R1 holds a 32-bit value (R0 holds the leastsignificant word), the following instructions leave the 32-bit incremented value in R0, R1: INC R0 INCC R1 INCC increments the value of Rn by 1 only if the Carry flag (stored in the T bit) is set, and stores the result back in register Rn. The T bit and the V flag are updated based on the result. // will be replaced by ADD R0, 1 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 1 0 1 0 1 1 1 0 Rn Operation Rn := Rn + T bit T bit := Carry from (Rn + T bit) V flag := Overflow from (Rn + T bit) if(Rn == R6/R7) Z0/Z1 := ((Rn + T0) == 0) Exceptions Notes None. None. MCU Team LSI Division System LSI Business - 57 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual JMP (1) Jump Register JPF/JPT/JMP/JSR Ai Description The Jump Register instructions change the program flow by assigning the value of register Ai into PC. JPF and JPT are conditional jumps that check the T bit to determine whether or not to jump to the target address. JMP unconditionally jumps to the target. JSR is an unconditional jump but saves the return address (the immediately following instruction to JSR) in the link register, A14. At the end of each subroutine, JMP A14 will change the program flow back to the original call site. 15 14 13 12 11 10 9 8 M[1] 7 6 5 4 3 M[0] 2 0 1 0 0 0 0 1 1 1 1 1 0 Ai Operation (M == 00, JPF) if (T bit == FALSE) PC := Ai (M == 01, JPT) if (T bit == TRUE) PC := Ai (M == 10, JMP) PC := Ai (M == 11, JSR) A14 := PC + 2 PC := Ai Exceptions Notes None. There is no delay slot for these instructions. Therefore, when conditional branch JPF or JPT is taken, the instruction in the pipeline which is fetched from PC+2 will be squashed. In case of JMP and JSR (always taken), the following instruction fetched will be always squashed. MCU Team LSI Division System LSI Business - 58 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual JMP (2) Jump Immediate JPF/JPT/JMP/JSR Description The Jump Immediate instructions change the program flow by assigning the value of 15 14 13 12 11 10 9 8 7 6 5 0 1 0 0 1 1 1 1 1 Operation ( Exceptions Notes None. These are 2-word instructions, where the 16-bit immediate ( MCU Team LSI Division System LSI Business - 59 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual LD (1) Load Register LD Rn, Ri Description The LD (Load Register) instruction is used to transfer a register value to a register. 15 14 13 12 11 8 7 6 5 4 3 0 1 0 0 0 Rn := Ri Rn 1 1 0 1 Ri Operation Exceptions Notes if(Rn == R6/R7) Z0/Z1 := (Ri == 0) None. None. MCU Team LSI Division System LSI Business - 60 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual LD (2) Load Extended Register LD An, Ai Description 15 14 13 This form of LD instruction (Load Extended Register) is used to load a 22-bit register value to a 22-bit register. 12 11 10 9 8 7 6 5 4 3 0 1 0 1 0 1 An 0 0 0 1 1 Ai Operation Exceptions Notes An := Ai None. None. MCU Team LSI Division System LSI Business - 61 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual LD (3) Load Short Immediate LD Rn, # Description The LD (Load Short Immediate) instruction is used to load an 8-bit immediate value to a register. 15 14 13 12 11 8 7 0 0 0 0 1 Rn Operation Exceptions Notes Rn[15:8] := 0, Rn[7:0] := MCU Team LSI Division System LSI Business - 62 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual LD (4) Load Immediate LD Rn, # Description This form of LD instruction (Load Immediate) is used to load a 16-bit immediate value to a register. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 1 1 0 1 1 1 1 1 Rn Operation Exceptions Notes Rn := MCU Team LSI Division System LSI Business - 63 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual LD (5) Load Large Immediate LD An, # Description This form of LD instruction (Load Large Immediate) is used to load a 22-bit immediate value to an extended register An. 15 14 13 12 11 10 8 7 6 5 0 1 0 1 0 1 An 1 0 Operation Exceptions Notes An := MCU Team LSI Division System LSI Business - 64 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual LD RExt Load Register Extension LD Dn, Ei / LD En, Di Description 15 14 13 The LD RExt (Load Register Extension) instructions are used to transfer a register value to and from a 6-bit extension register. 12 11 8 7 6 5 4 3 2 0 1 0 1 0 0 Dn(or Di) 0 0 0 1 M Ei (or En) Operation (M == 0, LD Dn, Ei) Dn := Ei (zero-extended to 16 bits) (M == 1, LD En, Di) En := Di (lower 6 bits only) Exceptions Notes None. None. MCU Team LSI Division System LSI Business - 65 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual LDB (1) Load Byte Register Disp. LDB Dn, @[Ai+ Description The LDB (Load Byte Register Displacement) instruction is used to load a byte from or to data memory at the location specified by the register Ai and a 4-bit displacement. 15 14 13 12 11 10 8 7 6 4 3 0 0 1 1 M 0 Dn or Di 0 Ai or An Operation (M == 0, LDB Dn, @[Ai+ Exceptions Notes None. None. MCU Team LSI Division System LSI Business - 66 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual LDB (2) Load Byte Register Large Disp. LDB Dn, @[Ai+ Description The LDB (Load Byte Register Large Displacement) instruction is used to load a byte from or to data memory at the location specified by the register Ai and a 16bit displacement. 15 14 13 12 11 10 8 7 6 5 4 3 2 0 1 0 1 0 0 Dn or Di 0 0 1 1 M Ai or An Operation (M == 0, LDB Dn, @[Ai+ Exceptions Notes None. This is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. Unlike 1-word instructions, therefore, fetching of this instruction takes 2 cycles. MCU Team LSI Division System LSI Business - 67 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual LDB (3) Load Byte Register Indexed LDB Dn, @[Ai+Rj] / LDB @[An+Rm], Di Description The LDB (Load Byte Register Indexed) instruction is used to load a byte from or to data memory at the location specified by the register Ai (or An) and the second register Rj (or Rm). 15 14 13 12 11 10 8 7 6 4 3 0 0 1 1 M 0 Dn or Di 1 Ai or An Rj or Rm Operation (M == 0, LDB Dn, @[Ai+Rj]) Dn := DM[(Ai+Rj] (M == 1, LDB @[An+Rm], Di) DM[(An+Rm)] := Di Exceptions Notes None. None. MCU Team LSI Division System LSI Business - 68 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual LDB (4) Load Byte to R0 Register Disp. LDB R0, @[A8+ Description The LDB (Load Byte to R0 Register Displacement) instruction is used to load a byte from or to data memory at the location specified by the register A8 and an 8bit displacement. 15 14 13 12 11 10 9 8 7 0 1 0 0 1 1 1 0 M Operation (M == 0, LDB R0, @[A8+ Exceptions Notes None. This single-word instruction allows a user to access a wider range of data memory than the LDB (1) instruction by providing a larger displacement, at the expense of the restrictions that only the R0 and A8 registers are used for data transfer and address computation. MCU Team LSI Division System LSI Business - 69 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual LDC Load Code LDC Rn, @Ai Description The LDC instruction is used to transfer a register value from the program memory. The program memory address is specified by the 22-bit register An. LDC is useful to look up the data stored in program memory, such as the coefficient table for certain numerical algorithms. 15 14 13 12 11 8 7 6 5 4 3 2 0 1 0 1 0 Rn := PM[Ai] None. None. Rn 0 0 0 0 0 Ai Operation Exceptions Notes MCU Team LSI Division System LSI Business - 70 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual LD PC Load Program Counter LD An, PC Description The LD PC (Load Program Counter) instruction is used to transfer the value of PC into a 22-bit register An. This instruction provides a way to implement position independent code (PIC) on CalmRISC16 even in the absence of general virtual memory support. After executing this instruction, An will be used to compute a PC-relative location of a data item or a code section. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 1 0 0 1 1 1 1 0 1 1 1 1 0 An Operation Exceptions Notes An := PC + 4 None. None. MCU Team LSI Division System LSI Business - 71 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual LD SvR (1) Load from Saved Register LD R0, SPCL_* / LD R0, SPCH_* / LD R0, SSR_* Description The LD SvR (Load from Saved Register) instructions are used to transfer a value from the specified interrupt register, e.g., SSR_FIQ. Only R0 register is used for this data transfer. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 1 1 1 1 0 1 0 1 0 Operation R0 := Exceptions Notes None. None. MCU Team LSI Division System LSI Business - 72 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual LD SvR (2) Load to Saved Register LD SPCL_*, R0 / LD SPCH_*, R0 / LD SSR_*, R0 Description The LD SvR (Load to Saved Register) instructions are used to transfer a value to the specified interrupt register, e.g., SSR_FIQ. Only R0 register is used for this data transfer. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 1 1 1 1 0 1 0 1 1 Operation Exceptions Notes None. None. MCU Team LSI Division System LSI Business - 73 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual LD SR Load Status Register LD R0, SR / LD SR, R0 Description The LD SR (Load Status Register) instruction is used to transfer a value to and from SR. Only R0 register is used for this operation. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 1 1 1 1 0 1 0 0 1 1 0 1 M Operation (M == 0, LD R0, SR) R0 := SR (M == 1, LD SR, R0) SR := R0 Exceptions Notes None. None. MCU Team LSI Division System LSI Business - 74 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual LDW (1) Load Word Stack Disp. LDW Rn, @[SP+ Description The LDW (Load Word Stack Displacement) instruction is used to load a word from or to data memory at the location specified by the SP register (or A15) and an even 9-bit displacement. 15 14 13 12 11 8 7 0 0 0 1 M Rn or Ri Operation (M == 0, LDW Rn, @[SP+ Exceptions Notes None. For memory transfer per word, the (byte) address need to be aligned to be even. Thus, if (SP + MCU Team LSI Division System LSI Business - 75 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual LDW (2) Load Word Register Small Disp. LDW Rn, @[Ai+ Description The LDW (Load Word Register Displacement) instruction is used to load a word from or to data memory at the location specified by the register Ai and a 5-bit even displacement from 0 to 30. 15 14 13 12 11 8 7 6 4 3 0 0 1 0 M Rn or Ri 0 Ai or An Operation (M == 0, LDW Rn, @[Ai+ Exceptions Notes None. For memory transfer per word, the (byte) address need to be aligned to be even. Thus, if (Ai + MCU Team LSI Division System LSI Business - 76 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual LDW (3) Load Word Register Disp. LDW Rn, @[Ai+ Description The LDW (Load Word Register Large Displacement) instruction is used to load a word from or to data memory at the location specified by the register Ai and a 16bit displacement. 15 14 13 12 11 8 7 6 5 4 3 2 0 1 0 1 0 Rn or Ri 0 0 1 0 M Ai or An Operation (M == 0, LDW Rn, @[Ai+ Exceptions Notes None. This is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. Unlike 1-word instructions, therefore, fetching of this instruction takes 2 cycles. For memory transfer per word, the (byte) address need to be aligned to be even. Thus, if (Ai + MCU Team LSI Division System LSI Business - 77 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual LDW (4) Load Word Register Indexed LDW Rn, @[Ai+Rj] / LDW @[An+Rm], Ri Description The LDW (Load Word Register Indexed) instruction is used to load a word from or to data memory at the location specified by the register Ai (or An) and the second register Rj (or Rm), which is an unsigned value. 15 14 13 12 11 8 7 6 4 3 0 0 1 0 M Rn or Ri 1 Ai or An Rj or Rm Operation (M == 0, LDW Rn, @[Ai+Rj]) Rn := DM[(Ai+Rj] (M == 1, LDW @[An+Rm], Ri) DM[(An+Rm)] := Ri Exceptions Notes None. For memory transfer per word, the (byte) address needs to be aligned to be even. Thus, if (Ai + Rj) or (An + Rm) is an odd number, it will be made even by clearing the least significant bit. MCU Team LSI Division System LSI Business - 78 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual LDW (5) Load Word Register Small Disp. LDW An, @[Ai+ Description The LDW (Load Word Register Displacement) instruction is used to load 2 word from or to data memory at the location specified by the register Ai and a 5-bit even displacement from 0 to 30. 15 14 13 12 11 8 7 6 4 3 0 0 1 1 M 1 An 0 Ai Operation (M == 0, LDW An, @[Ai+ Exceptions Notes None. For memory transfer per word, the (byte) address need to be aligned to be even. Thus, if (Ai + MCU Team LSI Division System LSI Business - 79 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual LDW (6) Load Word Register Disp. LDW An, @[Ai+ Description The LDW (Load Word Register Large Displacement) instruction is used to load 2 word from or to data memory at the location specified by the register Ai and a 16bit displacement. 15 14 13 12 11 8 7 6 5 4 3 2 0 1 0 1 0 1 An 0 0 1 1 M Ai Operation (M == 0, LDW An, @[Ai+ Exceptions Notes None. This is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. Unlike 1-word instructions, therefore, fetching of this instruction takes 2 cycles. For memory transfer per word, the (byte) address need to be aligned to be even. Thus, if (Ai + MCU Team LSI Division System LSI Business - 80 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual LDW (7) Load Word Register Indexed LDW An, @[Ai+Rj] / LDW @[Ai+Rj], An Description The LDW (Load Word Register Indexed) instruction is used to load 2 word from or to data memory at the location specified by the register Ai and the second register Rj, which is an unsigned value. 15 14 13 12 11 8 7 6 4 3 0 0 1 1 M 1 An 1 Ai Rj Operation (M == 0, LDW An, @[Ai + Rj]) En := DM[(Ai + Rj)] Rn := DM[(Ai + Rj + 2)] (M == 1, LDW @[Ai + Rj], An) DM[(Ai + Rj)] := En DM[(Ai + Rj + 2)] := Rn Exceptions Notes None. For memory transfer per word, the (byte) address needs to be aligned to be even. Thus, if (Ai + Rj) is an odd number, it will be made even by clearing the least significant bit. MCU Team LSI Division System LSI Business - 81 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual MUL Multiplication MUL Mode, Dn, Di Description The instruction MUL performs 8x8 multiplication of the least significant byte of Dn and the least significant byte of Di. Dn and Di are registers from R0 to R7. The 16-bit multiplication result is written back to Dn. The mode is one of UU, US, SU, SS. The mode indicates each operand is signed value or unsigned value. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 0 M1 Dn 1 1 0 1 M2 Di Operation if(M1 == 0 && M2 == 0) else if(M1 == 0 && M2 == 1) else if(M1 == 1 && M2 == 0) else // mode == SS // mode = UU // mode == US // mode == SU Dn := lower 16 bits of ({0,Dn[7:0]} * {0, Di[7:0]}) Dn := lower 16 bits of ({0,Dn[7:0]} * {Di[7],Di[7:0]}) Dn := lower 16 bits of ({Dn[7],Dn[7:0]} * {0,Di[7:0]}) Dn := lower 16 bits of ({Dn[7],Dn[7:0]} * {Di[7],Di[7:0]}) Exceptions Notes None. None. MCU Team LSI Division System LSI Business - 82 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual NOP No Operation NOP Description The NOP (No Operation) instruction does not perform any operation. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 1 None. None. None. 1 1 1 0 1 0 0 1 0 0 0 0 Operation Exceptions Notes MCU Team LSI Division System LSI Business - 83 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual OR (1) OR Register OR Rn, Ri Description The OR (OR Register) instruction is used to perform bitwise OR operation on two values in registers, Rn and Ri. The result is stored in register Rn. The T bit is updated based on the result. 15 14 13 12 11 8 7 6 5 4 3 0 1 0 0 0 Rn := Rn | Ri Rn 0 1 0 1 Ri Operation T bit := ((Rn | Ri) == 0) if(Rn == R6/R7) Z0/Z1 := ((Rn|Ri) == 0) Exceptions Notes None. None. MCU Team LSI Division System LSI Business - 84 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual OR (2) OR Small Immediate OR R0, # Description The OR (OR Small Immediate) instruction is used to perform bitwise OR operation on two values in register R0 and 15 14 13 12 11 10 9 8 7 0 1 0 0 1 1 0 0 1 Operation Exceptions Notes R0 := R0 | MCU Team LSI Division System LSI Business - 85 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual OR (3) OR Large Immediate OR Rn, # Description This type of OR instruction is used to perform bitwise OR operation on two values in register Rn and 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 0 1 0 1 1 1 1 1 Rn Operation Rn := Rn | Exceptions Notes None. This is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. Unlike 1-word instructions, therefore, fetching of this instruction takes 2 cycles. MCU Team LSI Division System LSI Business - 86 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual POP(1) Load register from Stack POP Rn, Rm / POP Rn Description The POP instruction load one or two 16-bit data from software stack to general registers. In the instruction of "POP Rn, Rm", there are some restrictions on Rn and Rm. Rn and Rm should not be R15. If Rn is one of the 8 registers from R0 to R7, Rm should also be one of them. If Rn is one of the registers from R8 to R14, Rm should also be one of them. For example, "POP R7, R8" is illegal. If Rn is the same as Rm, pop operation occurs only once. "POP Rn, Rn" is equivalent to "POP Rn". 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 0 if(Rn == Rm) { SP := SP + 2 } else { Rm // POP Rn 1 1 1 0 0 Rn Operation Rn := DM[SP + 2] Rn := DM[SP + 2] Rm := DM[SP + 4] SP := SP + 4 } Exceptions Notes None. None. MCU Team LSI Division System LSI Business - 87 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual POP(2) Load register from Stack POP An, Am / POP An Description The POP instruction load one or two 22-bit data from software stack to extended registers. In the instruction of "POP An, Am", there are some restrictions on An and Am. An and Am should not be A15. If An is the same as Am, pop operation occurs only once. "POP An, An" is equivalent to "POP An". 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 0 1 Am // POP An 1 1 1 0 1 An Operation if(An == Am) { En := lower 6 bits of DM[SP + 2] Rn := DM[SP + 4] SP := SP + 4 } else { En := lower 6 bits of DM[SP + 2] Rn := DM[SP + 4] Em := lower 6 bits of DM[SP + 6] Rm := DM[SP + 8] SP := SP + 8 } Exceptions Notes None. None. MCU Team LSI Division System LSI Business - 88 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual PUSH(1) Load register to Stack PUSH Rn, Rm / PUSH Rn Description The PUSH instruction load one or two 16-bit data from general registers to software stack. In the instruction of "PUSH Rn, Rm", there are some restrictions on Rn and Rm. Rn and Rm should not be R15. If Rn is one of the 8 registers from R0 to R7, Rm should also be one of them. If Rn is one of the registers from R8 to R14, Rm should also be one of them. For example, "PUSH R7, R8" is illegal. If Rn is the same as Rm, push operation occurs only once. "PUSH Rn, Rn" is equivalent to "PUSH Rn". 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 0 if(Rn == Rm) { Rm // PUSH Rn 1 1 1 1 0 Rn Operation DM[SP] := Rn SP := SP - 2 } else { DM[SP] := Rn DM[SP - 2] := Rm SP := SP - 4 } Exceptions Notes None. None. MCU Team LSI Division System LSI Business - 89 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual PUSH(2) Load register to Stack PUSH An, Am / PUSH An Description The PUSH instruction load one or two 22-bit data to software stack from extended registers. In the instruction of "PUSH An, Am", there are some restrictions on An and Am. An and Am should not be A15. If An is the same as Am, push operation occurs only once. "PUSH An, An" is equivalent to "PUSH An". 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 0 1 Am // PUSH An 1 1 1 1 1 An Operation if(An == Am) { DM[SP] := Rn DM[SP - 2] := {10'h000, En} SP := SP - 4 } else { DM[SP] := Rn DM[SP - 2] := {10'h000, En} DM[SP - 4] := Rm DM[SP - 6] := {10'h000, Em} SP := SP - 8 } Exceptions Notes None. None. MCU Team LSI Division System LSI Business - 90 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual RETD Ret. from Subroutine with Delay Slot RETD Description The RETD (Return from Subroutine with Delay Slot) instruction is used to finish a subroutine and return by jumping to the address specified by the link register or A14. The difference between RETD and JMP A14 is that RETD has a delay slot, which allows efficient implementation of small subroutines. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 1 1 1 1 0 1 0 0 1 1 1 1 1 Operation Exceptions Notes PC := A14 None. None. MCU Team LSI Division System LSI Business - 91 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual RET_FIQ Return from Fast Interrupt RET_FIQ Description The RET_FIQ (Return from Fast Interrupt) instruction is used to finish a FIQ handler and resume the normal program execution. When this instruction is executed, SSR_FIQ (saved SR) is restored into SR, and the program control transfers to (SPCH_FIQ:SPCL_FIQ). 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 1 1 1 1 0 1 0 0 1 1 1 0 0 Operation Exceptions Notes SR := SSR_FIQ PC := (SPCH_FIQ:SPCL_FIQ) None. Fast Interrupt is requested through the core signal nFIQ. When the request is acknowledged, SR and current PC are saved in the designated registers (namely SSR_FIQ and SPCH_FIQ:SPCL_FIQ) assigned for FIQ processing. Such bits in SR as FE, IE, and TE are cleared, and PM is set. MCU Team LSI Division System LSI Business - 92 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual RET_IRQ Return from Interrupt RET_IRQ Description The RET_IRQ (Return from Interrupt) instruction is used to finish an IRQ handler and resume the normal program execution. When this instruction is executed, SSR_IRQ (saved SR) is restored into SR, and the program control transfers to (SPCH_IRQ:SPCL_IRQ). 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 1 1 1 1 0 1 0 0 1 1 1 0 1 Operation Exceptions Notes SR := SSR_IRQ PC := (SPCH_IRQ:SPCL_IRQ) None. Interrupt is requested through the core signals nIRQ. When the request is acknowledged, SR and current PC are saved in the designated registers (namely SSR_IRQ and SPCH_FIQ:SPCL_IRQ) assigned for IRQ processing. Such bits in SR as IE and TE are cleared, and PM is set. MCU Team LSI Division System LSI Business - 93 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual RET_SWI Return from Software Interrupt RET_SWI Description The RET_SWI (Return from Software Interrupt) instruction is used to finish a SWI handler and resume the normal program execution. When this instruction is executed, SSR_FIQ (saved SR) is restored into SR, and the program control transfers to the address A14 (link register). 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 1 1 1 1 0 1 0 0 1 1 1 1 0 Operation Exceptions Notes SR := SSR_SWI PC := A14 None. Software interrupt is initiated by executing a SWI instruction from applications. When SWI instruction is executed, SR and current PC are saved in the designated registers (namely SSR_SWI and A14) assigned for SWI processing. MCU Team LSI Division System LSI Business - 94 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual RL Rotate Left RL Rn Description The RL (Rotate Left) instruction rotates the value of Rn left by one bit and stores the result back in Rn. T bit is updated as a result of this operation. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 0 0 0 1 1 1 1 0 Rn Operation Exceptions Notes Rn := Rn << 1, Rn[0] = MSB of Rn before rotation T bit := MSB of Rn before rotation None. None. MCU Team LSI Division System LSI Business - 95 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual RR Rotate Right RR Rn Description The RR (Rotate Right) instruction rotates the value of Rn right by one bit and stores the result back in Rn. T bit is updated as a result of this operation. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 0 0 0 0 1 1 1 0 Rn Operation Exceptions Notes Rn := Rn >> 1, MSB of Rn = Rn[0] before rotation T bit := Rn[0] before rotation None. None. MCU Team LSI Division System LSI Business - 96 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual RRC Rotate Right with Carry RRC Rn Description The RRC (Rotate Right with Carry) instruction rotates the value of (Rn:T bit) right by one bit and stores the result back in Rn. T bit is updated as a result of this operation. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 0 0 1 0 1 1 1 0 Rn Operation Exceptions Notes Rn := Rn >> 1, MSB of Rn = T bit before rotation T bit := Rn[0] before rotation None. None. MCU Team LSI Division System LSI Business - 97 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual SBC (1) Subtract with Carry Register SBC Rn, Ri Description The SBC (Subtract with Carry) instruction is used to synthesize 32-bit subtraction. If register pairs R0, R1 and R2, R3 hold 32-bit values (R0 and R2 hold the leastsignificant word), the following instructions leave the 32-bit result in R0, R1: SUB R0, R2 SBC R1, R3 SBC subtracts the value of register Ri, and the value of the Carry flag (stored in the T bit), from the value of register Rn, and stores the result in register Rn. The T bit and the V flag are updated based on the result. 15 14 13 12 11 8 7 6 5 4 3 0 1 0 0 0 Rn 0 0 1 1 Ri Operation Rn := Rn + ~Ri + T bit T bit := Carry from (Rn + ~Ri + T bit) V flag := Overflow from (Rn + ~Ri + T bit) if(Rn == R6/R7) Z0/Z1 := ((Rn + ~Ri + T) == 0) Exceptions Notes None. None. MCU Team LSI Division System LSI Business - 98 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual SBC (2) Subtract with Carry Immediate SBC Rn, # Description The SBC (Subtract with Carry immediate) instruction is used to synthesize 32-bit subtraction with an immediate operand. If register pair R0, R1 holds a 32-bit value (R0 holds the least-significant word), the following instructions leave the 32-bit subtraction result with 34157856h in R0, R1: SUB R0, #7856h SBC R1, #3415h SBC subtracts the value of 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 0 0 1 1 1 1 1 1 Rn Operation Rn := Rn + ~ Exceptions Notes None. This is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. Unlike 1-word instructions, therefore, fetching of this instruction takes 2 cycles. MCU Team LSI Division System LSI Business - 99 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual SETSR Set SR SETSR bs:3 Description The SETSR (Set SR) instruction is used to set a specified bit in SR as follows: SETSR FE / IE / TE / V / Z0 / Z1 / PM To set the T bit, one can do as follows: CMP EQ, R0, R0 To clear a specified bit in SR, the CLRSR instruction (in page 45) is used. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 1 0 0 1 1 1 1 0 1 0 0 0 1 Operation Exceptions Notes SR[ MCU Team LSI Division System LSI Business - 100 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual SR Shift Right SR Rn Description The SR (Shift Right) instruction shifts the value of Rn right by one bit and stores the result back in Rn. T bit is updated as a result of this operation. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 0 1 0 0 1 1 1 0 Rn Operation Exceptions Notes Rn := Rn >> 1, with Rn[15] set to 0 T bit := Rn[0] before shifting None. None. MCU Team LSI Division System LSI Business - 101 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual SRA Shift Right Arithmetic SRA Rn Description The SRA (Shift Right Arithmetic) instruction shifts the value of Rn right by one bit and stores the result back in Rn. While doing so, the original sign bit (most significant bit) is copied to the most significant bit of the result. T bit is updated as a result of this operation. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 0 1 0 1 1 1 1 0 Rn Operation Rn := Rn >> 1, with Rn[15] set to the original value T bit := Rn[0] before shifting Exceptions Notes None. None. MCU Team LSI Division System LSI Business - 102 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual SRB Shift Right Byte SRB Rn Description The SRB (Shift Right Byte) instruction shifts the value of Rn right by 8 bit and stores the result back in Rn. The high 8 bit positions are filled with 0's. T bit is updated as a result of this operation. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 0 0 1 1 1 1 1 0 Rn Operation Rn[7:0] := Rn[15:8] and Rn[15:8] := 8'h00 T bit := Rn[7] before shifting Exceptions Notes None. None. MCU Team LSI Division System LSI Business - 103 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual SUB (1) Subtract Register SUB Rn, Ri Description The SUB (Subtract Register) instruction is used to subtract a 16-bit register value from another 16-bit register value. 32-bit subtraction can be achieved by executing SBC instruction in pair with this instruction (see page 98). SUB subtracts the value of register Ri from the value of Rn, and stores the result in register Rn. The T bit and the V flag are updated based on the result. 15 14 13 12 11 8 7 6 5 4 3 0 1 0 0 0 Rn := Rn - Ri Rn 0 0 0 1 Ri Operation T bit := Carry from (Rn - Ri) V flag := Overflow from (Rn - Ri) if(Rn == R6/R7) Z0/Z1 := ((Rn - Ri) == 0) Exceptions Notes None. None. MCU Team LSI Division System LSI Business - 104 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual SUB (2) Subtract Small Immediate SUB Rn, # Description This form of SUB instruction is used to subtract a 7-bit immediate value from a register It subtracts the value of 15 14 13 12 11 8 7 6 0 0 0 0 0 Rn 1 Operation Rn := Rn - Exceptions Notes None. MCU Team LSI Division System LSI Business - 105 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual SUB (3) Subtract Extended Register SUB An, Ri Description This form of SUB instruction (Subtract Extended Register) is used to add a 16-bit unsigned register value from a 22-bit value in register. This instruction subtracts the value of 16-bit register Ri from the value of 22-bit register An, and stores the result in register An. 15 14 13 12 11 10 8 7 6 5 4 3 0 1 0 1 0 1 An 1 1 0 0 Ri Operation Exceptions Notes An := An - Ri None. None. MCU Team LSI Division System LSI Business - 106 - April 2000 Excellence in Low-Power The way MCU/DSP should be CalmRISC16 Reference Manual SUB (4) Subtract Large Immediate SUB An, # |