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FEATURES Complete Receiver on a Chip: MonoceiverTM Mixer -15 dBm 1 dB Compression Point -8 dBm Input Third Order Intercept 500 MHz RF and LO Bandwidths Linear IF Amplifier Linear-in-dB Gain Control MGC or AGC with RSSI Output Quadrature Demodulator On-Board Phase-Locked Quadrature Oscillator Demodulates IFs from 400 kHz to 12 MHz Can Also Demodulate AM, CW, SSB Low Power 25 mW at 3 V CMOS Compatible Power-Down Interfaces to AD7013 and AD7015 Baseband Converters APPLICATIONS GSM, CDMA, TDMA, and TETRA Receivers Satellite Terminals Battery-Powered Communications Receivers
Low Power Mixer/AGC/RSSI 3 V Receiver IF Subsystem AD607
PIN CONFIGURATION 20-Lead SSOP (RS Suffix)
FDIN 1 COM1 2 PRUP 3 LOIP 4 RFLO 5
20 VPS1 19 FLTR 18 IOUT 17 QOUT
AD607
16 VPS2
TOP VIEW RFHI 6 (Not to Scale) 15 DMIP GREF 7 MXOP 8 VMID 9 IFHI 10 14 IFOP 13 COM2 12 GAIN/RS 11 IFLO
GENERAL DESCRIPTION
The AD607 is a 3 V low power receiver IF subsystem for operation at input frequencies as high as 500 MHz and IFs from 400 kHz to 12 MHz. It consists of a mixer, IF amplifiers, I and Q demodulators, a phase-locked quadrature oscillator, AGC detector, and a biasing system with external power-down. The AD607's low noise, high intercept mixer is a doublybalanced Gilbert cell type. It has a nominal -15 dBm input referred 1 dB compression point and a -8 dBm input referred third-order intercept. The mixer section of the AD607 also includes a local oscillator (LO) preamplifier, which lowers the required LO drive to -16 dBm. The gain control input can serve as either a manual gain control (MGC) input or an automatic gain control (AGC) voltagebased RSSI output. In MGC operation, the AD607 accepts an external gain-control voltage input from an external AGC detector or a DAC. In AGC operation, an onboard detector and an external averaging capacitor form an AGC loop that holds the IF output level at 300 mV. The voltage across this capacitor then provides an RSSI output.
The I and Q demodulators provide inphase and quadrature baseband outputs to interface with Analog Devices' AD7013 (IS54, TETRA, MSAT) and AD7015 (GSM) baseband converters. A quadrature VCO phase-locked to the IF drives the I and Q demodulators. The I and Q demodulators can also demodulate AM; when the AD607's quadrature VCO is phase locked to the received signal, the in-phase demodulator becomes a synchronous product detector for AM. The VCO can also be phase-locked to an external beat-frequency oscillator (BFO), and the demodulator serves as a product detector for CW or SSB reception. Finally, the AD607 can be used to demodulate BPSK using an external Costas Loop for carrier recovery.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. (c) Analog Devices, Inc., 1995 One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD607-SPECIFICATIONS
Model DYNAMIC PERFORMANCE MIXER Maximum RF and LO Frequency Range Maximum Mixer Input Voltage Input 1 dB Compression Point Input Third-Order Intercept Noise Figure Maximum Output Voltage at MXOP Mixer Output Bandwidth at MXOP LO Drive Level LO Input Impedance Isolation, RF to IF Isolation, LO to IF Isolation, LO to RF Isolation, IF to RF IF AMPLIFIERS Noise Figure Input 1 dB Compression Point Output Third-Order Intercept Maximum IF Output Voltage at IFOP Output Resistance at IFOP Bandwidth GAIN CONTROL Gain Control Range Gain Scaling Gain Scaling Accuracy Bias Current at GAIN/RSSI Bias Current at GREF Input Resistance at GAIN, GREF I AND Q DEMODULATORS Required DC Bias at DMIP Input Resistance at DMIP Input Bias Current at DMIP Maximum Input Voltage Amplitude Balance Quadrature Error Phase Noise in Degrees Demodulation Gain Maximum Output Voltage Output Offset Voltage Output Bandwidth PLL Required DC Bias at FDIN Input Resistance at FDIN Input Bias Current at FDIN Frequency Range Required Input Drive Level Acquisition Time to 3 POWER-DOWN INTERFACE Logical Threshold Input Current for Logical High Turn-On Response Time Standby Current POWER SUPPLY Supply Range Supply Current OPERATING TEMPERATURE TMIN to TMAX
Specifications subject to change without notice.
(@ TA = + 25C, Supply = 3.0 V, IF = 10.7 MHz, unless otherwise noted)
Min AD607ARS Typ Max Units
Conditions
For Conversion Gain > 20 dB For Linear Operation; Between RFHI and RFLO RF Input Terminated in 50 RF Input Terminated in 50 Matched Input, Max Gain, f = 83 MHz, IF = 10.7 MHz Matched Input, Max Gain, f = 144 MHz, IF = 10.7 MHz ZIF = 165 , at Input Compression -3 dB, ZIF = 165 Mixer LO Input Terminated in 50 LOIP to VMID RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz Max Gain, f = 10.7 MHz IF = 10.7 MHz IF = 10.7 MHz ZIF = 600 From IFOP to VMID -3 dB at IFOP, Max Gain (See Figures 43 and 44) Mixer + IF Section, GREF to 1.5 V GREF to 1.5 V GREF to General Reference Voltage VR GREF to 1.5 V, 80 dB Span
500 54 -15 -5 14 12 1.3 45 -16 1 30 20 40 70 17 -15 +18 560 15 45 90 20 75/VR 1 5 1 1 VPOS/2 50 2 150 75 0.2 -1.2 -100 18 1.23 10 1.5 VPOS/2 50 200 0.4 to 12 400 16.5 2 75 16.5 550 2.7 5.5 8.5 -25 -40 +85 +85
MHz mV dBm dBm dB dB V MHz dBm k dB dB dB dB dB dBm dBm mV MHz dB mV/dB dB/V dB A A M V dc k A mV mV dB Degrees dBc/Hz dB V mV MHz V dc k nA MHz mV s V dc A s A V mA C C
From DMIP to VMID IF > 3 MHz IF 3 MHz IF = 10.7 MHz, Outputs at 600 mV p-p, F = 100 kHz IF = 10.7 MHz, Outputs at 600 mV p-p, F = 100 kHz IF = 10.7 MHz, F = 10 kHz Sine Wave Input, Baseband Output RL 20 k Measured from IOUT, QOUT to VMID Sine Wave Input, Baseband Output
From FDIN to VMID
Sine Wave Input at Pin 1 IF = 10.7 MHz For Power Up on Logical High To PLL Locked
Midgain, IF = 10.7 MHz Operation to 2.7 V Minimum Supply Voltage Operation to 4.5 V Minimum Supply Voltage
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AD607
ABSOLUTE MAXIMUM RATINGS 1 ORDERING GUIDE
Supply Voltage VPS1, VPS2 to COM1, COM2 . . . . . . . +5.5 V Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 600 mW 2.7 V to 5.5 V Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 25C to +85C 4.5 V to 5.5 V Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300C
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Thermal Characteristics: 20-lead SSOP Package: JA = 126C/W.
Model AD607ARS
Temperature Range - 25C to +85C for 2.7 V to 5.5 V Operation; -40C to +85C for 4.5 V to 5.5 V Operation
Package Description 20-Pin Plastic SSOP
Package Option RS-20
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD607 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD607
PIN DESCRIPTION
Pin 1 2 3 4 5 6 7 8 9 10 11 12
Mnemonic FDIN COM1 PRUP LOIP RFLO RFHI GREF MXOP VMID IFHI IFLO GAIN/RSSI
Reads Frequency Detector Input Common #1 Power-Up Input Local Oscillator Input RF "Low" Input RF "High" Input Gain Reference Input Mixer Output Midsupply Bias Voltage IF "High" Input IF "Low" Voltage Gain Control Input/RSSI Output
Function PLL input for I/Q demodulator quadrature oscillator, 400 mV drive required from external oscillator. Must be biased at VP/2. Supply common for RF front end and main bias. 3 V/5 V CMOS compatible power-up control; logical high = powered-up; max input level = VPS1 = VPS2. LO input, ac coupled 54 mV LO input required (-16 dBm for 50 input termination). Usually connected to ac ground. AC coupled, 56 mV, max RF input for linear operation. High impedance input, typically 1.5 V, sets gain scaling. High impedance, single-sided current output, 1.3 V max voltage output ( 6 mA max current output). Output of the midsupply bias generator (VMID = VPOS/2). AC coupled IF input, 56 mV max input for linear operation. Reference node for IF input; auto-offset null. High impedance input, 0 V-2 V using 3 V supply, max gain at V = 0. RSSI Output when using Internal AGC Detector; RSSI voltage is across AGC Capacitor connected to this pin. Supply common for IF stages and demodulator. Low impedance, single-sided voltage output, +5 dBm ( 560 mV) max. Signal input to I and Q demodulators 150 mV max input at IF > 3 MHz for linear operation; 75 mV max input at IF < 3 MHz for linear operation. Must be biased at VP/2. Supply to high-level IF, PLL, and demodulators. Low impedance Q baseband output 1.23 V full scale in 20 k min load; ac coupled. Low impedance I baseband output; 1.23 V full scale in 20 k min load; ac coupled. Series RC PLL Loop filter, connected to ground. Supply to mixer, low level IF, PLL, and gain control.
13 14 15
COM2 IFOP DMIP
Common #2 IF Output Demodulator Input
16 17 18 19 20
VPS2 QOUT IOUT FLTR VPS1
VPOS Supply #2 Quadrature Output In-Phase Output PLL Loop Filter VPOS Supply #1
PIN CONNECTION 20-Pin SSOP (RS-20)
FDIN 1 COM1 2 PRUP 3 LOIP 4 RFLO 5
20 VPS1 19 FLTR 18 IOUT 17 QOUT
AD607
16 VPS2
TOP VIEW RFHI 6 (Not to Scale) 15 DMIP GREF 7 MXOP 8 VMID 9 14 IFOP 13 COM2 12 GAIN/RS 11 IFLO
IFHI 10
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Typical Performance Characteristics-AD607
50 HP8656B IEEE RF_OUT HP8764B 0 1 0 50 1
SYNTHESIZER HP8656B IEEE RF_OUT
S0 S1 V
CHARACTERIZATION BOARD
50
HP8764B 0 1 0
SYNTHESIZER RFHI R HP8656B IEEE RF_OUT LOIP L MXOP X 50
S0 S1
1
V
SYNTHESIZER HP6633A VPOS IEEE VNEG SPOS SNEG DCPS HP34401A HI CPIB DMM DP8200 VPOS IEEE VNEG SPOS SNEG VREF 0 1 S0 V S1 1k HP8765B C LO I R5 PRUP GAIN VPOS BIAS DMIP FDIN PLL QOUT IOUT IN2 OUT2 PROBE SUPPLY IFHI IFOP X10 FET P6205 OUT IN1 PROBE TEK1105 OUT1 0 1 S0 V S1 HP8765B C HP8594E RF_IN IEEE SPEC AN
Figure 1. Mixer/Amplifier Test Set
HP8720C PORT_1 IEEE_488 PORT_2
NETWORK AN 0 NOISE 1 S0 V S1 HP8765B C
CHARACTERIZATION BOARD
HP8765B RFHI R L MXOP X C S1 V S0 0 1 50 HP8970A RF_IN 28V_OUT
HP346B 28V
NOISE SOURCE HP8656B IEEE RF_OUT
NOISE FIGURE METER
SYNTHESIZER
LOIP
IFHI
IFOP
DMIP FDIN PLL
IOUT
QOUT HP6633A VPOS IEEE VNEG SPOS SNEG DCPS DP8200 VPOS IEEE VREF VNEG SPOS SNEG PRUP GAIN VPOS BIAS
Figure 2. Mixer Noise Figure Test Set
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AD607
CHARACTERIZATION BOARD
MXOP R L LOIP HP346B 28V NOISE IFHI IFOP X10 FET P6205 OUT IN1 PROBE IN2 DMIP FDIN PLL QOUT HP6633A VPOS IEEE VNEG SPOS SNEG DCPS DP8200 VPOS
IEEE
RFHI
X
TEK1103 OUT1
HP8970A RF_IN 28V_OUT
NOISE SOURCE OUT2 PROBE SUPPLY IOUT
NOISE FIGURE METER
VPOS BIAS PRUP GAIN
VNEG SPOS VREF SNEG
Figure 3. IF Amp Noise Figure Test Set
CHARACTERIZATION BOARD
50 HP8656B IEEE RF_OUT
HP8764B 0 1 0 RFHI R L LOIP S0 S1 IFHI IFOP MXOP X
SYNTHESIZER 50
1
V
HP3326A DCFM IEEE OUTPUT_1 OUTPUT_2 FDIN DUAL SYNTHESIZER PLL QOUT HP6633A VPOS IEEE VNEG SPOS SNEG DCPS DP8200 VPOS IEEE VNEG SPOS VREF SNEG PRUP GAIN CH1 CH2 CH3 CH4 TRIG IEEE_488 DIGITAL OSCILLOSCOPE X10 VPOS BIAS DMIP IOUT P6205 X10 OUT IN1 FET PROBE P6205 OUT IN2 OUT2 1 S0 V S1 C C S1 V S0 HP54120 1 1103 OUT1 0 HP8765B HP8765B 0 HP8694E RF_IN IEEE SPEC AN
FET PROBE
PROBE SUPPLY
Figure 4. PLL/Demodulator Test Set
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AD607
CHARACTERIZATION BOARD
RFHI R LOIP HP6633A VPOS IEEE VNEG SPOS SNEG DCPS DP8200 VPOS IEEE VNEG SPOS SNEG VREF HP34401A HI GPIB DMM LO I
R1 499k
MXOP X L
IFHI
IFOP
DMIP FDIN PLL
IOUT
QOUT
VPOS BIAS PRUP GAIN
Figure 5. GAIN Pin Bias Test Set
CHARACTERIZATION BOARD
RFHI R LOIP HP6633A VPOS IEEE VNEG SPOS SNEG DCPS DP8200 VPOS IEEE VNEG SPOS SNEG VREF HP34401A HI GPIB DMM LO I
R1 499k
MXOP X L
IFHI
IFOP
DMIP FDIN PLL
IOUT
QOUT
VPOS BIAS PRUP GAIN
Figure 6. Demodulator Bias Test Set
CHARACTERIZATION BOARD
HP3325B IEEE RF_OUT RFHI R L LOIP VPOS IEEE VNEG SPOS SNEG DCPS HP6633A VPOS IEEE VNEG SPOS SNEG DCPS HP34401A HI GPIB DMM LO I GAIN
R1 10k
MXOP X
SYNTHESIZER HP6633A
HP8594E IFHI IFOP RF_IN SPEC AN IEEE
DMIP FDIN PLL
IOUT
QOUT
VPOS BIAS PRUP
Figure 7. Power-Up Threshold Test Set
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AD607
CHARACTERIZATION BOARD
RFHI R L LOIP
MXOP X
IFHI
IFOP
X10
50
P6205 OUT IN1 FET PROBE P6205
1103 OUT1 CH1 CH2 CH3 CH4 TRIG
HP54120
X10 FL6082A RF_OUT IEEE MOD_OUT HP6633A VPOS IEEE VNEG SPOS SNEG DCPS DP8200 VPOS IEEE VNEG SPOS SNEG VREF HP8112 IEEE PULSE_OUT PRUP GAIN DMIP FDIN PLL QOUT VPOS BIAS IOUT
OUT IN2 OUT2 FET PROBE PROBE SUPPLY
IEEE_488 DIGITAL OSCILLOSCOPE
NOTE: MUST BE 3 RESISTOR POWER DIVIDER
PULSE GENERATOR
Figure 8. Power-Up Test Set
CHARACTERIZATION BOARD
RFHI R L LOIP HP8656B IEEE RF_OUT
MXOP X
IFHI
IFOP
R1 1k
P6205 X10 OUT IN1 FET PROBE IN2
1103 OUT1 RF_IN
HP8594E IEEE
SYNTHESIZER
SPEC AN OUT2
DMIP FDIN PLL
IOUT
PROBE SUPPLY
QOUT HP6633A VPOS IEEE VNEG SPOS SNEG DCPS PRUP GAIN VPOS BIAS
Figure 9. IF Output Impedance Test Set
CHARACTERIZATION BOARD
RFHI R L LOIP
MXOP X
IFHI 20 dB
IFOP
HP54120 FL6082A IEEE RF_OUT MOD_OUT HP6633A VPOS IEEE VNEG SPOS SNEG DCPS DP8200 VPOS IEEE VNEG SPOS VREF SNEG PRUP GAIN DMIP FDIN PLL QOUT X10 VPOS BIAS P6205 IOUT X10 OUT IN1 1103 OUT1 CH1 CH2 CH3 OUT IN2 OUT2 CH4 TRIG IEEE_488 DIGITAL OSCILLOSCOPE
FET PROBE P6205
FET PROBE
PROBE SUPPLY
Figure 10. PLL Settling Time Test Set
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AD607
CHARACTERIZATION BOARD
RFHI R HP3325B IEEE RF_OUT IFHI L LOIP
MXOP X
SYNTHESIZER
IFOP
HP3326 DCFM IEEE OUTPUT_1 OUTPUT_2 FDIN DUAL SYNTHESIZER PLL QOUT HP6633A VPOS IEEE VNEG SPOS SNEG DCPS DP8200 VPOS IEEE VNEG SPOS VREF SNEG PRUP GAIN X10 VPOS BIAS DMIP IOUT P6205 X10 OUT IN1 FET PROBE P6205 OUT IN2 OUT2 1 S0 V S1 C 1103 OUT1 0 HP8765B HP8694E RF_IN IEEE SPEC AN
FET PROBE
PROBE SUPPLY
Figure 11. Quadrature Accuracy Test Set
VPOS GND C15 0.1F C11 10nF FDIN R8 51.1 0 R12 PRUP R7 51.1 C9 1nF RFHI R6 51.1 R13 301 R14 54.9 332 R5 51.1 R9 C7 1nF C10 1nF C16 1nF 0.1F C13 1 FDIN 2 COM1 3 PRUP 4 LOIP 5 RFLO 6 RFHI 7 GREF 8 MXOP 9 VMID 10 IFHI VPS1 20 FLTR 19 IOUT 18 QOUT 17 R1 1k 0.1F C2 4.99k R10 0.1F C1
C3 10nF IOUT * QOUT *
LOIP
AD607
VPS2 16 DMIP 15 IFOP 14 COM2 13 GAIN 12 IFLO 11
R2 316
IFOP * C5 1nF GAIN * DMIP *
MXOP *
C6 0.1F C8 0.1F
IFHI
0.1F NOTE: CONNECTIONS MARKED * ARE DC COUPLED.
Figure 12. AD607 Characterization Board
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AD607
20 19 18 17 30 25 VGAIN = 0.3V
CONVERSION GAIN - dB
20 VGAIN = 0.6V 15 10 5 0 -5 VGAIN = 1.2V VGAIN = 1.8V VGAIN = 2.4V
SSB NF - dB
16 15
VPOS = 5V, IF = 20 MHz VPOS = 3V, IF = 20 MHz
14 13 12 11 10 50 VPOS = 5V, IF = 10 MHz 70 90 110 130 150 VPOS = 3V, IF = 10 MHz
-10 170 190 210 230 250 0.1 1 10 100 RF FREQUENCY - MHz INTERMEDIATE FREQUENCY - MHz
Figure 13. Mixer Noise Figure vs. Frequency
Figure 16. Mixer Conversion Gain vs. IF, T = +25C, VPOS = 3 V, VREF = 1.5 V
4500 4000 3500 C SHUNT COMPONENT
RESISTANCE -
4.0
80
3.5
70
3.0 2.5 2.0
CAPACITANCE - pF
CUBIC FIT OF IF_GAIN (TEMP) 60 50 IF AMP GAIN
3000 2500 2000
GAIN - dB
40 30 20 10 0 -10 -20
-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130
1.5 1500 R SHUNT COMPONENT 1000 500 0 0 50 100 150 200 250 300 350 400 450 FREQUENCY - MHz 1.0 0.5 0 500
CUBIC FIT OF CONV_GAIN (TEMP) MIXER CG
TEMPERATURE - C
Figure 14. Mixer Input Impedance vs. Frequency, VPOS = 3 V, V GAIN = 0.8 V
Figure 17. Mixer Conversion Gain and IF Amplifier Gain vs. Temperature, VPOS = 3 V, VGAIN = 0.3 V, VREF = 1.5 V, IF = 10.7 MHz, RF = 250 MHz
30 25 20
CONVERSION GAIN - dB
VGAIN = 0.00V VGAIN = 0.54V
80 70
15 10
GAIN - dB
CUBIC FIT OF IF_GAIN (VPOS) IF AMP GAIN
60
5 0 -5 -10 -15 -20
VGAIN = 1.62V
VGAIN = 1.08V
50
40 30 CUBIC FIT OF CONV_GAIN (VPOS)
VGAIN = 2.16V
20
0
50
100 150 200 250 300 350 400 450 500 550 600 RADIO FREQUENCY - MHz
10
MIXER CG
2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6
SUPPLY - Volts
Figure 15. Mixer Conversion Gain vs. Frequency, T = +25C, VPOS = 2.7 V, VREF = 1.35 V, IF = 10.7 MHz
Figure 18. Mixer Conversion Gain and IF Amplifier Gain vs. Supply Voltage, T = +25C, VGAIN = 0.3 V, VREF = 1.5 V, IF = 10.7 MHz, RF = 250 MHz
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AD607
80 70 60 VGAIN = 0.3V
-100.00 -90.00
IF AMPLIFIER GAIN - dB
VGAIN = 0.6V
PHASE NOISE - dBc
-110.00
50 40 30 20 10 VGAIN = 2.4V 0 -10 0.1 1 10 100 INTERMEDIATE FREQUENCY - MHz VGAIN = 1.8V VGAIN = 1.2V
-120.00
-130.00
-140.00
-150.00
1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07
CARRIER FREQUENCY OFFSET, f(fm) - Hz
Figure 19. IF Amplifier Gain vs. Frequency, T = +25C, VPOS = 3 V, VREF = 1.5 V
Figure 22. PLL Phase Noise L (F) vs. Frequency, VPOS = 3 V, C3 = 0.1 F, IF = 10.7 MHz
10 8 6 4
FLTR PIN VOLTAGE - Volts
2.5
IF AMP
ERROR - dB
2 0 -2 -4 -6 -8 -10 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 GAIN VOLTAGE - Volts MIXER
2
1.5 0.1 1 10 100 PLL FREQUENCY - MHz
Figure 20. AD607 Gain Error vs. Gain Control Voltage, Representative Part
Figure 23. PLL Loop Voltage at FLTR (KVCO) vs. Frequency
8 7 6 5
COUNT
4 3
996.200 s Timebase Memory 1 Timebase Memory 2 Timebase Delta T Start = = = = = = =
1.00870 ms
1.02120 ms Delay = Offset = Delay = Offset = Delay = 1.00870 ms 127.3 mVolts 1.00870 ms 155.2 mVolts 1.00870 ms
2 1 0 85 86 87 88 89 90 91 92 93 94 95 QUADRATURE ANGLE - Degrees
2.5 s/div 100.0 mVolts/div 2.50 s/div 20.00 mVolts/div 2.50 s/div 16.5199 s 1.00048 ms
Stop = 1.01700 ms
Trigger on External at Pos. Edge at 134.0 mVolts
Figure 21. PLL Acquisition Time
Figure 24. Demodulator Quadrature Angle, Histogram, T = +25C, VPOS = 3 V, IF = 10.7 MHz
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AD607
30
20 19 I_GAIN_CORR
25
18 17 CUBIC FIT OF I_GAIN_CORR (TEMP)
20
IGAIN - dB
16 15 14 13 12
COUNT
15
10
5
11
0 -2 -1 0 IQ GAIN BALANCE - dB 1 2
10 2.5 3 3.5 4 4.5 5 5.5 6 SUPPLY - Volts
Figure 25. Demodulator Gain Balance, Histogram, T = +25C, VPOS = 3 V, IF = 10.7 MHz
Figure 28. Demodulator Gain vs. Supply Voltage
40
20
35
19 18 17
30 25
IGAIN - dB
16 15 QUADRATIC FIT OF I_GAIN_CORR (IFF) 14 13 12 11 10 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 BASEBAND FREQUENCY - MHz
COUNT
I_GAIN_CORR
20 15 10 5 0 17 17.2 17.4 17.6 17.8 18 18.2 18.4 18.6 18.8 DEMODULATOR GAIN - dB
Figure 26. Demodulator Gain vs. Frequency
Figure 29. Demodulator Gain Histogram, T = +25C, VPOS = 3 V, IF = 10.7 MHz
20 19 18 17 I_GAIN_CORR
14
12 10
CUBIC FIT OF I_GAIN_CORR (TEMP)
IGAIN - dB
15 14 13 12
COUNT
16
8 6 4 2
11 10
-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130
0 -0.1 -0.08 -0.06 -0.04 -0.02
0
0.02 0.04
0.06
0.08
0.1
TEMPERATURE - C
OUTPUT OFFSET - Volts
Figure 27. Demodulator Gain vs. Temperature
Figure 30. Demodulator Output Offset Voltage Histogram, T = +25C, VPOS = 3 V, IF = 10.7 MHz
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AD607
PRODUCT OVERVIEW
40.2127 ms Timebase Memory 1 Timebase Memory 2 Timebase Delta T Start = = = = = = =
40.2377 ms
40.2627 ms 40.2377 ms 154.0 mVolts 40.2377 ms 209.0 mVolts 40.2377 ms
5.00 s/div 100.0 mVolts/div 5.00 s/div 60.00 mVolts/div 5.00 s/div 15.7990 s 40.2327 ms
Delay = Offset = Delay = Offset = Delay =
The AD607 provides most of the active circuitry required to realize a complete low power, single-conversion superheterodyne receiver, or most of a double-conversion receiver, at input frequencies up to 500 MHz, and with an IF of from 400 kHz to 12 MHz. The internal I/Q demodulators, and their associated phase locked-loop, which can provide carrier recovery from the IF, support a wide variety of modulation modes, including nPSK, n-QAM, and AM. A single positive supply voltage of 3 V is required (2.7 V minimum, 5.5 V maximum) at a typical supply current of 8.5 mA at midgain. In the following discussion, VP will be used to denote the power supply voltage, which will be assumed to be 3 V. Figure 33 shows the main sections of the AD607. It consists of a variable-gain UHF mixer and linear four-stage IF strip, which together provide a voltage controlled gain range of more than 90 dB; followed by dual demodulators, each comprising a multiplier followed by a 2-pole, 2 MHz low-pass filter; and driven by a phase-locked loop providing the inphase and quadrature clocks. An internal AGC detector is included, and the temperature stable gain control system provides an accurate RSSI capability. A biasing system with CMOS compatible power-down completes the AD607.
Mixer
Stop = 40.2485 ms
Trigger on External at Pos. Edge at 40.0 mVolts
Figure 31. Power-Up Response Time to PLL Stable
15
SUPPLY CURRENT - mA
10
5 0 0.5 1 1.5 2 2.5 GAIN VOLTAGE - Volts
The UHF mixer is an improved Gilbert cell design, and can operate from low frequencies (it is internally dc-coupled) up to an RF input of 500 MHz. The dynamic range at the input of the mixer is determined, at the upper end, by the maximum input signal level of 56 mV between RFHI and RFLO up to which the mixer remains linear, and, at the lower end, by the noise level. It is customary to define the linearity of a mixer in terms of the 1 dB gain-compression point and third-order intercept, which for the AD607 are -15 dBm and -8 dBm, respectively, in a 50 system.
Figure 32. Power Supply Current vs. Gain Control Voltage, GREF = 1.5 V
LOIP
RFHI MXOP BPF IFHI
VMID
IOUT FDIN VQFO FLTR
IFOP RFLO VMID MID-POINT BIAS GENERATOR IFLO AGC DETECTOR
BPF OR LPF
DMIP
QOUT
GAIN/RSSI VPS1 VPS2 PRUP COM1 COM2 BIAS GENERATOR PTAT VOLTAGE
GREF
AD607
Figure 33. Functional Block Diagram
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AD607
The mixer's RF input port is differential, that is, pin RFLO is functionally identical to RFHI, and these nodes are internally biased; we will generally assume that RFLO is decoupled to ac ground. The RF port can be modeled as a parallel RC circuit as shown in Figure 34.
AD607
C1 C2 RFHI CIN RFLO C3 RIN
Table I. AD607 Filter Termination Resistor Values for Common IFs
IF 450 kHz 455 kHz 6.5 MHz 10.7 MHz
Filter Impedance 1500 1500 1000 330
Filter Termination Resistor Values1 for 24 dB of Mixer Gain R1 174 174 215 330 R2 1330 1330 787 0 R3 1500 1500 1000 330
L1
NOTES 1 Resistor values were calculated such that R1+ R2 = Z FILTER and R1 (R2 + ZFILTER) = 165 .
C1, C2, L1: OPTIONAL MATCHING CIRCUIT C3: COUPLES RFLO TO AC GROUND
Figure 34. Mixer Port Modeled as a Parallel RC Network; an Optional Matching Network Is also Shown
The local oscillator (LO) input is internally biased at VP/2 via a nominal 1000 resistor internally connected from pin LOIP to VMID. The LO interface includes a preamplifier which minimizes the drive requirements, thus simplifying the oscillator design and reducing LO leakage from the RF port. Internally, this single-sided input is actually differential; the noninverting input is referenced to pin VMID. The LO requires a single-sided drive of 50 mV, or -16 dBm in a 50 system. The mixer's output passes through both a low-pass filter and a buffer, which provides an internal differential to single-ended signal conversion with a bandwidth of approximately 45 MHz. Its output at pin MXOP is in the form of a single-ended current. This approach eliminates the 6 dB voltage loss of the usual series termination by replacing it with shunt terminations at the both the input and the output of the filter. The nominal conversion gain is specified for operation into a total IF bandpass filter (BPF) load of 165 , that is, a 330 filter, doubly-terminated as shown in Figure 33. Note that these loads are connected to bias point VMID, which is always at the midpoint of the supply (that is, VP/2). The conversion gain is measured between the mixer input and the input of this filter, and varies between 1.5 dB and 26.5 dB for a 165 load impedance. Using filters of higher impedance, the conversion gain can always be maintained at its specified value or made even higher; for filters of lower impedance, of say ZO, the conversion gain will be lowered by 10 log10(165/ZO). Thus, the use of a 50 filter will result in a conversion gain that is 5.2 dB lower. Figure 35 shows filter matching networks and Table I lists resistor values.
The maximum permissible signal level at MXOP is determined by both voltage and current limitations. Using a 3 V supply and VMID at 1.5 V, the maximum swing is about 1.3 V. To attain a voltage swing of 1 V in the standard IF filter load of 165 load requires a peak drive current of about 6 mA, which is well within the linear capability of the mixer. However, these upper limits for voltage and current should not be confused with issues related to the mixer gain, already discussed. In an operational system, the AGC voltage will determine the mixer gain, and hence the signal level at the IF input pin IFHI; it will always be less than 56 mV (-15 dBm into 50 ), which is the limit of the IF amplifier's linear range.
IF Amplifier
Most of the gain in the AD607 arises in the IF amplifier strip, which comprises four stages. The first three are fully differential and each has a gain span of 25 dB for the nominal AGC voltage range. Thus, in conjunction with the mixer's variable gain, the total gain exceeds 90 dB. The final IF stage has a fixed gain of 20 dB, and it also provides differential to single-ended conversion. The IF input is differential, at IFHI (noninverting relative to the output IFOP) and IFLO (inverting). Figure 36 shows a simplified schematic of the IF interface. The offset voltage of this stage would cause a large dc output error at high gain, so it is nulled by a low-pass feedback path from the IF output, also shown in Figure 25. Unlike the mixer output, the signal at IFOP is a low-impedance single-sided voltage, centered at VP/2 by the DC feedback loop. It may be loaded by a resistance as low as 50 which will normally be connected to VMID.
AD607
IFHI 10k VMID
IFOP IFLO 10k
R2 MXOP 8 R1 VMID 9 100nF BPF
1nF 10 IFHI R3 11 IFLO 100nF
OFFSET FEEDBACK LOOP
Figure 36. Simplified Schematic of the IF Interface
Figure 35. Suggested IF Filter Matching Network. The Values of R1 and R2 Are Selected to Keep the Impedance at Pin MXOP at 165
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The IF's small-signal bandwidth is approximately 45 MHz from IFHI and IFLO through IFOP. The peak output at IFOP is 560 mV at VP = 3 V and 400 mV at the minimum VP of 2.7 V. This allows some headroom at the demodulator inputs (pin DMIP), which accept a maximum input of 150 mV for IFs > 3 MHz and 75 mV for IFs 3 MHz (at IFs 3 MHz, the drive to the demodulators must be reduced to avoid saturating the output amplifiers with higher order mixing products that are no longer removed by the onboard low-pass filters). If the internal AGC detector is used, the IF output will be at an amplitude of VP/10, that is, 300 mV for VP = 3 V. This 300 mV level requires the insertion of 6 dB of post-IF filter loss between IFOP and DMIP to avoid overloading the demodulators; often, a simple RC low-pass filter with its corner frequency at the IF will suffice. Since there is no band-limiting in the IF strip, the outputreferred noise can be quite high; in a typical application and at a gain of 75 dB it is about 100 mV rms, making post-IF filtering desirable. IFOP may be also used as an IF output for driving an A/D converter, external demodulator, or external AGC detector. Figure 37 shows methods of matching the optional second IF filter.
VPOS
The gain control scaling is proportional to the reference voltage applied to the pin GREF. When this pin is tied to the midpoint of the supply (VMID), the scale is nominally 20 mV/dB (50 dB/ V) for VP = 3 V. Under these conditions, the lower 80 dB of gain range (mixer plus IF) corresponds to a control voltage of 0.4 V VG 2.0 V. The final centering of this 1.6 V range depends on the insertion losses of the IF filters used. More generally, the gain scaling using these connections is VP/150 (volts per dB), so becomes 33.3 mV/dB (30 dB/V) using a 5 V supply, with a proportional change in the AGC range, to 0.33 V VG 3 V, Table II lists gain control voltages and scale factors for power supply voltages from 2.7 V to 5.5 V. Alternatively, pin GREF can be tied to an external voltage reference, VR, provided, for example, by an AD1582 (2.5 V) or AD1580 (1.21 V) voltage reference, to provide supplyindependent gain scaling of VR/75 (volts per dB). When using the Analog Devices' AD7013 and AD7015 baseband converters, the external reference may also be provided by the reference output of the baseband converter (Figure 38). For example, the AD7015 baseband converter provides a VR of 1.23 V; when connected to GREF the gain scaling is 16.4 mV/dB (60 dB/V). An auxiliary DAC in the AD7015 can be used to generate the MGC voltage. Since it uses the same reference voltage, the numerical input to this DAC provides an accurate RSSI value in digital form, no longer requiring the reference voltage to have high absolute accuracy.
AD607
R IOUT R QOUT C VMID IADC QADC GREF 10nF REFOUT (AD7015) BYPASS (AD7013) AUX DAC 1nF C QADC
AD607
RT IFOP BPF 2RT 2RT
AD7013 OR AD7015
IADC
DMIP
a. Biasing DMIP from Power Supply (Assumes BPF AC Coupled Internally)
AD607
IFOP
RT BPF
GAIN/RSSI
DMIP RT VMID CBYPASS
Figure 38. Interfacing the AD607 to the AD7013 or AD7015 Baseband Converters
I/Q Demodulators
b. Biasing DMIP from VMID (Assumes BPF AC Coupled Internally) Figure 37. Input and Output Matching of the Optional Second IF Filter
Gain Scaling and RSSI
The AD607's overall gain, expressed in decibels, is linear-in-dB with respect to the AGC voltage VG at pin GAIN/RSSI. The gain of all sections is maximum when VG is zero, and reduces progressively up to VG = 2.2 V (for VP = 3 V; in general, up to a limit VP - 0.8 V). The gain of all stages changes in parallel. The AD607 features temperature-compensation of the gain scaling. Note that GAIN/RSSI pin is either an MGC input, when the gain is controlled by some external means, or an RSSI output, when the internal AGC detector is used.
Both demodulators (I and Q) receive their inputs at pin DMIP. Internally, this single-sided input is actually differential; the noninverting input is referenced to pin VMID. Each demodulator comprises a full-wave synchronous detector followed by a 2 MHz, two-pole low-pass filter, producing single-sided outputs at pins IOUT and QOT. Using the I and Q demodulators for IFs above 12 MHz is precluded by the 400 kHz to 12 MHz response of the PLL used in the demodulator section. Pin DMIP requires an external bias source at VP/2; Figure 39 shows suggested methods. Outputs IOUT and QOUT are centered at VP/2 and can swing up to 1.23 V even at the low supply voltage of 2.7 V. They can therefore directly drive the RX ADCs in the AD7015 baseband converter, which require an amplitude of 1.23 V to fully load them when driven by a single-sided signal. The conversion gain of the I and Q demodulators is 18 dB (X8), requiring a maximum input amplitude at DMIP of 150 mV for IFs > 3 MHz.
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AD607
VPOS
AD607
RT IFOP BPF 2RT 2RT
quadrature accuracy of this VFQO is typically -1.2 at 10.7 MHz. The PLL uses a sequential-phase detector that comprises low power emitter-coupled logic and a charge pump (Figure 40).
DMIP
IU~ 40A VF I-CLOCK VARIABLEFREQUENCY QUADRATURE OSCILLATOR
a. Biasing DMIP from Power Supply (Assumes BPF AC Coupled Internally)
AD607
IFOP
F R
SEQUENTIAL PHASE DETECTOR
U D
90
C R
RT BPF
ID~ 40A REFERENCE CARRIER (FDIN AFTER LIMITING)
Q-CLOCK (ECL OUTPUTS)
DMIP RT DMIP CBYPASS
Figure 40. Simplified Schematic of the PLL and Quadrature VCO
b. Biasing DMIP from VMID (Assumes BPF AC Coupled Internally) Figure 39. Suggested Methods for Biasing Pin DMIP at VP/2
For IFs < 3 MHz, the on-chip low-pass filters (2 MHz cutoff) do not attenuate the IF or feedthrough products; thus, the maximum input voltage at DMIP must be limited to 75 mV to allow sufficient headroom at the I and Q outputs for not only the desired baseband signal but also the unattenuated higher-order demodulation products. These products can be removed by an external low-pass filter. In the case of IS54 applications using a 455 kHz IF and the AD7013 baseband converter, a simple 1-pole RC filter with its corner above the modulation bandwidth is sufficient to attenuate undesired outputs.
Phase-Locked Loop
The reference signal may be provided from an external source, in the form of a high-level clock, typically a low level signal ( 400 mV) since there is an input amplifier between FDIN and the loop's phase detector. For example, the IF output itself can be used by connecting DMIP to FDIN, which will then provide automatic carrier recover for synchronous AM detection and take advantage of any post-IF filtering. Pin FDIN must be biased at VP/2; Figure 41 shows suggested methods. The VFQO operates from 400 kHz to 12 MHz and is controlled by the voltage between VPOS and FLTR. In normal operation, a series RC network, forming the PLL loop filter, is connected from FLTR to ground. The use of an integral sample-hold system ensures that the frequency-control voltage on pin FLTR remains held during power-down, so reacquisition of the carrier typically occurs in 16.5 s. In practice, the probability of a phase mismatch at power-up is high, so the worst-case linear settling period to full lock needs to be considered in making filter choices. This is typically 16.5 s at an IF of 10.7 MHz for a 100 mV signal at DMIP and FDIN.
The demodulators are driven by quadrature signals that are provided by a variable frequency quadrature oscillator (VFQO), phase locked to a reference signal applied to pin FDIN. When this signal is at the IF, inphase and quadrature baseband outputs are generated at IOUT and QOUT, respectively. The
Table II. AD607 Gain and Manual Gain Control Voltage vs. Power Supply Voltage
Power Supply Voltage (V) 2.7 3.0 3.5 4.0 4.5 5.0 5.5
GREF (= VMID) (V) 1.35 1.5 1.75 2.0 2.25 2.5 2.75
Scale Factor (dB/V) 55.56 50.00 42.86 37.50 33.33 30.00 27.27
Scale Factor (mV/dB) 18.00 20.00 23.33 26.67 30.00 33.33 36.67
Gain Control Voltage Input Range (V) 0.360-1.800 0.400-2.000 0.467-2.333 0.533-2.667 0.600-3.000 0.667-3.333 0.733-3.667
NOTE Maximum gain occurs for gain control voltage = 0 V.
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Bias System USING THE AD607
The AD607 operates from a single supply, VP, usually of 3 V, at a typical supply current of 8.5 mA at midgain and T = 27C, corresponding to a power consumption of 25 mW. Any voltage from 2.7 V to 5.5 V may be used. The bias system includes a fast-acting active-high CMOScompatible power-up switch, allowing the part to idle at 550 A when disabled. Biasing is proportional-to-absolute-temperature (PTAT) to ensure stable gain with temperature. An independent regulator generates a voltage at the midpoint of the supply (VP/2) which appears at the VMID pin, at a low impedance. This voltage does not shut down, ensuring that the major signal interfaces (e.g., mixer-to-IF and IF-to-demodulators) remain biased at all times, thus minimizing transient disturbances at power-up and allowing the use of substantial decoupling capacitors on this node. The quiescent consumption of this regulator is included in the idling current.
VPOS 50k FDIN EXTERNAL FREQUENCY REFERENCE 50k
In this section, we will focus on a few areas of special importance and include a few general application tips. As is true of any wideband high gain component, great care is needed in PC board layout. The location of the particular grounding points must be considered with due regard to possibility of unwanted signal coupling, particularly from IFOP to RFHI or IFHI or both. The high sensitivity of the AD607 leads to the possibility that unwanted local EM signals may have an effect on the performance. During system development, carefully-shielded test assemblies should be used. The best solution is to use a fullyenclosed box enclosing all components, with the minimum number of needed signal connectors (RF, LO, I and Q outputs) in miniature coax form. The I and Q output leads can include small series resistors (about 100 ) inside the shielded box without significant loss of performance, provided the external loading during testing is light (that is, a resistive load of more than 20 k and capacitances of a few picofarads). These help to keep unwanted RF emanations out of the interior. The power supply should be connected via a through-hole capacitor with a ferrite bead on both inside and outside leads. Close to the IC pins, two capacitors of different value should be used to decouple the main supply (VP) and the midpoint supply pin, VMID. Guidance on these matters is also generally included in applications schematics.
Gain Distribution
AD607
a. Biasing FDIN from Supply when Using External Frequency Reference
AD607
FDIN EXTERNAL FREQUENCY REFERENCE 50k VMID CBYPASS
As in all receivers, the most critical decisions in effectively using the AD607 relate to the partitioning of gain between the various subsections (Mixer, IF Amplifier, Demodulators) and the placement of filters, so as to achieve the highest overall signal-tonoise ratio and lowest intermodulation distortion. Figure 42 shows the main RF/IF signal path at maximum and minimum signal levels.
b. Biasing FDIN from VMID when Using External Frequency Reference Figure 41. Suggested Methods for Biasing Pin FDIN at VP/2
I 54mV MAX INPUT RFHI 1.3V MAX OUTPUT MXOP 54mV MAX INPUT IFHI 560mV MAX OUTPUT IFOP 154mV MAX INPUT DMIP QOUT 1.23V MAX OUTPUT IOUT
IF BPF
IF BPF
LOIP CONSTANT -16dBm (50mV)
330
330
(VMID)
Q
(TYPICAL IMPEDANCE)
(LOCATION OF OPTIONAL SECOND IF FILTER)
Figure 42. Signal Levels for Minimum and Maximum Gain
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As noted earlier, the gain in dB is reduced linearly with the voltage VG on the GAIN pin. Figure 43 shows how the mixer and IF strip gains vary with VG when GREF is connected to VMID (1.5 V) and a supply voltage of 3 V is used. Figure 44 shows how these vary when GREF is connected to a 1.23 V reference.
90dB 80dB 70dB 60dB 50dB 40dB (67.5dB)
1.5V
30A
4.5A
77A LAST IF STAGE IFOP Q1 Q2 IC2
ZERO
1.5V + 316mV
GAIN
TO INTERNAL GAIN CONTROL
IF OUTPUT
CAGC (EXT) 4.5A (INT) COMM
IF GAIN
AVERAGE OF IC2 IS FORCED TO 4.5A BY INTEGRATION IN CAGC
30dB 20dB 10dB 0dB 0
0.4V 1.8V 1V NORMAL OPERATING RANGE
(21.5dB)
MIXER GAIN
(7.5dB) (1.5dB) 2V Vg
2.2V
Figure 45. Simplified Schematic of AGC Detector
Figure 43. Gain Distribution for GREF = 1.5 V
90dB 80dB 70dB 60dB 50dB (67.5dB)
Acting against this is an internally generated 4.5 A pull-down current, which operates to within a few millivolts of ground. As VG, the voltage at the GAIN/RSSI pin, rises, the gain falls, so reducing the amplitude of the IF output and reducing the amplitude of the current spike in Q2; eventually a point is reached where its average collector current is balanced by the pull-down current, and the charging ceases. It will be apparent that the loop filter is essentially a perfect integrator. This simple system can be used because the input impedance of the gain-control system, also internally tied to the GAIN/RSSI pin, is several megohms, and its bias current is small. The voltage VG may be used as an RSSI output; however, if it is to be heavily loaded, a buffer amplifier must be used.
IF GAIN
40dB 30dB 20dB 10dB 0dB 0
0.328V
(21.5dB)
MIXER GAIN
(7.5dB) (1.5dB) 1V NORMAL OPERATING RANGE
1.64V
2V Vg
Figure 44. Gain Distribution for GREF = 1.23 V
Using the Internal AGC Detector
Note that, unlike a post-demodulation AGC detector (via DSP), this scheme responds to signal plus noise. Thus, when operating at high gains, the AGC loop will "see" a substantial output at the IFOP node, even though a filter may be added by the user between the pins IFOP and DMIP. This will trick the loop into lowering the gain until the composite output signal (IF plus noise) reaches the reference level and satisfies the averagecurrent requirement. In these circumstances, the wanted signal will be smaller than expected. Thus, the internal AGC system will result in a slight compression of the demodulated output for very small signal levels.
AGC Discharge Time
The AD607 includes a detector cell at the output of the IF amplifier that allows it to provide its own AGC and output-leveling function in receiver applications where DSP support is not needed. It is only necessary to connect a filter capacitor between the GAIN pin and ground to invoke this feature. The voltage appearing on this pin may then be used as an RSSI output, with the scaling discussed earlier; note particularly that the voltage on GREF continues to determine this scaling. Figure 45 shows a simplified schematic of the detector. Transistor Q2 remains cut off by a 300 mV bias (when VP = 3 V; in general, VP/10) until the positive tip of the IF waveform causes it to briefly conduct, charging the AGC filter capacitor CAGC in a positive direction. The voltage across this capacitor is VG.
The discharge current is approximately 4.5 A; thus, to restore gain in the event of a rapid drop-out requires a time of T = C x VG/4.5 A. Using a 1 nF capacitor, and noting that an 80 dB gain change corresponds to 1.6 V, the discharge time is 355 s. Note, however, that when GREF is tied to a different value, the scaling changes. For GREF = 1.23 V, the scale factor is 16.4 mV/dB, 80 dB corresponds to a 1.312 V change, and the discharge time decreases to 290 s. VG could also be expressed in dB: with a scaling of 20 mV/dB, it works out to T = C x P x 44,000, where P is the change in input power, expressed in dB. Thus, using C = 1 nF, checking the time needed for 80 dB we get T = 355 s. For the case where the scaling is 16.4 mV/dB, T = C x P x 36,000. The AD607's AGC detector delivers only one brief charging pulse per cycle of the IF. At a 10.7 MHz IF, for example, this is every 93 ns. When the AGC system is in equilibrium, this pulse
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AD607
of current exactly balances the 4.5 A discharge current. (It makes no difference what the actual value of VG is at that point, since the AGC filter is an integrator.) Thus, at 20 mV/dB pass filter does. This "input" is an INCREASED AMPLITUDE required at IFOP. The AGC loop thus does not level the output at IFOP.
Reasons for Using a Larger AGC Capacitor
VRIPPLE =
IT C
=
4.5 A x 93 ns 1 nF
= 0.42 mV
1. In applications where gain modulation may be troublesome, raise the capacitor from 1 nF to 2.7 nF; the 80 dB slew time (at 20 mV/dB) is now close to 1 ms. 2. As the IF is lowered, the capacitor must be increased accordingly if gain ripple is to be avoided. Thus, to achieve the same ripple at 455 kHz requires the 1 nF capacitor to be increased to 0.022 F. 3. In AM applications, the AGC loop must not track the modulation envelope. The objective should be that the gain should not vary by more than the amount required to introduce, say, 1% THD distortion at the lowest modulation frequency, say, 300 Hz. Note that in AM applications it is the modulation bandwidth that determines the required AGC filter capacitor, not the IF. 4. In some applications, even slower AGC may be desired than that required to prevent modulation tracking.
AD607 EVALUATION BOARD
This corresponds to 0.021 dB, and the ripple will modulate the gain by that amount over each cycle. The effect of such modulation on the signal is hard to quantify, but it roughly translates to a 2% amplitude modulation. Also, the gain ripple depends on the scale factor. For this example, at GREF = 1.23 V and a 16.4 mV/dB scale factor, the gain ripple increases to 0.025 dB.
AGC Charge Time
When the gain is too high, the IF amplifier will be overdriven to produce a square wave output (roughly) of 560 mV. If perfectly square and time- and amplitude-symmetric, this would be sliced at the 300 mV level to generate a current of 76 A/2, or 38 A. After subtracting the 4.5 A, we should have about 33 A. In fact, the maximum ramp-up current is about 20 A, because the waveform is not a crisp square wave (and as the loop approaches equilibrium it is more nearly sinusoidal). Thus, the ramp-up rate is 20/4.5 = 4.4 times faster than the discharge rate. In our example, a 1.6 V change will require about 1.5 ms using C = 1 nF.
Applications Hints
Do not place a resistor from Pin 12 to Ground: The resistor converts the integrator--ideal for AGC--into a low-pass filter. An integrator needs no input to sustain a given output; a lowVPOS GND
The AD607 evaluation board (Figures 46 and 47) consists of an AD607, ground plane, I/O connectors, and a 10.7 MHz bandpass filter. The RF and LO ports are terminated in 50 to provide a broadband match to external signal generators to allow a choice of RF and LO input frequencies. The IF filter is at 10.7 MHz and has 330 input and output terminations; the board is laid out to allow the user to substitute other filters for other IFs.
C15 0.1F C11 10nF
JUMPER R10 4.99k C12 0.1F FDIN R9 0 COM1 PRUP LOIP C9 1nF C16 1nF RFLO RFHI VPS1 R1 FLTR IOUT QOUT 1k I C2 0.1F C4 47pF Q C3 10nF R11 OPEN C1 0.1F
FDIN
R8 51.1
PRUP C13 0 LO C14 0 RF R6 51.1 R5 332 R3 R7 51.1 C10 1nF
AD607
VPS2 DMIP IFOP COM2 GAIN IFLO C6 0.1F C8 0.1F R2 316
GREF JUMPER R4 0 MXOP VMID IFHI 332 C7 1nF
IF RSSI
C5 1nF
AD607 EVALUATION BOARD (AS RECEIVED)
VPOS R15 50k C18 SHORT FDIN FDIN R14 51.1 C17 10nF R12 OPEN VMID FDIN R19 RSOURCE C20 SHORT R16 OPEN R13 50k C19 ANYTHING FDIN R17 OPEN R18 OPEN VPOS
VMID
MOD FOR LARGE MAGNITUDE AC COUPLED INPUT
MOD FOR DC COUPLED INPUT
Figure 46. Evaluation Board
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AD607
Figure 47. Evaluation Board Layout
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AD607
The board provides SMA connectors for the RF and LO port inputs, the demodulated I and Q outputs, the manual gain control (MGC) input, the PLL input, and the power-up input. In addition, the IF output is also available at an SMA connector; this may be connected to the PLL input for carrier recovery to realize synchronous AM and FM detection via the I and Q demodulators, respectively. Table III lists the AD607 Evaluation Board's I/O Connectors and their functions.
Table III. AD607 Evaluation Board Input and Output Connections
Reference Designation J1
Connector Type SMA
Description Frequency Detector Input
Coupling DC
Approximate Signal Level 400 mV
Comments This pin needs to be biased at VMID and ac coupled when driven by an external signal generator.
J2 J3 J4 J5
SMA SMA SMA SMA
Power Up LO Input RF Input MGC Input or RSSI Output IF Output Q Output I Output Ties GREF to VMID Ties Power-Up to Positive Supply Power Supply Positive Input (VPS1, VPS2) Power Supply Return (GND)
DC AC AC DC
CMOS Logic Level Input -16 dBm ( 50 mV) -15 dBm max ( 54 mV) 0.4 V to 2.0 V (3 V Supply) (GREF = VMID) NA NA NA NA
Tied to Positive Supply by Jumper J10. Input is terminated in 50 . Input is terminated in 50 . Jumper is set for Manual Gain Control Input; See Table I for Control Voltage Values. This signal level depends on the AD607's gain setting. This signal level depends on the AD607's gain setting. This signal level depends on the AD607's gain setting. Sets gain-control Scale Factor (SF); SF = 75/VMID in dB/V, where VMID = VPOS/2. Remove to test Power Up/Down.
J6 J7 J8 J9
SMA SMA SMA Jumper
AC AC AC NA
J10
Jumper
NA
NA
T1
Terminal Pin
DC
DC
2.7 V to 5.5 V Draws 8.5 mA at midgain connection.
T2
Terminal Pin
DC
0V
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AD607
In operation (Figure 48), the AD607 evaluation board draws about 8.5 mA at midgain (59 dB). Use high impedance probes to monitor signals from the demodulated I and Q outputs and the IF output. The MGC voltage should be set such that the signal level at DMIP does not exceed 150 mV; signal levels above this will overload the I and Q demodulators. The insertion loss between IFOP and DMIP is typically 3 dB if a simple low-pass filter (R8 and C2) is used and higher if a reverseterminated bandpass filter is used. If the AD607's internal AGC detector is used, then the GAIN/ RSSI (Pin 12) becomes an output and the RSSI voltage appears across C12, which serves as an integrating capacitor. This voltage must be monitored by a high impedance (100 k minimum) probe. The internal AGC loop holds the IF voltage at IFOP (Pin 14) at 300 mV; in this application, about 6 dB of attenuation is needed between pins IFOP and DMIP to avoid overloading the I and Q demodulators.
HP 6632A PROGRAMMABLE POWER SUPPLY 2.7V-6V
HP 3326 SYNTHESIZED SIGNAL GENERATOR 10.710 MHz
FLUKE 6082A SYNTHESIZED SIGNAL GENERATOR 240 MHz MCL ZFSC-2-1 COMBINER HP 8656A SYNTHESIZED SIGNAL GENERATOR 240.02 MHz
VPOS
FDIN I OUTPUT TEKTRONIX 11402A OSCILLOSCOPE WITH 11A32 PLUGIN
RF
AD607 EVALUATION BOARD LO
Q OUTPUT
MGC
HP 9920 IEEE CONTROLLER HP9121 DISK DRIVE
HP 8656A SYNTHESIZED SIGNAL GENERATOR 229.3 MHz
DATA PRECISION DVC8200 PROGRAMMABLE VOLTAGE SOURCE
IEEE -488 BUS
Figure 48. Evaluation Board Test Setup
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AD607
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Pin Plastic SSOP (RS-20)
20
11
0.212 (5.38) 0.205 (5.207) 0.311 (7.9) 0.301 (7.64) 1 10
PIN 1
0.295 (7.50) 0.271 (6.90)
0.07 (1.78) 0.066 (1.67)
0.008 (0.203) 0.002 (0.050)
0.0256 (0.65) BSC
0.009 (0.229) 0.005 (0.127)
8 0
0.037 (0.94) 0.022 (0.559)
1. LEAD NO. 1 IDENTIFIED BY A DOT. 2. LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS
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C2047-10-7/95
PRINTED IN U.S.A.

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