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Ordering number : ENN7257A
Monolithic Digital IC
LB11872H
Three-Phase Brushless Motor Driver for Polygonal Mirror Motors
Overview
The LB11872H is a three-phase brushless motor driver developed for driving the motors used for the polygonal mirror in laser printers and similar applications. It can implement, with a single IC chip, all the circuits required for polygonal mirror drive, including speed control and driver functions. The LB11872H can implement motor drive within minimal drive noise due to its use of current linear drive.
Package Dimensions
unit: mm 3233A-HSOP28H
[LB11872H]
15.2 (6.2) 0.65 0.25
28
15
Functions and Features
* Three-phase bipolar current linear drive + midpoint control circuit * PLL speed control circuit * Speed is controlled by an external clock signal. * Supports Hall FG operation. * Built-in output saturation prevention circuit * Phase lock detection output (with masking function) * Includes current limiter, thermal protection, rotor constraint protection, and low-voltage protection circuits on chip. * On-chip output diodes.
1
(0.8) (2.25) 0.8 2.0
14
0.3
2.45max
0.1
2.7
SANYO: HSOP28H
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Supply voltage Output current Allowable power dissipation 1 Allowable power dissipation 2 Operating temperature Storage temperature Symbol VCC max IO max Pd max1 Pd max2 Topr Tstg T 500 ms Independent IC Mounted on a PCB (114.3 x 76.1 x 1.6 mm, glass epoxy) Conditions Ratings 30 1.2 0.8 2.0 -20 to +80 -55 to +150 Unit V A W W C C
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
91002AS (OT) No. 7257 -1/13
10.5
7.9
4.9
LB11872H Allowable Operating Ranges at Ta = 25C
Parameter Supply voltage range 6.3 V regulator-voltage output current LD pin applied voltage LD pin output current FGS pin applied voltage FGS pin output current Symbol VCC IREG VLD ILD VFG IFG Conditions Ratings 10 to 28 0 to -20 0 to 28 0 to 15 0 to 28 0 to 10 Unit V mA V mA V mA
Electrical Characteristics at Ta = 25C, VCC = VM = 24 V
Parameter Supply current 1 Supply curren 2 [Output Saturation Voltages SOURCE (1) SOURCE (2) SINK (1) SINK (2) Output leakage current [6.3 V Regulator-Voltage Output] Output voltage Voltage regulation Load regulation Temperature coefficient [Hall Amplifier Block] Input bias current Differential input voltage range Common-phase input voltage range Input offset voltage [FG Amplifier and Schmitt Block (IN1)] Input amplifier gain Input hysteresis (high to low) Input hysteresis (low to high) Hysteresis width [Low-Voltage Protection Circuit] Operating voltage Hysteresis width [Thermal Protection Circuit] Thermal shutdown operating temperature Hysteresis width [Current Limiter Operation] Acceleration limit voltage Deceleration limit voltage [Error Amplifier] Input offset voltage Input bias current High-level output voltage Low-level output voltage DC bias level [Phase Comparator Output] High-level output voltage Low-level output voltage Output source current Output sink current VPDH VPDL IPD+ IPD- IOH = -100 A IOL = 100 A VPD = VREG/2 VPD = VREG/2 1.5 VREG - 0.2 VREG - 0.1 0.2 0.3 -500 V V A mA VIO (ER) IB (ER) VOH (ER) IOH = -500 A VOL (ER) VB (ER) IOL = 500 A -5% Design target value -10 -1 VREG - 1.2 VREG - 0.9 0.9 1/2VREG 1.2 5% 10 1 mV A V V V VRF1 VRF2 0.53 0.32 0.59 0.37 0.65 0.42 V V TSD TSD Design target value (junction temperature) Design target value (junction temperature) 150 180 40 C C VSD VSD 8.4 0.2 8.8 0.4 9.2 0.6 V V GFG VSHL VSLH VFGL Input conversion 4 5 0 -10 7 12 deg mV mV mV IB (HA) VHIN VICM VIOH Differential input: 50 mVp-p SIN wave input Differential input: 50 mVp-p Design target value 50 2.0 -20 2 10 *600 VCC - 2.5 20 A mVp-p V mV VREG VREG1 VREG2 VREG3 VCC = 9.5 to 28 V Iload = -5 to -20 mA Design target value 5.90 6.25 50 10 0 6.60 100 60 V mV mV mV/C VAGC = 3.5 V] VSAT1-1 VSAT1-2 VSAT2-1 VSAT2-2 IO = 0.5 A, RF = 0 IO = 1.0 A, RF = 0 IO = 0.5 A, RF = 0 IO = 1.0 A, RF = 0 1.7 2.0 0.4 1.0 2.2 2.7 0.9 1.7 100 V V V V A Symbol ICC1 ICC2 Stop mode Start mode Conditions Ratings min typ 5 17 max 7 22 Unit mA mA
IO (LEAK) VCC = 28 V
Note*: Since kickback can occur in the output waveform if the Hall input amplitude is too large, the Hall input amplitudes should be held to under 350 mVp-p.
Continued on next page.
No. 7257 -2/13
LB11872H
Continued from preceding page.
Parameter [Lock Detection Output] Output saturation voltage Output leakage current [FG Output] Output saturation voltage Output leakage current [Drive Block] Dead zone width Output idling voltage Forward gain 1 Forward gain 2 Reverse gain 1 Reverse gain 2 Acceleration command voltage Deceleration command voltage Forward limiter voltage Reverse limiter voltage [CSD Oscillator Circuit] Oscillation frequency High-level pin voltage Low-level pin voltage External capacitor charge and discharge current Lock detection delay count Clock cutoff protection operating count Lock protection count Initial reset voltage [Clock Input Block] External input frequency High-level input voltage Low-level input voltage Input open voltage Hysteresis width High-level input current Low-level input current [S/S Pin] High-level input voltage Low-level input voltage Input open voltage Hysteresis width High-level input current Low-level input current VIH (S/S) VIL (S/S) VIO (S/S) VIS (S/S) IIH (S/S) IIL (S/S) V (S/S) = VREG V (S/S) = 0 V -185 2.0 0 2.7 0.1 3.0 0.2 140 -140 VREG 1.0 3.3 0.3 185 V V V V A A fCLK VIH (CLK) Design target value VIL (CLK) Design target value VIO (CLK) VIS (CLK) Design target value IIH (CLK) IIL (CLK) V (CLK) = VREG V (CLK) = 0 V -185 400 2.0 0 2.7 0.1 3.0 0.2 140 -140 10000 VREG 1.0 3.3 0.3 185 Hz V V V V A A fOSC VCSDH VCSDL ICHG CSDCT1 CSDCT2 CSDCT3 VRES C = 0.022 F 4.3 0.75 3 31 4.8 1.15 5 7 2 31 0.60 0.80 V 5.3 1.55 7 Hz V V A VDZ VID GDF+1 GDF+2 GDF-1 GDF-2 VSTA VSTO VL1 VL2 Rf = 22 Rf = 22 0.53 0.32 With phase locked With phase unlocked With phase locked With phase unlocked 0.4 0.8 -0.6 -0.8 5.0 0.5 1.0 -0.5 -1.0 5.6 0.8 0.59 0.37 1.5 0.65 0.42 With the phase is locked 50 100 300 6 0.6 1.2 -0.4 -1.2 mV mV deg deg deg deg V V V V VFG (SAT) IFG = 5 mA IFG (LEAK) VFG = 28 V 0.15 0.5 10 V A VLD (SAT) ILD = 10 mA ILD (LEAK) VLD = 28 V 0.15 0.5 10 V A Symbol Conditions Ratings min typ max Unit
Three-Phase Logic
OUT1 to OUT3 (H: Source, L: Sink) IN1 H H H L L L IN2 L L H H H L IN3 H L L L H H OUT1 L L M H H M OUT2 H M L L M H OUT3 M H H M L L
For IN1 to IN3, "H" means that IN+ is greater than IN-, and "L" means IN- is greater than IN+. For OUT1 to OUT3, "H" means the output is a source, and "L" means that it is a sink.
No. 7257 -3/13
LB11872H Pin Arrangement
VREG
OUT3
OUT2
OUT1
VCC
GND
SUB
CLK 16
28
27
26
25
24
23
22
21
20
19
18
17
15
S/S
EO
PD
FC
RF
LD
EI
LB11872H
1 NC 2 IN2+ 3 IN2- 4 IN1+ 5 IN1- 6 IN3+ 7 GND IN3- 8 AGC 9 MN 10 NC 11 NC 12 CSD 13 NC 14 FG
Pd max - Ta
2.4 Mounted on a specified board. (114mm x 71.1mm x 1.6mmt, glass epoxy) 2
Allowable Power Dissipation, Pdmax - W
1.6
1.2 Independent IC 0.8
1.12
0.45 0.4
0 -20 0 20 40 60 80 100
Ambient temprature, Ta - C
No. 7257 -4/13
HSOP28H
LB11872H Pin Functions
Pin No. FRAME 1 Symbol GND NC GND pin NC (No connection) pin These pins input the Hall effect sensor signal for each phase. The logic of these inputs is that the input is "high" when VIN+ is greater than VIN-. Insert a capacitor between pin 8 and ground. This pin must be left open. Pin
2 to 7
IN1+ to IN3+ IN1- to IN3-
Hall sensor input pins
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 to 28
AGC MN NC NC CSD NC FG S/S CLK LD PD EI EO FC VREG VCC SUB Rf OUT1 to 3
Frequency characteristics correction pin Test pin
Phase lock detection chattering prevention pin
Insert a capacitor between pin 12 and ground.
FG output pin Start/stop switching pin Clock signal input pin Phase lock detection output pin Phase comparator output pin Error amplifier input pin Error amplifier output pin Frequency characteristics correction pin Stabilized power supply output pin Power supply pin SUBGND pin Output current detection pin Output pins
This is an open-collector output Low: start mode
This pin goes to the on state when the phase is locked. It is an open-collector output.
Insert a capacitor between pin 21 and ground. Insert a capacitor between pin 22 and ground.
Connect this pin to ground. Insert a resistor between pin 25 and ground.
No. 7257 -5/13
CLK
CLK PD 18 23 Vcc TSD LVSD
PD
EI 19 EO 20
16
Vreg
22
6.3VREG
Vcc
LB11872H Equivalent Circuit Block Diagram
CSD
12
OSC CLOCK DET
15 S/S PLL LOCK DET
LD
RESET V - AMP
S/S 21 FC
LB11872H
LD
LD 17
RESTRICT DET
OCL
25 RF
FG
FG 14 FG
26 OUTPUT 27 28
OUT1 OUT2 OUT3
x5
FILTER
MN 9 HALL AMP & MATRIX AGC
4
5 IN1
2
3 IN2
6
7 IN3
8 AGC
24 SUB
FREAM GND
No. 7257 -6/13
LB11872H Pin Circuits and Functions
Pin No. Pin Function Equivalent circuit
Vcc
Hall effect sensor signal inputs 2 3 4 5 6 7 IN2+ IN2- IN1+ IN1- IN3+ IN3- These inputs are high when IN+ is greater than IN- and low when IN- is greater than IN+. Insert capacitors between the IN+ and IN- pins to reduce noise. An amplitude of over 50 mA p-p and under 350 mVp-p is desirable for the Hall input signals. Kickback can occur in the output waveform if the Hall input amplitude is over 350 mVp-p.
3
5
7
300
300
2
4
6
VREG
AGC amplifier frequency characteristics correction. 8 AGC Insert a capacitor (about 0.022 F) between this pin and ground.
300 8
9
MN
Monitor pin This pin should be left open in normal operation.
VREG
12
CSD
Used for both initial reset pulse generation and as the reference time for constraint protection circuits. Insert a capacitor between this pin and ground.
300
12
VREG
14
14 FG FG pulse output. This is an open-collector output.
VREG
33k
Start/stop control. 15 S/S Low: Start 0 to 1.0 V High: Stop 2.0 V to VREG This pin goes to the high level when open.
5k 15 30k
Continued on next page. No. 7257 -7/13
LB11872H
Continued from preceding page.
Pin No. Pin Function Equivalent circuit
VREG
Clock input. 16 CLK Low: 0 to 1.0 V High: 2.0 V to VREG This pin goes to the high level when open.
33k 5k 16 30k
VREG
Phase locked state detection output 17 LD This output goes to the on state when the PLL locked state is detected. This is an open-collector output.
17
VREG
Phase comparator output (PLL output) 18 PD This pin output the phase error as a pulse signal with varying duty.The output current increases as the duty becomes smaller.
18
VREG
19
EI
Error amplifier in put pin.
300 19
VREG
20
EO
Error amplifier output pin. The output current increases when this output is high.
300 40k
20
Continued on next page. No. 7257 -8/13
LB11872H
Continued from preceding page.
Pin No. Pin Function Equivalent circuit
VREG
Control amplifier frequency correction. Inserting a capacitor (about 5600 pF) between this pin and ground will stop closed loop oscillation in the current control system. The output current response characteristics will be degraded if the capacitor is too large.
21
21
FC
Vcc
Stabilized power supply (6.3 V) 22 VREG Insert a capacitor (about 0.1 F) between this pin and ground for stabilization.
22
23 24
VCC SUB
Power supply SUB pin. Connect this pin to ground. Output current detection.
25
RF
Insert low-valued resistors (Rf) between these pins and ground. The output current will be limited to the value set by the equation IOUT = VL/RF.
Vcc
VREG 26 27 28
26 27 28 OUT1 OUT2 OUT3 Motor drive outputs. If the output oscillates, insert a capacitor (about 0.1 F) between this pin and ground.
300 25
1 10 11 13 FRAME GND Ground NC No connection (NC) pins. These pins may be used for wiring connections.
No. 7257 -9/13
LB11872H Overview of the LB11872H 1. Speed Control Circuit This IC adopts a PLL speed control technique and provides stable motor operation with high precision and low jitter. This PLL circuit compares the phase error at the edges of the CLK signal (falling edges) and FG signal (rising edges (low to high transitions) on the IN1 input), and the IC uses the detected error to control the motor speed. During this control operation, the FG servo frequency will be the same as the CLK frequency. fFG (servo) = fCLK 2. Output Drive Circuit To minimize motor noise, this IC adopts three-phase full-wave current linear drive. This IC also adopts a midpoint control technique to prevent ASO destruction of the output transistors. Reverse torque braking is used during motor deceleration during speed switching and lock pull-in. In stop mode, the drive is cut and the motor is left in the free-running state. Since the output block may oscillate depending on the motor actually used, capacitors (about 0.1 F) must be inserted between the OUT pins and ground. 3. Hall Input Signals This IC includes an AGC circuit that minimizes the influence on the output of changes in the Hall signal input amplitudes due to the motor used. However, note that if there are discrepancies in the input amplitudes between the individual phases, discrepancies in the output phase switching timing may occur. An amplitude (differential) of at least 50 mVp-p is required in the Hall input signals. However, if the input amplitude exceeds 350 mVp-p, the AGC circuit control range will be exceeded and kickback may occur in the output. If Hall signal input frequencies in excess of 1 kHz (the frequency in a single Hall input phase) are used, internal IC heating during startup and certain other times (that is, when the output transistors are saturated) may increase. Reducing the number of magnetic poles can be effective in dealing with problem. The IN1 Hall signal is used as the FG signal for speed control internally to the IC. Since noise can easily become a problem, a capacitor must be inserted across this input. However, since this could result in differences between the signal amplitudes of the three phases, capacitors must be inserted across all of the three input phases. Although VCC can be used as the Hall element bias power supply, using VREG can reduce the chances of problems occurring during noise testing and at other times. If VREG is used, since there is no longer any need to be concerned with the upper limit of the Hall amplifier common-mode input voltage range, bias setting resistors may be used only on the low side. 4. Power Saving Circuit This IC goes into a power saving state that reduces the current drain in the stop state. The power saving state is implemented by removing the bias current from most of the circuits in the IC. However, the 6.3 V regulator output is provided in the power saving state. 5. Reference Clock Care must be taken to assure that no chattering or other noise is present on the externally input clock signal. Although the input circuit does have hysteresis, if problems do occur, the noise must be excluded with a capacitor. This IC includes an internal clock cutoff protection circuit. If a signal with a frequency below that given by the formula below is input, the IC will not perform normal control, but rather will operate in intermittent drive mode. f (Hz) .=. 0.64 / CCSD CCSD (F): The capacitor inserted between the CSD pin and ground. When a capacitor of 0.022 F is used, the frequency will be about 29 Hz. If the IC is set to the start state when the reference clock signal is completely absent, the motor will turn somewhat and then motor drive will be shut off. After the motor stops and the rotor constraint protection time elapses, drive will not be restarted, even if the clock signal is then reapplied. However, drive will restart if the clock signal is reapplied before the rotor constraint protection time elapses.
No. 7257 -10/13
LB11872H 6. Rotor Constraint Protection Circuit This IC provides a rotor constraint protection circuit to protect the IC itself and the motor when the motor is constrained physically, i.e. prevented from turning. If the FG signal (edges of one type (rising or falling edges) on the IN1 signal) does not switch within a fixed time, output drive will be turned off. The time constant is determined by the capacitor connected to the CSD pin. .=. 30.5 x 1.57 x CCSD (F) If a 0.02 F capacitor is used, the protection time will be about 1.05 seconds. To clear the rotor constraint protection state, the IC must be set to the stopped state or the power must be turned off and reapplied. If there is noise present on the FG signal during the constraint time, the rotor constraint protection circuit may not operate normally. 7. Phase Lock Signal (1) Phase lock range Since this IC does not include a counter or similar functionality in the speed control system, the speed error range in the phase locked state cannot be determined solely by IC characteristics. (This is because the acceleration of the changes in the FG frequency influences the range.) When it is necessary to stipulate this characteristic for the motor, the designer must determine this by measuring the actual motor state. Since speed errors occur easily in states where the FG acceleration is large, it is thought that the speed errors will be the largest during lock pull-in at startup and when unlocked due to switching clock frequencies. (2) Masking function for the phase lock state signal A stable lock signal can be provided by masking the short-term low-level signals due to hunting during lock pullin. However, this results in the lock state signal output being delayed by the masking time. The masking time is determined by the capacitor inserted between the CSD pin and ground. .= 6.5 x 1.57 x CCSD (F) . When a 0.022 F capacitor is used, the masking time will be about 225 ms. In cases where complete masking is required, a masking time with fully adequate margin must be used. 8. Initial Reset To initially reset the logic circuits in start mode, the IC goes to the reset state when the CSD pin voltage goes to zero until it reaches 0.63 V. Drive output starts after the reset state is cleared. The reset time can be calculated to a good approximation using the following formula. .=. 0.13 x CCSD (F) A reset time of over 100 s is required. 9. Current Limiter Circuit The current limit value is determined by the resistor Rf inserted between the RF pin and ground. ILIM = VL/Rf VL = 0.59 V (typical) (during acceleration) and 0.37 V (typical) (during deceleration) 10. Power Supply Stabilization An adequately large capacitor must be inserted between the VCC pin and ground for power supply stabilization. If diodes are inserted in the power supply lines to prevent destruction of the device if the power supply is connected with reverse polarity, the power supply line levels will be even more easily disrupted, and even larger capacitors must be used. If high-frequency noise is a problem, a ceramic capacitor of about 0.1 F must also be inserted in parallel.
No. 7257 -11/13
LB11872H 11. VREG Stabilization A capacitor of at least 0.1 F must be used to stabilize the VREG voltage, which is the control circuit power supply. The capacitor must be connected as close as possible to the pins. 12. Error Amplifier External Component Values To prevent adverse influence from noise, the error amplifier external components must be located as close to the IC as possible. 13. FRAME Pin and Heat sink Area The FRAME pin and the heat sink area function as the control circuit ground terminal. It is desirable that this ground line and the Rf resistor ground line be grounded at a single point at the ground for the electrolytic capacitor. Thermal dissipation can be improved significantly by tightly bonding the metallic surface of the back of the IC package to the PCB with, for example, a solder with good thermal conductivity. 14. CSD Pin The capacitor connected to the CSD pin influences several operational aspects of this IC, including the rotor constraint protection time and the phase lock signal mask time. The following are possible ways of determining the value of this capacitor. (1) If removing chattering from the phase lock state signal is most important: Select a capacitance that can assure an adequate mask time. (2) If startup time is more important than chattering: Select a capacitance such that the rotor constraint protection circuit does not operate at startup time and verify that there are no problems with the clock cutoff protection circuit and initial reset time. Operation of the rotor constraint protection circuit may hinder the study of motor characteristics in the uncontrolled state. It is possible to only operate the initial reset function and not operate the rotor constraint protection circuit by inserting a resistor (about 390 k) in parallel with the capacitor between the CSD pin and ground. 15. FC Pin The capacitor connected to the FC pin is required for current limiter loop phase compensation. If the value is too low, the output will oscillate. If the value is too large, it will be easier for currents in excess of the limit value to flow during the current limit time (time before the circuit operates) in states where the output is saturated. (This is because the control response characteristics become worse.) 16. AGC Pin A capacitance that allows a certain amount of smoothing of the AGC pin voltage in the motor speed range used must be selected for the capacitor connected to the AGC pin. It is also desirable to use a capacitance that allows the AGC voltage to reach an essentially stabilized voltage before the initial reset is cleared. (If the capacitance is too large, the rate of change of the AGC voltage will become slower.)
No. 7257 -12/13
LB11872H
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of September 2002. Specifications and information herein are subject to change without notice. PS No. 7257 -13/13

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