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Final Electrical Specifications
LT4250L/LT4250H Negative 48V Hot Swap Controller
April 2001
FEATURES
s s
DESCRIPTIO
s
s s s s s s
Allows Safe Board Insertion and Removal from a Live - 48V Backplane Circuit Breaker Immunity to Voltage Steps and Current Spikes Programmable Inrush and Short-Circuit Current Limits Pin Compatible with LT1640L/LT1640H Operates from -20V to - 80V Programmable Overvoltage Protection Programmable Undervoltage Lockout Power Good Control Output Bell-Core Compatible ON/OFF Threshold
APPLICATIO S
s s s
The LT(R)4250L/LT4250H are 8-pin, negative 48V Hot SwapTM controllers that allow a board to be safely inserted and removed from a live backplane. Inrush current is limited to a programmable value by controlling the gate voltage of an external N-channel pass transistor. The pass transistor is turned off if the input voltage is less than the programmable undervoltage threshold or greater than the overvoltage threshold. A programmable current limit protects the system against shorts. After a 500s timeout the current limit activates the electronic circuit breaker. The PWRGD (LT4250L) or PWRGD (LT4250H) signal can be used to directly enable a power module. The LT4250L is designed for modules with a low enable input and the LT4250H for modules with a high enable input. The LT4250L/LT4250H are available in 8-pin PDIP and SO packages.
, LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation.
Central Office Switching - 48V Distributed Power Systems Negative Power Supply Control
TYPICAL APPLICATIO
GND GND R4 549k 1% R5 6.49k 1% R6 10k 1% (SHORT PIN)
8 VDD 3 UV LT4250L 2 OV VEE 4 SENSE 5 GATE 6 R3 1k, 5% C1 470nF 25V 4 2 Q1 IRF530 R2 10 5% C2 15nF 100V 2 ON/OFF 1 9 VOUT+ VIN+ +8 SENSE 7 TRIM -6 SENSE 4 5 VOUT- VIN- LUCENT JW050A1-E 5V DRAIN 7 PWRGD 1
UV = 38.5V UV RELEASE AT 43V OV = 71V
* INPUT 1 3 1 INPUT 2 C3 0.1F 100V R1 0.02 5%
+
* DIODES INC. SMAT70A THESE COMPONENTS ARE APPLICATION SPECIFIC AND MUST BE SELECTED BASED UPON OPERATING CONDITIONS AND DESIRED PERFORMANCE. SEE APPLICATIONS INFORMATION.
C4 100F 100V
+
C5 100F 16V
4250 TA01
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
Voltage Step On Input Supply
VEE AND DRAIN RELATIVE TO GND ID(Q1)
5A
U
U
1
LT4250L/LT4250H ABSOLUTE MAXIMUM RATINGS U WW U W
(Note 1), All Voltages Referred to VEE
Supply Voltage (VDD - VEE) .................... - 0.3V to 100V DRAIN, PWRGD, PWRGD Pins ............... - 0.3V to 100V SENSE, GATE Pins .................................... - 0.3V to 20V UV, OV Pins .............................................. - 0.3V to 60V Maximum Junction Temperature ......................... 125C
Operating Temperature Range LT4250LC/LT4250HC ............................. 0C to 70C LT4250LI/LT4250HI .......................... - 40C to 85C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
PACKAGE/ORDER I FOR ATIO
TOP VIEW PWRGD 1 OV 2 UV 3 VEE 4 N8 PACKAGE 8-LEAD PDIP 8 7 6 5 VDD DRAIN GATE SENSE
ORDER PART NUMBER LT4250LCN8 LT4250LCS8 LT4250LIN8 LT4250LIS8 S8 PART MARKING 4250L 4250LI
PWRGD 1 OV 2 UV 3 VEE 4 N8 PACKAGE 8-LEAD PDIP
S8 PACKAGE 8-LEAD PLASTIC SO
TJMAX = 125C, JA = 120C/W (N8) TJMAX = 125C, JA = 150C/W (S8)
Consult factory for parts specified with wider operating temperature ranges.
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 2), VDD = 48V, VEE = 0V unless otherwise noted.
SYMBOL DC VDD IDD VUVLOH VUVLOL VCL IPU IPD ISENSE VGATE VUVH VUVL VUVHY IINUV VOVH VOVL Supply Voltage Operating Range Supply Current Undervoltage Lockout Voltage High Undervoltage Lockout Voltage Low Current Limit Trip Voltage GATE Pin Pull-Up Current GATE Pin Pull-Down Current SENSE Pin Current External Gate Drive UV Pin High Threshold Voltage UV Pin Low Threshold Voltage UV Pin Hysteresis UV Pin Input Current OV Pin High Threshold Voltage OV Pin Low Threshold Voltage VUV = VEE OV Increasing OV Decreasing
q q q q
ELECTRICAL CHARACTERISTICS
PARAMETER
CONDITIONS
UV = 3V, OV = VEE, SENSE = VEE VDD Low to High Transition VDD High to Low Transition VCL = (VSENSE - VEE) Gate Drive On, VGATE = VEE Gate Drive OFF VSENSE = 50mV (VGATE - VEE), 20V VDD 80V UV Increasing UV Decreasing
2
U
TOP VIEW 8 7 6 5 VDD DRAIN GATE SENSE
W
ORDER PART NUMBER LT4250HCN8 LT4250HCS8 LT4250HIN8 LT4250HIS8 S8 PART MARKING 4250H 4250HI
S8 PACKAGE 8-LEAD PLASTIC SO
TJMAX = 125C, JA = 120C/W (N8) TJMAX = 125C, JA = 150C/W (S8)
MIN 20
TYP
MAX 80
UNITS V mA V V
q q q q q
1.6 15.4 15.4 40 - 30 24 50 - 45 50 - 20 13.5 1.255 1.125 130 - 0.02 1.235 1.215 1.255 1.235
5
60 - 60 70 18 1.270 1.145 - 0.5 1.275 1.255
mV A mA A V V V mV A V V
q q q
10 1.240 1.105
LT4250L/LT4250H
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 2), VDD = 48V, VEE = 0V unless otherwise noted.
SYMBOL VOVHY IINOV VDL VGH IDRAIN VOL PARAMETER OV Pin Hysteresis OV Pin Input Current DRAIN Low Threshold GATE High Threshold Drain Input Bias Current PWRGD Output Low Voltage VOV = VEE VDRAIN - VEE, High to Low Transition VGATE - VGATE, High to Low Transition VDRAIN = 48V PWRGD (LT4250L), (VDRAIN - VEE) < VDL IOUT = 1mA IOUT = 5mA PWRGD (LT4250H), VDRAIN = 5V IOUT = 1mA PWRGD (LT4250L), VDRAIN = 48V, VPWRGD = 80V PWRGD (LT4250H), VDRAIN = 0V, VPWRGD = 80V Figures 1a, 2 Figures 1a, 3 Figures 1a, 2 Figures 1a, 3 Figures 1a, 4a Figures 1b, 4b
q q q q q q q
ELECTRICAL CHARACTERISTICS
CONDITIONS
MIN
TYP 20 - 0 .03
MAX - 0.5 2.0 250 0.8 3.0 1.0 10 10
UNITS mV A V V A V V V A A s s s s
1.1 10
1.6 1.3 80 0.48 1.2 0.75 0.05 0.05 1.7 1.5 5.5 6.5 1 500 1 1 1.5 1.5
PWRGD Output Low Voltage (PWRGD - DRAIN) IOH AC tPHLOV tPHLUV tPLHOV tPLHUV tPHLSENSE tPHLCB tPHLDL tPHLGH OV High to GATE Low UV Low to GATE Low OV Low to GATE High UV High to GATE High SENSE High to Gate Low Current Limit to GATE Low Output Leakage
3
s s s s s s
DRAIN Low to PWRGD Low (LT4250L) Figures 1a, 5a DRAIN Low to (PWRGD - DRAIN) High (LT4250H) Figures 1a, 5a GATE High to PWRGD Low GATE High to (PWRGD - DRAIN) High (LT4250L) Figures 1a, 5b (LT4250H) Figures 1a, 5b
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.
Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to VEE unless otherwise specified.
TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Supply Voltage
1.8 1.7
TA = 25C
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
1.6 1.5 1.4 1.3 1.2 1.1 0 0 20 80 60 SUPPLY VOLTAGE (V) 40 100
1640 G01
GATE VOLTAGE (V)
UW
Supply Current vs Temperature
1.6 VDD = 48V 1.5 1.4 1.3 1.2 1.1
Gate Voltage vs Supply Voltage
15 14 13 12 11 10 9 8 7 TA = 25C
1.0 - 50
- 25
0 25 50 TEMPERATURE (C)
75
100
1640 G02
6 0 20 80 60 40 SUPPLY VOLTAGE (V) 100
1640 G03
3
LT4250L/LT4250H TYPICAL PERFOR A CE CHARACTERISTICS
Gate Voltage vs Temperature
15.0 VDD = 48V 14.5 14.0 13.5 13.0 12.5 12.0 - 50
GATE PULL-UP CURRENT (A)
TRIP VOLTAGE (mV)
GATE VOLTAGE (V)
- 25
25 50 0 TEMPERATURE (C)
Gate Pull-Down Current vs Temperature
55 0.5
PWRGD OUTPUT LOW VOLTAGE (V)
VGATE = 2V
GATE PULL-DOWN CURRENT (mA)
OUTPUT IMPEDANCE (k)
52
49
46
43
40 - 50
- 25
0 50 25 TEMPERATURE (C)
PIN FUNCTIONS
PWRGD/PWRGD (Pin 1): Power Good Output Pin. This pin will latch when VDRAIN is within VDL of VEE and VGATE is within VGH of VGATE. This pin can be connected directly to the enable pin of a power module. When the DRAIN pin of the LT4250L is above VEE by more than VDL or VGATE is more than VGH from VGATE, the PWRGD pin will be high impedance, allowing the pull-up current of the module's enable pin to pull the pin high and turn the module off. When VDRAIN drops below VDL and VGATE rises above VGH, the PWRGD pin sinks current to VEE, pulling the enable pin low and turning on the module. This condition is latched until the GATE pin is turned off via the UV, OV, UVLO or the electronic circuit breaker. When the DRAIN pin of the LT4250H is above VEE by more than VDL or VGATE is more than VGH from VGATE, the PWRGD pin will sink current to the DRAIN pin which pulls the module's enable pin low, forcing it off. When VDRAIN drops below VDL and VGATE rises above VGH, the PWRGD sink current is turned off, allowing the module's pull-up current to pull the enable pin high and turn on the module. This condition is latched until the GATE pin is turned off via the UV, OV, UVLO or the electronic circuit breaker.
4
UW
75
1640 G04
Current Limit Trip Voltage vs Temperature
55 54 53 52 51 50 49 48 - 50
48 47 46 45 44 43 42 41
Gate Pull-Up Current vs Temperature
VGATE = 0V
100
- 25
50 0 25 TEMPERATURE (C)
75
100
1640 G05
40 - 50
- 25
0 25 50 TEMPERATURE (C)
75
100
1640 G06
PWRGD Output Low Voltage vs Temperature (LT4250L)
8
IOUT = 1mA 0.4
PWRGD Output Impedance vs Temperature (LT4250H)
VDRAIN - VEE > 2.4V 7 6 5 4 3 2 - 50
0.3
0.2
0.1
75
100
1640 G07
0 - 50
- 25
25 50 0 TEMPERATURE (C)
75
100
1640 G08
- 25
0 25 50 TEMPERATURE (C)
75
100
1640 G09
U
U
U
LT4250L/LT4250H
PIN FUNCTIONS
OV (Pin 2): Analog Overvoltage Input. When OV is pulled above the 1.255V threshold, an overvoltage condition is detected and the GATE pin will be immediately pulled low. The GATE pin will remain low until OV drops below the 1.235V threshold. UV (Pin 3): Analog Undervoltage Input. When UV is pulled below the 1.125V threshold, an undervoltage condition is detected and the GATE pin will be immediately pulled low. The GATE pin will remain low until UV rises above the 1.255 threshold. The UV pin is also used to reset the electronic circuit breaker. If the UV pin is cycled low and high following the trip of the circuit breaker, the circuit breaker is reset and a normal power-up sequence will occur. VEE (Pin 4): Negative Supply Voltage Input. Connect to the lower potential of the power supply. SENSE (Pin 5): Circuit Breaker Sense Pin. With a sense resistor placed in the supply path between VEE and SENSE, the overcurrent condition will pull down the GATE pin and regulate the voltage across the resistor to be 50mV. If the overcurrent condition exists for more than 500s the electronic circuit breaker will trip. If the current limit value is set to twice the normal operating current, only 25mV is dropped across the sense resistor during normal operation. To disable the current limit feature, VEE and SENSE can be shorted together. GATE (Pin 6): Gate Drive Output for the External N-Channel. The GATE pin will go high when the following start-up conditions are met: the UV pin is high, the OV pin is low, (VSENSE - VEE) < 50mV and the VDD pin is greater than VUVLOH. The GATE pin is pulled high by a 45A current source and pulled low with a 50mA current source. During current limit the GATE pin is pulled low using a 100mA current source. DRAIN (Pin 7): Analog Drain Sense Input. Connect this pin to the drain of the external N-channel and the V - pin of the power module. When the DRAIN pin is below VDL, the PWRGD or PWRGD pin will latch to the true logic state. VDD (Pin 8): Positive Supply Voltage Input. Connect this pin to the higher potential of the power supply inputs and the V + pin of the power module. An undervoltage lockout circuit disables the chip until the VDD pin is greater than the 16V VUVLOH threshold.
BLOCK DIAGRA
UV
REF LOGIC
OV
-+
VEE SENSE
+
-
W
U
+
+
-
-
U
U
VDD
UVLO
VCC AND REFERENCE GENERATOR
VCC REF OUTPUT DRIVE
PWRGD/PWRGD
50mV 500s DELAY GATE DRIVER
+ + -
VEE VDL
-
+
- - +
VGH
VGATE
4250 BD
GATE
DRAIN
5
LT4250L/LT4250H
V+ 5V
R 5k PWRGD/PWRGD VDD OV DRAIN
+ -
VDRAIN
PWRGD/PWRGD VDD 48V OV DRAIN
+ - + -
48V 10k 10
20V
VOV
LT4250L/LT4250H UV GATE SENSE
LT4250L/LT4250H UV VUV VEE GATE
IRF530 0.1F
VUV VEE VSENSE
SENSE 10
1640 F01a 4250 F01b
Figure 1a. Test Circuit 1
Figure 1b. Test Circuit 2
TIMING DIAGRAMS
2V OV 0V tPHLOV GATE tPLHOV 1.255V 1.235V
1V
Figure 2. OV to GATE Timing
60mV
SENSE
tPHLSENSE GATE
1V
4250 F04a
Figure 4a. SENSE to GATE Timing
DRAIN
PWRGD
DRAIN
PWRGD VPWRGD - VDRAIN = 0V
Figure 5a. DRAIN to PWRGD/PWRGD Timing
6
W
UW
2V UV 0V
1.125V
1.255V
tPHLUV GATE
tPLHUV
1V
4250 F02
1V
1V
4250 F03
Figure 3. UV to GATE Timing
UV tPHLCB GATE
1V
1V
4250 F04b
Figure 4b. Current Limit to GATE Timing
VGATE - VGATE = 0
1.4V
GATE
1.4V
tPHLDL
PWRGD
tPHLGH
1V
1V
VEE
VGATE - VGATE = 0 GATE
VEE
1.4V
1.4V
tPHLDL
PWRGD
tPHLGH
1V
4250 F05a
VPWRGD - VDRAIN = 0
1V
4250 F05b
Figure 5b. GATE to PWRGD/PWRGD Timing
LT4250L/LT4250H
APPLICATIONS INFORMATION
Hot Circuit Insertion When circuit boards are inserted into a live - 48V backplane, the bypass capacitors at the input of the board's power module or switching power supply can draw huge transient currents as they charge up. The transient currents can cause permanent damage to the board's components and cause glitches on the system power supply. The LT4250 is designed to turn on a board's supply voltage in a controlled manner, allowing the board to be safely inserted or removed from a live backplane. The chip also provides undervoltage, overvoltage and overcurrent protection while keeping the power module off until its input voltage is stable and within tolerance. Power Supply Ramping The input to the power module on a board is controlled by placing an external N-channel pass transistor (Q1) in the power path (Figure 6a, all waveforms are with respect to the VEE pin of the LT4250). R1 provides current fault detection and R2 prevents high frequency oscillations. Resistors R4, R5 and R6 provide undervoltage and overvoltage sensing. By ramping the gate of Q1 up at a slow rate, the surge current charging load capacitors C3 and C4 can be limited to a safe value when the board makes connection. Resistor R3 and capacitor C2 act as a feedback network to accurately control the inrush current. The inrush current can be calculated with the following equation: IINRUSH = (45A * CL)/C2
GND GND R4 549k 1% UV = 38.5V R5 6.49k 1% R6 10k 1% 8 VDD 3 UV LT4250H 2 OV VEE 4 SENSE 5 GATE 6 C1 470nF 25V 4 2 Q1 IRF530 R3 1k, 5% R2 10 5% C2 15nF 100V
4250 F06a
(SHORT PIN) C3 0.1F 100V C4 + 100F 100V
PWRGD
1
OV = 71V
DRAIN 7
* 3 - 48V * DIODES INC. SMAT70A 1
R1 0.02 5%
Figure 6a. Inrush Control Circuitry
U
W
U
U
where CL is the total load capacitance, C3 + C4 + module input capacitance. Capacitor C1 and resistor R3 prevent Q1 from momentarily turning on when the power pins first make contact. Without C1 and R3, capacitor C2 would pull the gate of Q1 up to a voltage roughly equal to VEE * C2/CGS(Q1) before the LT4250 could power up and actively pull the gate low. By placing capacitor C1 in parallel with the gate capacitance of Q1 and isolating them from C2 using resistor R3 the problem is solved. The value of C1 is given by:
V - VTH C1 = INMAX * C 2 + C GD VTH
(
)
where VTH is the MOSFET's minimum gate threshold and VINMAX is the maximum operating input voltage. R3's value should not exceed a value that produces an R3 * C2 time-constant of 150s. A 1k value for R3 will ensure this for C2 values up to 150nF. The waveforms are shown in Figure 6b. When the power pins make contact, they bounce several times. While the contacts are bouncing, the LT4250 senses an undervoltage condition and the GATE is immediately pulled low when the power pins are disconnected. Once the power pins stop bouncing, the GATE pin starts to ramp up. When Q1 turns on, the GATE voltage is held constant by the feedback network of R3 and C2. When the DRAIN voltage has finished ramping, the GATE pin then ramps to its final value.
VICOR VI-J3D-CY VIN+ VOUT+ 5V
+
GATE IN VIN- VOUT-
C5 100F 16V
Figure 6b. Inrush Control Waveforms
7
LT4250L/LT4250H
APPLICATIONS INFORMATION
Current Limit/Electronic Circuit Breaker The LT4250 features a current limit function that protects against short circuits or excessive supply currents. If the current limit is active for more than 500s the electronic circuit breaker will trip. By placing a sense resistor between the VEE and SENSE pin, the current limit will be activated whenever the voltage across the sense resistor is greater than 50mV. Note that the current limit threshold should be set sufficiently high to account for the sum of the load current and the inrush current. If the load current is controlled by the PWRGD/PWRGD pin (as in Figure 6a), the threshold can be set lower, since it will never need to accommodate inrush current and load current simultaneously. In the case of a short circuit, the current limit activates and immediately pulls the GATE low, which servos the SENSE voltage to 50mV and starts a 500s timer. The MOSFET current is limited to 50mV/RSENSE (see Figure 7). If the short circuit persists for more than 500s, the circuit breaker trips and pulls the GATE pin low, shutting off the MOSFET. The circuit breaker is reset by pulling UV low, or by cycling power to the part. If the short circuit clears before the 500s timing interval the current limit will deactivate and release the GATE. The LT4250 guards against voltage steps on the input supply. A positive voltage step (increasing in magnitude) on the input supply creates a current step equal to I = CL * V/T. The resultant inrush current is proportional to the voltage slew rate. If the inrush exceeds 50mV/ RSENSE, the current limit will activate as shown in Figure 8. The GATE pin pulls low, limiting the current to 50mV/ RSENSE. At this level the MOSFET drain will not follow the source as the input voltage rapidly changes, but instead remains at the voltage stored on the load capacitance. The load capacitance begins to charge at a current of 50mV/ RSENSE, but not for long. As the drain charges the load capacitance, C2 pushes back on the gate and limits the MOSFET current in a manner identical to the initial startup condition which is less than the short circuit limiting value of 50mV/RSENSE. Thus the circuit breaker does not trip. To ensure correct operation under input voltage step conditions, RSENSE must be chosen to provide a current limit value greater than the sum of the load current and the dynamic current in the load capacitance. For C1 values less than 0.33F a positive voltage step on the input supply can result in the Q1 turning off momentarily which can shut down the output. By adding an additional resistor and diode, Q1 remains on during the voltage step. This is shown as D1 and R7 in Figure 9. The purpose of D1 is to shunt current around R7 when the power pins first make contact and allow C1 to hold the GATE low. The value of R7 should be sized to generate an R7 * C1 time constant of 33s. Under some conditions, a short circuit at the output can cause the input supply to dip below the UV threshold. The LT4250 turns off once and then turns on until the electronic circuit breaker is tripped. This can be minimized by adding a deglitching delay to the UV pin with a capacitor from UV to VEE. This capacitor forms an RC time constant with the resistors at UV, allowing the input supply to recover before the UV pin resets the circuit breaker. A circuit that automatically resets the circuit breaker after a current fault is shown in Figure 10. Transistors Q2 and Q3 along with R7, R8, C4 and D1 form a programmable one-shot circuit. Before a short occurs, the GATE pin is pulled high and Q3 is turned on, pulling node 2 to VEE. Resistor R8 turns off Q2. When a short occurs, the GATE pin is pulled low and Q3 turns off. Node 2 starts to charge C4 and Q2 turns on, pulling the UV pin low and resetting the circuit breaker. As soon as C4 is fully charged, R8 turns off Q2, UV goes high and the GATE starts to ramp up. Q3 turns back on and quickly pulls node 2 back to VEE. Diode D1 clamps node 3 one diode drop below VEE. The duty cycle is set to 10% to prevent Q1 from overheating.
DRAIN
GATE
ID (Q1)
Figure 7. Short-Circuit Protection Waveforms
8
U
W
U
U
LT4250L/LT4250H
APPLICATIONS INFORMATION
GND GND 8 R4 549k 1% R5 6.49k 1%
VEE AND DRAIN RELATIVE TO GND
ID(Q1)
5A
- 48V
Figure 8. Voltage Step on Input Supply Waveforms
* DIODES INC. SMAT70A
(SHORT PIN) GND GND R7 1M 5% C4 1F 100V R4 549k 1% R5 6.49k 1% R6 10k 1% 3 Q3 ZVN3310 D1 1N4148 - 48V * DIODES INC. SMAT70A R8 510k 5% R1 0.02 5% 1 2 8 VDD 3 UV LT4250L 2 OV VEE 4 SENSE 5 GATE 6 R2 10 5% R3 1k, 5% C2 15nF 100V
4250 F09a
2
Q2 2N2222
*
Figure 10. Automatic Restart After Current Fault
U
*
W
U
U
(SHORT PIN)
VDD 3 UV LT4250H 2 OV VEE 4 SENSE 5 GATE 6 R3 1k 5% R2 10 5% C2 3.3nF 100V DRAIN 7 PWRGD 1
C3 0.1F 100V
+
R6 10k 1%
C4 22F 100V
R7 220 5% R1 0.02 5% 1 2
D1 BAT85 C1 150nF 25V
3
4
Q1 IRF530
4250 F08a
Figure 9. Circuit for Input Steps with Small C1
PWRGD
1
+
DRAIN 7
C3 100F 100V
C1 470nF 25V 4
3
Q1 IRF530
9
LT4250L/LT4250H
APPLICATIONS INFORMATION
Undervoltage and Overvoltage Detection The UV (Pin 3) and OV (Pin 2) pins can be used to detect undervoltage and overvoltage conditions at the power supply input. The UV and OV pins are internally connected to analog comparators with 130mV and 20mV of hysteresis respectively. When the UV pin falls below its threshold or the OV pin rises above its threshold, the GATE pin is immediately pulled low. The GATE pin will be held low until UV is high and OV is low. The undervoltage and overvoltage trip voltages can be programmed using a three resistor divider as shown in Figure 11. With R4 = 549k, R5 = 6.49k and R6 = 10K, the undervoltage threshold is set to 38.5V (with a 43V release from undervoltage) and the overvoltage threshold is set to 71V. The resistor divider will also gain up the hysteresis at the UV pin and OV pin to 4.5V and 1.2V at the input respectively. PWRGD/PWRGD Output The PWRGD/PWRGD output can be used to directly enable a power module when the input voltage to the module is within tolerance. The LT4250L has a PWRGD output for modules with an active low enable input, and the LT4250H has a PWRGD output for modules with an active high enable input. When the DRAIN voltage of the LT4250H is high with respect to VEE (Figure 12) or the GATE voltage is low, the internal transistor Q3 is turned off and I1 and Q2 clamp the PWRGD pin one SAT drop ( 0.3V) above the DRAIN pin. Transistor Q2 sinks the module's pull-up current and the module turns off. When the DRAIN voltage drops below VDL and the GATE voltage is high, Q3 will turn on, shorting the bottom of I1 to DRAIN and turning Q2 off. The pull-up current in the module pulls the PWRGD pin high and enables the module. When the DRAIN voltage of the LT4250L is high with respect to VEE or the GATE voltage is low, the internal pulldown transistor Q2 is off and the PWRGD pin is in a high impedance state (Figure 13). The PWRGD pin will be pulled high by the module's internal pull-up current source, turning the module off. When the DRAIN voltage drops below VDL and the GATE voltage is high, Q2 will turn on and the PWRGD pin will pull low, enabling the module. The PWRGD signal can also be used to turn on an LED or optoisolator to indicate that the power is good as shown in Figure 14. Gate Pin Voltage Regulation When the supply voltage to the chip is more than 20V, the GATE pin voltage is regulated at 13.5V above VEE. The gate voltage will be no greater than 18V for supply voltages up to 80V.
(SHORT PIN) GND GND
GND GND 8 (SHORT PIN)
VUV = 1.255
VOV = 1.255
( (
R4 + R5+ R6 R5 + R6 R4 + R5+ R6 R6
) )
R4 3 R5 2 R6 UV
VDD
LT4250L/LT4250H OV VEE 4
- 48V
4250 F10
Figure 11. Undervoltage and Overvoltage Sensing Figure 12. Active High Enable Module
10
U
W
U
U
ACTIVE HIGH ENABLE MODULE 8 VIN+ VOUT+ PWRGD 1
R4 3 R5 2 R6
LT4250H GATE UV + -
VDD I1
+
Q2 Q3 C3
ON/OFF
OV
- VGH + + -
+ VDL - SENSE 5 GATE 6 C1 R2 R3 C2 VEE DRAIN 7 VIN- VOUT-
VGATE VEE 4 *
3 - 48V * DIODES INC. SMAT70A 1
R1 2
4
4250 F11
Q1
LT4250L/LT4250H
APPLICATIONS INFORMATION
(SHORT PIN) GND GND 8 R4 3 R5 2 OV R6 LT4250L GATE UV - + Q2 C3 VDD PWRGD 1 ACTIVE LOW ENABLE MODULE VIN+ VOUT+
+
- VGH + + -
+ VDL VEE - SENSE 5 GATE 6
VEE DRAIN 7
VGATE
4 *
C1 3 - 48V * DIODES INC. SMAT70A 1 R1 2 4 Q1
R2
R3
C2
4250 F12
Figure 13. Active Low Enable Module
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted. N8 Package 8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.400* (10.160) MAX 8 7 6 5
0.300 - 0.325 (7.620 - 8.255)
0.045 - 0.065 (1.143 - 1.651)
0.009 - 0.015 (0.229 - 0.381)
0.065 (1.651) TYP 0.125 (3.175) 0.020 MIN (0.508) MIN 0.018 0.003 (0.457 0.076)
(
+0.035 0.325 -0.015 8.255 +0.889 -0.381
)
0.100 (2.54) BSC
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
S8 Package 8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 - 0.197* (4.801 - 5.004) 0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254) 0- 8 TYP 0.053 - 0.069 (1.346 - 1.752) 8 0.004 - 0.010 (0.101 - 0.254) 0.228 - 0.244 (5.791 - 6.197) 0.150 - 0.157** (3.810 - 3.988) 7 6 5
0.014 - 0.019 (0.355 - 0.483) TYP *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.016 - 0.050 (0.406 - 1.270)
U
U
W
U
U
(SHORT PIN) GND GND R4 549k 1% 8 VDD 3 UV LT4250L 2 OV VEE 4 SENSE 5 C1 150nF 25V 4 2 Q1 IRF530 GATE 6 R2 10 5% R3 1k, 5% C2 3.3nF 100V DRAIN 7 PWRGD 1
PWRGD R7 51k 5%
ON/OFF
R5 6.49k 1%
VIN- VOUT-
4N25
R6 10k 1%
* R1 0.02 5%
C3 + 100F 100V
3 - 48V
1 * DIODES INC. SMAT70A
4250 F13
Figure 14. Using PWRGD to Drive an Optoisolator
0.130 0.005 (3.302 0.127)
0.255 0.015* (6.477 0.381)
1
2
3
4
N8 1098
0.050 (1.270) BSC
SO8 1298
1
2
3
4
11
LT4250L/LT4250H
TYPICAL APPLICATION
Using an EMI Filter Module Many applications place an EMI filter module in the power path to prevent switching noise of the module from being injected back onto the power supply. A typical application
GND GND (SHORT PIN) R7 51k 5% 8 VDD R4 549k 1% R5 6.49k 1% R6 10k 1% * 3 - 48V * DIODES INC. SMAT70A 1 PWRGD 3 UV DRAIN LT4250L 2 OV VEE 4 R1 0.02 5% 2 GATE SENSE 5 4 Q1 IRF530 C1 470nF 25V 6 1 7 C2 15nF 100V C3 0.1F 100V LUCENT JW050A1-E 1 2 C4 0.1F 100V VIN+ ON/OFF VOUT+ SENSE + TRIM SENSE - VIN- 3
4250 F14
RELATED PARTS
PART NUMBER LTC 1421 LTC1422 LT1640H/LT1640L LT1641 LTC1642 LTC1643 LTC1645 LTC1646 LTC1647
(R)
DESCRIPTION Dual Hot Swap Controller with Additional -12V Control Hot Swap Controller in SO-8 -48V Hot Swap Controller in SO-8 48V Hot Swap Controller in SO-8 Fault Protected Hot Swap Controller PCI Hot Swap Controller Dual Hot Swap Controller Dual CompactPCI Hot Swap Controller Dual Hot Swap Controller
12
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
U
using the Lucent FLTR100V10 filter module is shown in Figure 15. When using a filter, an optoisolator is required to prevent common mode transients from destroying the PWRGD and ON/OFF pins.
4N25
9 8 7
5V
VIN+ R3 1k 5% R2 10 5%
VOUT+
+
LUCENT FLTR100V10 VIN- VOUT-
+
C5 100F 100V
C6 0.1F 100V 4
C7 100F 16V
6 5
VOUT- CASE
CASE
Figure 15. Typical Application Using a Filter Module
COMMENTS Operates from 3V to 12V System Reset Output with Programmable Delay LT4250 is a Pin-Compatible Upgrade to LT1640 Foldback Analog Current Limit, Operates from 9V to 80V Operates Up to 16.5V, Protected to 33V 3.3V, 5V, 12V, - 12V Supplies for PCI Bus Operates from 1.2V to 12V, Power Sequencing 3.3V, 5V Supplies with Precharge and Local PCI Reset Logic Dual ON Pins for Supplies from 3V to 15V
4250lhi LT/TP 0401 2K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 2001

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