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MITSUBISHI
M62353AGP
8BIT 8CH D-A CONVERTER WITH BUFFER AMPLIFIERS
DESCRIPTION M62353A is a CMOS structured semiconductor integrated ciruict integrating 8 channels of built-in D-A converters with high performance buffer operational amplifier for each channel output. 3-wire serial interface (DI,CLK,LD) method is used for the taransfer format of digital data to allow connection with microcomputer with minimum wiring Do terminal is provided to allow cascading serial use. Built-in buffer operational amplifiers are designed to operate or full-swing in the whole voltage range from Vcc to GND for each input/output. And their higher stability for capacitive load perfectly fits in to the use for electronic volume (VCA) or the replacement for semi-variable resistor for tuning. FEATURES 12 bit serial data input (3 wire serial data transfer method, DI, CLK, LD) Corresponds to TTL input for digital input (VINH 2V, VINL 0.8V) R-2R+ segment method high performance 8 channel 8 bit D-A converters 8ch buffer operational amplifiers opperating in the whole voltage range from Vcc to GND Buffer operational amplifiers with high oscillation stability for capacitive load APPLICATION Adjustment or control of industrial or home-use electronic equipments such as VTR camera, VTR set, TV, and CRT display.
Vss
(VrefL)
Pin configuration(Top View)
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
GND AO1 DI CLK LD DO AO8 Vcc
AO2 AO3 AO4 AO5 AO6 AO7 VDD
(VrefU)
Outline 16P2E-A
GND
16
AO1
15
DI
14
CLK
13
LD
12
DO
11
AO8
10
VCC
9
D0 1 2 3 4 5 6 D7 D8 9 10 D11
8bit R-2R+ segment D-A converter
8
D-A
(8)
Ch1
L
..... .....
(8)
(8)
(8)
L
Ch2
8bit R-2R+ segment D-A converter
L
4 5
L
6
L
7
L D-A
3
D-A
D-A
D-A
D-A
Buffer Amp.
1 2 3 4 5 6 7 8
Vss (VrefL)
AO2
AO3
AO4
AO5 ( 1 / 6)
AO6
AO7
VDD (VrefU)
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MITSUBISHI
M62353AGP
8BIT 8CH D-A CONVERTER WITH BUFFER AMPLIFIERS
EXPLANATION OF TERMINALS
Pin No.
14 11 13 12 15 2 3 4 5 6 7 10 9 16 8 1
symbol DI DO CLK LD AO1 AO2 AO3 AO4 AO5 AO6 AO7 AO8 VCC GND VDD VSS
Function Serial data input terminal. 12bit serial data is input to this terminal. Serial data output terminal. Serial data of 12bit shift register is output from this terminal. Serial clock input terminal.Input signal from DI terminal is input to 12bit shift register upon the rise Data is loaded to register when 'H' is input to LD terminal.
8bit D-A converter output terminal. Built-in buffer amp.is connected to VCC. D-A converted voltage between VDD and VSS is output to each terminal. Power supply terminal. Digital and Analog common GND D-A converter High level reference voltage input terminal. D-A converter Low level reference voltage input terminal.
BLOCK DIAGRAM FOR EXPLANATION OF TERMINALS
VCC
9
GND
16
DI CLK
14 13
12 BIT SHIFT REGISTER
D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 D 9 D10 D11
11
DO
DECODER (8) (8)
123 456 78
12
LD
D 0
8bit Latch
D 7
D 0
D 7
8bit Latch 8bit R-2R + segment D-A converter
8bit R-2R + segment D-A converter
A 1
A 8
8
15
10
1
VDD
AO1
AO8
VSS
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MITSUBISHI
M62353AGP
8BIT 8CH D-A CONVERTER WITH BUFFER AMPLIFIERS
DIGITAL DATA FORMAT
Last LSB First MSB
D0
D1
D2 D3 D4 DAC DATA
D5
D6
D7
D8
D9
D10 D11
DAC DATA
D0 0 1 0 1 : 0 1 D1 D2 0 0 1 1 : 1 1 0 0 0 0 : 1 1 D3 0 0 0 0 : 1 1 D4 0 0 0 0 : 1 1 D5 0 0 0 0 : 1 1 D6 0 0 0 1 : 1 1 : 1 1 D7 0 0 0 0
DAC SELECT DATA
D-A output (VrefU-VrefL)/256x1+VrefL[V] (VrefU-VrefL)/256x2+VrefL[V] (VrefU-VrefL)/256x3+VrefL[V] (VrefU-VrefL)/256x4+VrefL[V] : (VrefU-VrefL)/256x255+VrefL[V] VrefU[V] (255LSB) (256LSB)
VrefU=VDD VrefL=VSS
(1LSB) (2LSB) (3LSB) (3LSB)
DAC SELECT DATA D8 D9 D10 D11
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DAC SELECTION Don't Care A01select A02select A03select A04select A05select A06select A07select A08select Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care
TIMING CHART (model)
CLK
SI
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
LD
AO1~ AO8
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MITSUBISHI
M62353AGP
8BIT 8CH D-A CONVERTER WITH BUFFER AMPLIFIERS
ABSOLUTE MAXMUM RATING
Symbol Vcc VDD V IN Vout Pd Topr Tstg Parameter Supply voltage D-A converter High levelreference voltage Digital input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions Ratings - 0.3 ~ 7.0 - 0.3 ~ 7.0
- 0.3 ~ V CC +0.3 - 0.3 ~ V CC +0.3
Unit V V V V m W C C
150 - 20 ~ 85 - 40 ~ 125
ELECTRIC CHARACTERISTICS (VCC, VrefU=5V 10% , VCC VrefU, GND, VrefL=0.0V, Ta=-20 ~ + 85C unless otherwise specified.)
Symbol Vcc Icc IILK VIL VIH VOL VOH Parameter Supply voltage Supply current Input leak current
Digital input Low voltage Digital input High voltage Digital output Low voltage Digital output High voltage IOL = 2.5mA IOH = - 400 A CLK=1MHz Operation
V CC =5V, IAO =0 A
Ratings Conditions MIN 4.5 TYP 5.0 1.0 -10 2.0 0.4 VCC-0.4 MAX 5.5 2.5 10 0.8 Unit V m A A V V V V
VIN =0 ~ V CC
Note2: Typical value is for Ta=25C Note3: Changes from M62353GP: Digital input voltage corresponds to TTL spec. Symbol
IrefU VDD (V refU ) VSS (V refL ) (VCC, VrefU=5V 10% , VCC VrefU, GND, VrefL=0.0V, Ta=-20 ~ + 85C unless otherwise specified.)
Parameter Reference voltage pin current D-A converter High level reference voltage range D-A converter Low level reference voltage range Buffer amplifier output drive range Buffer amplifier output drive range
Conditions
VrefU =5V,VrefL =0V,IAO =0 A
Data condition: at Maxmum Current
The output does not necessarily be the Values within the reference voltage setting range.The output value is determined by the buffer amplifier output voltage range(VAO).
Ratings MIN TYP 0.9 3.5 GND 0.1 0.2 -1 -1.0 -1.5 -2.0 -2.0 MAX 1.7
VCC
Unit m A
V
VCC - 3.5 VCC -0.1 VCC -0.2
IAO = 100 A IAO = 500 A Upper side saturation voltage=0.3V Lower side saturation voltage=0.2V VrefU = 4.79V VrefL = 0.95V (15mV/LSB) VCC = 5.5V without load(I AO =+0 A)
VAO
V
IAO
1 1.0 1.5 2.0 2.0 0.1 5
m A
SDL SL
Differential nonlinearity Nonlinearity Zero code error Full scale error Output capacitative load
Buffer Amp. output impedance
LSB LSB LSB LSB F
Szero
SFULL
Co Ro
ohm
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MITSUBISHI
M62353AGP
8BIT 8CH D-A CONVERTER WITH BUFFER AMPLIFIERS
Symbol
tCKL tCKH tCR tCF tDCH tCHD tCHL tLDC tLDH tDO tLDD
(VCC, VrefU=5V 10% , VCC VrefU, GND, VrefL=0.0V, Ta=-20 ~ + 85C unless otherwise specified.)
Parameter Clock "L" pulse width Clock "H" pulse width Clock rise time Clock fall time Data setup time Data hold time LD setup time LD hold time LD "H"hold time
Data output delay time D-A output settling time
Ratings Conditions MIN 200 200 200 30 60 200 100 100
CL 100pF CL 100pF,VAO:0.5
The time until the output becomes the final value of 1/2 LSB
TYP
MAX
Unit ns ns ns ns ns ns ns ns
70
4.5V
350 300
ns s
Measurement circuit
DUT
input
output CL<100pF
=
TIMING CHART
tCR tCKH tCF tCHL
CLK
tCKL tLDC
DI
tDCH tCHD tCHL tLDH
LD
tLDD
AO1 ~ AO8 output
tDO
t DO
DO output
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MITSUBISHI
M62353AGP
8BIT 8CH D-A CONVERTER WITH BUFFER AMPLIFIERS
TYPICAL APPLICATION
9
8
VCC
VDD(VrefU)
AO1
14 13
15 2 3 4 5 6 7 10
DI CLK LD DO
AO2 AO3 AO4 AO5 AO6 AO7 AO8
MCU
12 11
GND
16
VSS(VrefL)
1
Note: M62353AGP has 3 terminals(VDD, VCC, and VSS) to which constant voltage is to be applied. Ripple voltage or spike noise to these terminals may worsen converting precision or cause erroneous operations. So be sure to use this device by putting cacpacitor between each terminal and GND to get D-A conversion operation stabilized. Output buffer amplifiers have high oscillation stability against capacitive load. This means that jitters by wirings around output terminals or capcitor between output and GND(0.1uF max.) do not cause any problems with DAC operations. Connect capacitor(0.1uF or around) between output and GND for protection from spark discharge when this device is used under such high electric field as that for instance of instruments with cathode ray tube.
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