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| MITSUMI System Reset PST591~595 System Reset Monolithic IC PST591~595 Series Outline These ICs function in a variety of CPU systems and other logic systems, to detect power supply voltage and reset the system accurately when power is turned on or interrupted, and has a built-in fixed delay time generating circuit. This series has been represented in the past by PST574/PST575, but these new low reset type system reset ICs expand the delay time series with a counter timer using an analog/digital hybrid circuit. Features 1. Fixed delay time setting by counter timer Excellent delay time temperature characteristics 2. Low operating limit voltage 3. Hysteresis voltage provided in detection voltage 4. Current consumption for no-load 5. 5 delay time products available 800ppm/C 0.65V typ. 50mV typ. ICCL=300A typ. ICCH=200A typ. PST591 50mS PST592 100mS PST593 200mS C : 4.5V typ. D : 4.2V typ. E : 3.9V typ. F : 3.6V typ. G : 3.3V typ. PST594 400mS PST595 800mS H : 3.1V typ. I : 2.9V typ. J : 2.7V typ. K : 2.5V typ. 6. Each product has 9 detection voltage ranks. Package MMP-4A (PST59 M) TO-92A (PST59 ) contains detection voltage rank. (MMP-4A has a manual reset pin, which should be set at GND or NC during normal operation.) * Applications 1. Reset circuits in microcomputers, CPUs and MPUs 2. Logic circuit reset circuits. 3. Battery voltage check circuits. 4. Back-up power supply switching circuits. 5. Level detection circuits. 6. Mechanical reset circuits MITSUMI System Reset PST591~595 Pin Assignment 1 1 2 3 VCC GND VOUT 1 2 3 4 1 2 3 MMP-4A 4 3 2 VOUT Manual Reset VCC GND TO-92A Equivalent Circuit Diagram Absolute Maximum Ratings Item Storage temperature Operating temperature Power supply voltage (Ta=25C) Symbol TSTG TOPR VCC max. VRES max. Pd Rating -40~+125 -20~+75 -0.3~10 -0.3~10 200 (MMP-4P) 300 (TO-92) Units C C V V mW Manual reset input voltage Allowable loss MITSUMI System Reset PST591~595 Electrical Characteristics Item (Ta=25C) (Except where noted otherwise, resistance unit is) Measurement conditions C D E RL=470 F < 0.4V VOL = G H VCC=H L I J K RL=470, VCC=L H L RL=470, Ta=-20C~+75C VCC=Vs min.-0.05V, RL=470 VCC=10V VCC=Vs min.-0.05V, RL= VCC=Vs typ./0.85V, RL= PST591 PST592 RL=4.7k PST593 CL=100PF 1 PST594 PST595 RL=4.7k, CL=100PF 1 RL=4.7k, VOL < 0.4V = VCC=VS min.-0.05V, RL=0 Ta=-20C~+75C, RL=0 2 Min. 4.3 4.0 3.7 3.4 3.1 2.9 2.75 2.55 2.35 30 Typ. 4.5 4.2 3.9 3.6 3.3 3.1 2.90 2.70 2.50 50 0.01 0.1 0.4 0.1 600 350 75 150 300 600 1200 Max. Unit 4.7 4.4 4.1 3.8 3.5 V 3.3 3.05 2.85 2.65 100 mV %/C V A A A Symbol Measuring circuit Detection voltage VS 1 Hysteresis voltage Detection voltage temperature coefficient Low-level output voltage Output leakage current Circuit current while on Circuit current while off VS VS/ T VOL IOH ICCL ICCH 1 1 1 1 1 1 "H" transport delay time tPLH 2 * "L" transport delay time Operating power supply voltage Output current while on 1 Output current while on 2 Manual Input high voltage reset Input high current pin Input low voltage tPHL VOPL IOL1 IOL2 VRESH VRESH VRESL 2 1 1 1 * * VRES=2V 300 200 30 50 60 100 120 200 mS 240 400 480 800 10 S 0.65 0.85 V 8 mA 6 mA 2.0 V 80 A 0.8 V *1 tpLH : VCC= (VS typ.-0.4V) *2 VCC=VS min.-0.15V Measuring Circuit [1] (VS typ.+0.4V), tpHL : VCC= (VS typ.+0.4V) (VS typ.-0.4V) Note 3: VOUT pin is low when manual reset pin is high. VOUT pin is high when manual reset pin is low. [2] Note: Input model is an example for PST591C. MITSUMI System Reset PST591~595 Characteristics VCC vs. VOUT 8 7 6 5 4 3 2 1 0 0 (Example: PST591D) VS vs. Ta 4.4 4.3 VOUT (V) Ta=-25C Ta=25C Ta=75C 1 2 3 4 5 6 7 8 VS (V) 4.2 4.1 4.0 3.9 -40 -20 0 20 40 60 80 VCC (V) Ta (C) VS vs. Ta 90 80 70 VOL vs. Ta 250 200 150 100 50 0 VS 60 (mV) 50 40 30 -40 -20 0 20 40 60 80 VOL (mV) -40 -20 0 20 40 60 80 Ta (C) Ta (C) ICCL vs. Ta 450 400 350 300 250 200 -40 -20 0 20 40 60 80 ICCH vs. Ta 230 220 ICCL (A) ICCH (A) 210 200 190 180 -40 -20 0 20 40 60 80 Ta(C) Ta (C) IOL vs. Ta 40 35 tPLH vs. Ta 53 52 51 50 49 48 -20 0 20 40 60 80 -40 -20 0 20 40 60 80 IOL 30 (mA) 25 20 15 -40 tPLH (mS) Ta (C) Ta (C) MITSUMI System Reset PST591~595 tPHL vs. Ta 12 11 Pd vs. Ta 300 200 TO92 100 MMP4 0 tPHL (S) 10 9 8 7 -40 -20 0 20 40 60 80 Pd (mW) 0 25 50 75 100 125 Ta (C) Ta (C) Timing Chart 7 6 5 4 VCC/VOUT 3 (V) 2 1 0 VCC VS VOUT Time Undefined RESET ON OFF Application circuits 1. Normal hard reset Note: Connect a capacitor between IC VCC and GND pins if VCC line impedance is high. MITSUMI 2. Manual reset System Reset PST591~595 VOUT pin low for manual switch ON. VOUT pin high for manual switch OFF. Note: Connect a capacitor between IC VCC and GND pins if VCC line impedance is high. 3. Mute circuit Note: Connect a capacitor between IC VCC and GND pins if VCC line impedance is high. |
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