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| W29C022 256K x 8 CMOS FLASH MEMORY GENERAL DESCRIPTION The W29C022 is a 2-megabit, 5-volt only CMOS flash memory organized as 256K x 8 bits. The device can be written (erased and programmed) in-system with a standard 5V power supply. A 12-volt VPP is not required. The unique cell architecture of the W29C022 results in fast write (erase/ program) operations with extremely low current consumption compared to other comparable 5-volt flash memory products. The device can also be written (erased and programmed) by using standard EPROM programmers. FEATURES * * Single 5-volt write (erase and program) operations Fast page-write operations - 128 bytes per page - Page write (erase/program) cycle: 10 mS (max.) - Effective byte-write (erase/program) cycle time: 39 S - Optional software-protected data write * * Software and hardware data protection Low power consumption - Active current: 25 mA (typ.) - Standby current: 20 A (typ.) * * Automatic write (erase/program) timing with internal VPP generation End of write (erase/program) detection - Toggle bit - Data polling * * * * Fast chip-erase operation: 50 mS Two 8 KB boot blocks with lockout Typical page write (erase/program) cycles: 1K Ten-year data retention * * * Latched address and data All inputs and outputs directly TTL compatible JEDEC standard byte-wide pinouts -1- Publication Release Date: March 26, 2002 Revision A3 W29C022 PIN CONFIGURATIONS BLOCK DIAGRAM NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 VDD #WE A17 A14 A13 A8 A9 A11 #OE A10 #CE DQ7 DQ6 DQ5 DQ4 DQ3 VDD VSS #CE #OE #WE CONTROL OUTPUT BUFFER DQ0 . . DQ7 32-pin DIP 26 25 24 23 22 21 20 19 18 17 A0 . . . A17 DECODER 8K Byte Boot Block (Optional) A 1 2 4 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13 A 1 5 3 A 1 6 2 N C 1 V D D # W E A 1 7 CORE ARRAY 8K Byte Boot Block (Optional) 32 31 30 29 28 27 A14 A13 A8 A9 A11 #OE A10 #CE DQ7 32-pin PLCC 26 25 24 23 22 21 14 15 16 17 18 19 20 PIN DESCRIPTION SYMBOL 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 D Q 1 D D QV Q 2 ss 3 D Q 4 D Q 5 D Q 6 PIN NAME Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Power Supply Ground No Connection A11 A9 A8 A13 A14 A17 #WE VDD NC A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 #OE A10 #CE DQ7 DQ6 DQ5 DQ4 DQ3 Vss DQ2 DQ1 DQ0 A0 A1 A2 A 3 A0 - A17 DQ0 - DQ7 #CE #OE #WE VDD Vss NC 32-pin TSOP -2- W29C022 FUNCTIONAL DESCRIPTION Read Mode The read operation of the W29C022 is controlled by #CE and #OE, both of which have to be low for the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip is de-selected and only standby power will be consumed. #OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either #CE or #OE is high. Refer to the read cycle timing waveforms for further details. Page Write Mode The W29C022 is written (erased/programmed) on a page basis. Every page contains 128 bytes of data. If a byte of data within a page is to be changed, data for the entire page must be loaded into the device. Any byte that is not loaded will be erased to "FF hex" during the write operation of the page. The write operation is initiated by forcing #CE and #WE low and #OE high. The write procedure consists of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the device. Step 2 is an internal write (erase/program) cycle, during which the data in the page buffers are simultaneously written into the memory array for non-volatile storage. During the byte-load cycle, the addresses are latched by the falling edge of either #CE or #WE, whichever occurs last. The data are latched by the rising edge of either #CE or #WE, whichever occurs first. If the host loads a second byte into the page buffer within a byte-load cycle time (TBLC) of 200 S after the initial byte-load cycle, the W29C022 will stay in the page load cycle. Additional bytes can then be loaded consecutively. The page load cycle will be terminated and the internal write (erase/program) cycle will start if no additional byte is loaded into the page buffer A7 to A17 specify the page address. All bytes that are loaded into the page buffer must have the same page address. A0 to A6 specify the byte address within the page. The bytes may be loaded in any order; sequential loading is not required. In the internal write cycle, all data in the page buffers, i.e., 128 bytes of data, are written simultaneously into the memory array. Before the completion of the internal write cycle, the host is free to perform other tasks such as fetching data from other locations in the system to prepare to write the next page. Software-protected Data Write The device provides a JEDEC-approved optional software-protected data write. Once this scheme is enabled, any write operation requires a three-byte command sequence (with specific data to a specific address) to be performed before the data load operation. The three-byte load command sequence begins the page load cycle, without which the write operation will not be activated. This write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by noise during system power-up and power-down. The W29C022 is shipped with the software data protection disabled. To enable the software data protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The device will then enter the software data protection mode, and any subsequent write operation must be preceded by the three-byte command sequence cycle. Once enabled, the software data protection will remain enabled unless the disable commands are issued. A power transition will not reset the software data protection feature. To reset the device to unprotected mode, a six-byte command sequence is required. For information about specific codes, see the Command Codes for Software Data Protection in the Table of Operating Modes. For information about timing waveforms, see the timing diagrams below. Publication Release Date: March 26, 2002 Revision A3 -3- W29C022 Hardware Data Protection The integrity of the data stored in the W29C022 is also hardware protected in the following ways: (1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle. (2) VDD Power Up/Down Detection: The write and read operation are inhibited when VDD is less than 2.5V. (3) Write Inhibit Mode: Forcing #OE low, #CE high, or #WE high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. (4) VDD power-on delay: When VDD reaches its sense level, the device will automatically timeout for 5 mS before any write (erase/program) operation. Chip Erase Modes The entire device can be erased by using a six-byte software command code. See the Software Chip Erase Timing Diagram. Boot Block Operation There are two boot blocks (8K bytes each) in this device, which can be used to store boot code. One of them is located in the first 8K bytes and the other is located in the last 8K bytes of the memory. The first 8K or last 8K of the memory can be set as a boot block by using a seven-byte command sequence. See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the data for the designated block cannot be erased or programmed (programming lockout); other memory locations can be changed by the regular programming method. Once the boot block programming lockout feature is activated, the chip erase function will be disabled. In order to detect whether the boot block feature is set on the two 8K blocks, users can perform a six-byte command sequence: enter the product identification mode (see Command Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address "00002 hex" (for the first 8K bytes) or "3FFF2 hex" (for the last 8K bytes). If the output data is "FF hex," the boot block programming lockout feature is activated; if the output data is "FE hex," the lockout feature is deactivated and the block can be programmed. To return to normal operation, perform a three-byte command sequence to exit the identification mode. For the specific code, see Command Codes for Identification/Boot Block Lockout Detection. Data Polling (DQ7)- Write Status Detection The W29C022 includes a data polling feature to indicate the end of a write cycle. When the W29C022 is in the internal write cycle, any attempt to read DQ7 from the last byte loaded during the page/byteload cycle will receive the complement of the true data. Once the write cycle is completed. DQ7 will show the true data. See the #DATA Polling Timing Diagram. -4- W29C022 Toggle Bit (DQ6)- Write Status Detection In addition to data polling, the W29C022 provides another method for determining the end of a write cycle. During the internal write cycle, any consecutive attempts to read DQ6 will produce alternating 0's and 1's. When the write cycle is completed, this toggling between 0's and 1's will stop. The device is then ready for the next operation. See Toggle Bit Timing Diagram. Product Identification The product ID operation outputs the manufacturer code and device code. The programming equipment automatically matches the device with its proper erase and programming algorithms. The manufacturer and device codes can be accessed through software or by hardware operation. In the software access mode, a six-byte command sequence can be used to access the product ID. A read from address "00000 hex" outputs the manufacturer code "DA hex." A read from address "00001 hex" outputs the device code "45 hex." The product ID operation can be terminated by a three-byte command sequence. In the hardware access mode, access to the product ID is activated by forcing #CE and #OE low, #WE high, and raising A9 to 12 volts. TABLE OF OPERATING MODES Operating Mode Selection Operating Range: 0 to 70 C (Ambient Temperature), VDD = 5V 10 %, VSS = 0V, VHH = 12V MODE #CE Read Write Standby Write Inhibit Output Disable 5-Volt Software Chip Erase Product ID VIL VIL VIH X X X VIL VIL VIL #OE #WE VIL VIH X VIL X VIH VIH VIL VIL VIH VIL X X VIH X VIL VIH VIH AIN AIN X X X X AIN PINS ADDRESS Dout Din High Z High Z/DOUT High Z/DOUT High Z DIN Manufacturer Code DA (Hex) DQ. A0 = VIL; A1 - A17 = VIL; A9 = VHH A0 = VIH; A1 - A17 = VIL; Device Code 45 (Hex) A9 = VHH -5- Publication Release Date: March 26, 2002 Revision A3 W29C022 Command Codes for Software Data Protection BYTE SEQUENCE 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write TO ENABLE PROTECTION ADDRESS 5555H 2AAAH 5555H DATA AAH 55H A0H TO DISABLE PROTECTION ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H DATA AAH 55H 80H AAH 55H 20H Software Data Protection Acquisition Flow Software Data Protection Enable Flow Load data AA to address 5555 Software Data Protection Disable Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 55 to address 2AAA Load data A0 to address 5555 Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 20 to address 5555 Notes for software program code: Data Format: DQ7 - DQ0 (Hex) Address Format: A14 - A0 (Hex) -6- W29C022 Command Codes for Software Chip Erase BYTE SEQUENCE 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H DATA AAH 55H 80H AAH 55H 10H Software Chip Erase Acquisition Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 10 to address 5555 Notes for software chip erase: Data Format: DQ7 - DQ0 (Hex) Address Format: A14 - A0 (Hex) -7- Publication Release Date: March 26, 2002 Revision A3 W29C022 Command Codes for Product Identification and Boot Block Lockout Detection BYTE SEQUENCE ALTERNATE PRODUCT (7) IDENTIFICATION/BOOT BLOCK LOCKOUT DETECTION ENTRY ADDRESS 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write 5555 2AAA 5555 Pause 10 mS DATA AA 55 90 SOFTWARE PRODUCT IDENTIFICATION/BOOT BLOCK LOCKOUT DETECTION ENTRY ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H Pause 10 mS DATA AAH 55H 80H AAH 55H 60H SOFTWARE PRODUCT IDENTIFICATION/BOOT BLOCK LOCKOUT DETECTION EXIT ADDRESS 5555H 2AAAH 5555H Pause 10 mS DATA AAH 55H F0H - Software Product Identification and Boot Block Lockout Detection Acquisition Flow Product Identification Entry (1) Load data AA to address 5555 (2) Read address = 00000 data = DA Product Identification and Boot Block Lockout Detection Mode (3) Product Identification Exit (1) Load data 55 to address 2AAA Load data AA to address 5555 Load data 80 to address 5555 (2) Read address = 00001 data = 45 Load data 55 to address 2AAA Load data AA to address 5555 (4) Read address = 00002 data = FF/FE Load data F0 to address 5555 Load data 55 to address 2AAA (5) Read address = 3FFF2 data = FF/FE Pause 10 mS Load data 60 to address 5555 (6) Normal Mode Pause 10 mS Notes for software product identification/boot block lockout detection: (1) Data Format: DQ7-DQ0 (Hex); Address Format: A14-A0 (Hex) (2) A1-A16 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification and boot block (address 0002 Hex/3FFF2 Hex respond to first 8K/last 8K) lockout detection mode if power down. (4), (5) If the output data is "FF Hex," the boot block programming lockout feature is activated; if the output data "FE Hex," the lockout feature is inactivated and the block can be programmed. (6) The device returns to standard operation mode. (7) This product supports both the JEDEC standard 3 byte command code sequence and original 6 byte command code sequence. For new designs, Winbond recommends that the 3 byte command code sequence be used. -8- W29C022 Command Codes for Boot Block Lockout Enable BYTE SEQUENCE BOOT BLOCK LOCKOUT FEATURE SET ON FIRST 8K ADDRESS BOOT BLOCK ADDRESS 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write 6 Write 5555H 2AAAH 5555H 5555H 2AAAH 5555H 00000H Pause 10 mS DATA AAH 55H 80H AAH 55H 40H 00H BOOT BLOCK LOCKOUT FEATURE SET ON LAST 8K ADDRESS BOOT BLOCK ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H 3FFFFH Pause 10 mS DATA AAH 55H 80H AAH 55H 40H FFH Boot Block Lockout Enable Acquisition Flow Boot Block Lockout Feature Set on First 8K Address Boot Block Load data AA to address 5555 Boot Block Lockout Feature Set on Last 8K Address Boot Block Load data AA to address 5555 Load data 55 to address 2AAA Load data 55 to address 2AAA Load data 80 to address 5555 Load data 80 to address 5555 Load data AA to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 55 to address 2AAA Load data 40 to address 5555 Load data 40 to address 5555 Load data 00 to address 00000 Load data FF to address 3FFFF Pause 10 mS Pause 10 mS Notes for boot block lockout enable: 1. Data Format: DQ7 - DQ0 (Hex) 2. Address Format: A14 - A0 (Hex) 3. If you have any questions about this command sequence, please contact the local distributor or Winbond Electronics Corp. -9- Publication Release Date: March 26, 2002 Revision A3 W29C022 DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER Power Supply Voltage to VSS Potential Operating Temperature Storage Temperature D.C. Voltage on Any Pin to Ground Potential Except A9 Transient Voltage (<20 nS) on Any Pin to Ground Potential Voltage on A9 and #OE Pin to Ground Potential RATING -0.5 to 7.0 0 to +70 -65 to +150 -0.5 to VDD +1.0 -1.0 to VDD +1.0 -0.5 to 12.5 UNIT V C C V V V Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. Operating Characteristics (VDD = 5.0V 10%, VSS = 0V, TA = 0 to 70 C) PARAMETER Power Supply Current SYM. ICC TEST CONDITIONS MIN. #CE = #OE = VIL, #WE = VIH, all DQs open Address inputs = VIL/VIH, at f = 5 MHz #CE = #OE = VIL, #WE = VIH, all DQs open Address inputs = VIL/VIH, at f = 2 MHz - LIMITS TYP. MAX. 50 UNIT mA - 30 Standby VDD Current (TTL input) Standby VDD Current (CMOS input) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output High Voltage CMOS ISB1 ISB2 ILI ILO VIL VIH VOL #CE = VIH, all DQs open Other inputs = VIL/VIH #CE = VDD -0.3V, all DQs open VIN = Vss to VDD VIN = Vss to VDD IOL = 2.0 mA 2.0 2.4 4.2 2 20 - 3 100 10 10 0.8 0.45 - mA A A A V V V V V VOH1 IOH = -400 A VOH2 IOH = -100 A; VDD = 4.5V - 10 - W29C022 Power-up Timing PARAMETER Power-up to Read Operation Power-up to Write Operation SYMBOL TPU. READ TPU. WRITE TYPICAL 100 5 UNIT S mS CAPACITANCE (VDD = 5.0V, TA = 25 C, f = 1 MHz) PARAMETER DQ Pin Capacitance Input Pin Capacitance SYMBOL CDQ CIN CONDITIONS VDQ = 0V VIN = 0V MAX. 12 6 UNIT pF pF AC CHARACTERISTICS AC Test Conditions (VDD = 5.0V 10% for 90 nS and 120 nS; VDD = 5.0V 5% for 70 nS) PARAMETER Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load 0V to 3V <5 nS 1.5V/1.5V CONDITIONS 1 TTL Gate and CL = 100 pF for 90/120 nS CL = 30 pF for 70 nS AC Test Load and Waveform +5V 1.8K DOUT 100 pF for 90/120 nS 30 pF for 70 nS (Including Jig and Scope) 1.3K Input 3V 1.5V 0V Test Point Output 1.5V Test Point - 11 - Publication Release Date: March 26, 2002 Revision A3 W29C022 AC Characteristics, continued Read Cycle Timing Parameters (VSS = 0V, TA = 0 to 70 C) PARAMETER SYMBOL W29C022 MIN. MAX. 120 120 50 30 30 - UNIT Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time #CE High to High-Z Output #OE High to High-Z Output Output Hold from Address Change TRC TCE TAA TOE TCHZ TOHZ TOH 120 0 nS nS nS nS nS nS nS Byte/Page-write Cycle Timing Parameters PARAMETER Write Cycle (Erase and Program) Address Setup Time Address Hold Time #WE and #CE Setup Time #WE and #CE Hold Time #OE High Setup Time #OE High Hold Time #CE Pulse Width #WE Pulse Width #WE High Width Data Setup Time Data Hold Time Byte Load Cycle Time SYMBOL TWC TAS TAH TCS TCH TOES TOEH TCP TWP TWPH TDS TDH TBLC MIN. 0 50 0 0 0 0 70 70 100 50 0 TYP. MAX. 10 150 UNIT mS nS nS nS nS nS nS nS nS nS nS nS S Note: All AC timing signals observe the following guideline for determining setup and hold times: Reference level is VIH for high-level signal and VIL for low-level signal. - 12 - W29C022 AC Characteristics, continued #DATA Polling Characteristics (1) PARAMETER Data Hold Time #OE Hold Time #OE to Output Delay (2) Write Recovery Time SYMBOL TDH TOEH TOE TWR MIN. 10 10 0 TYP. MAX. UNIT nS nS nS nS Notes: (1) These parameters are characterized and not 100% tested. (2) See TOE spec in A.C. Read Cycle Timing Parameters. Toggle Bit Characteristics (1) PARAMETER Data Hold Time #OE Hold Time #OE to Output Delay (2) #OE High Pulse Write Recovery Time SYMBOL TDH TOEH TOE TOEHP TWR MIN. 10 10 150 0 TYP. MAX. UNIT nS nS nS nS nS Notes: (1) These parameters are characterized and not 100% tested. (2) See TOE spec in A.C. Read Cycle Timing Parameters. TIMING WAVEFORMS Read Cycle Timing Diagram TRC Address A17-0 #CE TCE #OE TOE #WE VIH TOHZ TOH DQ7-0 High-Z Data Valid TAA T CHZ Data Valid High-Z - 13 - Publication Release Date: March 26, 2002 Revision A3 W29C022 Timing Waveforms, continued #WE Controlled Write Cycle Timing Diagram T WC TAS Address A17-0 #CE TAH TCS TOES TCH TOEH #OE TWP TWPH #WE TDS DQ7-0 Data Valid TDH Internal write starts #CE Controlled Write Cycle Timing Diagram TAS TAH TWC Address A17-0 TWPH #CE T OES #OE #WE TDS DQ7-0 High Z Data Valid TCS TCP TOEH TCH TDH Internal Write Starts - 14 - W29C022 Timing Waveforms, continued Page Write Cycle Timing Diagram TWC Address A17-0 DQ7-0 #CE #OE #WE TWP TWPH TBLC Byte 0 Byte 1 Byte 2 Byte N-1 Internal Write Start Byte N #DATA Polling Timing Diagram Address A17-0 #WE #CE TOEH #OE TDH DQ7 TOE HIGH-Z TWR - 15 - Publication Release Date: March 26, 2002 Revision A3 W29C022 Timing Waveforms, continued Toggle Bit Timing Diagram #WE #CE TOEH #OE TDH TOE DQ6 HIGH-Z TWR Page Write Timing Diagram Software Data Protection Mode Three-byte sequence for software data protection mode Address A15-0 5555 2AAA 5555 Byte/page load cycle starts TWC DQ15-0 AAAA 5555 A0A0 #CE #OE TWP #WE TWPH SW1 SW2 Word 0 Word N-1 Word N (last word) Internal write starts TBLC SW0 - 16 - W29C022 Timing Waveforms, continued Reset Software Data Protection Timing Diagram Six-byte sequence for resetting software data protection mode Address A15-0 5555 2AAA 5555 5555 2AAA 5555 TWC DQ7-0 AA 55 80 AA 55 20 #CE #OE TWP #WE TWPH SW0 SW1 SW2 SW3 SW4 SW5 Internal programming starts TBLC Software Chip Erase Timing Diagram Six-byte code for 5V-only software chip erase Address A15-0 5555 2AAA 5555 5555 2AAA 5555 TWC DQ7-0 AA 55 80 AA 55 10 #CE #OE TWP #WE SW0 TWPH SW1 SW2 SW3 SW4 SW5 Internal erasing starts TBLC - 17 - Publication Release Date: March 26, 2002 Revision A3 W29C022 ORDERING INFORMATION PART NO. ACCESS TIME (nS) POWER STANDBY SUPPLY CURRENT VDD CURRENT MAX. (mA) MAX. (A) 50 100 PACKAGE CYCLING W29C022 Notes: 1K 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. - 18 - W29C022 BONDING PAD DIAGRAM 5 4 4 3 2 1 32 32s 32s 31 30 29 28 27 -1 -2 A6 A7 A12 6 A5 7 A4 A15 A16 VccVcc VccWEA17A14A13 A8 26 A9 25 A11 Y X 8 A3 9 A2 26 A9 25 RA8048 A11 10 11 12 13 14 15 16s 16s 17 18 19 20 21 22 23 -1 -2 A1 A0 I/O0I/O1 I/O2GND VSS I/O3I/O4I/O5I/O6I/O7CE A10 VSS PAD NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16S-1 16S-2 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32S-1 32S-2 32 X -354.32 -491.12 -1085.00 -1221.80 -1387.04 -1500.86 -1500.86 -1470.02 -1470.02 -1316.36 -1179.56 -949.94 -699.98 -477.02 -271.34 -60.38 -17.38 209.57 432.53 682.49 905.45 1155.41 1378.97 1485.11 1485.11 1492.43 1492.43 1373.30 1236.50 815.66 503.66 366.86 180.71 138.11 -73.61 Y 3100.88 3100.88 3100.88 3100.88 3100.88 2893.70 2756.90 -2758.97 -2924.21 -3104.57 -3104.57 -3103.49 -3103.49 -3103.49 -3059.15 -3059.15 -3059.15 -3091.49 -3091.49 -3091.49 -3091.49 -3091.49 -3094.91 -2889.80 -2753.00 2745.20 2933.00 3100.88 3100.88 3100.88 3100.88 3100.88 3094.82 3094.82 3094.79 Note: For bare chip form (C.O.B.) applications, the substrate must be connected to VDD or left floating in the PCB layout. - 19 - Publication Release Date: March 26, 2002 Revision A3 W29C022 VERSION HISTORY VERSION A1 A2 A3 DATE Apr. 1997 Mar. 2001 Mar. 26, 2002 PAGE 10 1, 18, 20, 21 1, 12 1, 18 4 19 Initial Issued Add in one more Test Condition in Power Supply Current (Icc): f = 2 MHz Delete Package Description Delete Access Time Delete 10K cycling Modify VDD Power Up/Down Detection description Add Bonding Pad Diagram DESCRIPTION Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ Winbond Electronics Corporation America 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office 9F, No.480, Rueiguang Rd., Neihu Chiu, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 Winbond Electronics Corporation Japan 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 20 - |
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