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CXG1121TN
SP4T GSM/GPRS Dual-Band Antenna Switch + Logic
Description The CXG1121TN is one of a range of low insertion loss, high power MMIC antenna switches for GSM/ GPRS dual-band application. The low insertion loss on transmit means increased talk time as the Tx power amplifier can be operated at a lower output level. On-chip logic reduces component count and simplifies PWB layout by allowing direct connection of the switch to digital base band control lines with CMOS logic levels. This switch is an SP4T, one antenna can be routed to either of the 2 Tx or 2 Rx ports. It requires 3 CMOS control lines (Tx/Rx, GSM900/1800 and Standby). The Sony GaAs JFET process is used for low insetion loss. An evaluation PWB is available. Features * Insertion loss (Tx) 0.5dB typical at 34dBm (GSM900) * 3 CMOS compatible control lines * Low second harmonic, -40dBm typical, at 34dBm (GSM900) * Small package size: 16-pin TSSOP (3.9mm x 4.1mm x 1.2mm) Applications * Dual-band handsets using combinations of GSM900/GSM1800/GSM1900 * GPRS class 12 handsets Structure GaAs J-FET MMIC 16 pin TSSOP (Plastic)
Absolute Maximum Ratings (Ta = 25C) * Bias voltage VDD 7 * Control voltage VCTL 5 * Operating temperature Topr -20 to +80
V V C
GaAs MMICs are ESD sensitive devices. Special handling precautions are required. The IC will be damaged in the range from 100 to 200V @200pF 0 and below 1000V @100pF 1500.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E01661-PS
CXG1121TN
Pin Configuration
GND
9
8
Tx1
GND 10
7
GND
ANT 11
6
Tx2
GND 12
5
GND
VDD 13
4
Rx1
GND 14
3
GND
Band Select 15
2
Rx2
Tx/Rx 16
1
STDBY
Truth Table On Pass ANT - Tx1 DCS1800 ANT - Tx2 GSM900 ANT - Rx1 GSM900/DCS1800 ANT - Rx2 GSM900/DCS1800 OFF Band select H L L H -- Tx (H) / Rx (L) H H L L -- Standby H H H H L
-2-
CXG1121TN
Electrical characteristics Item Symbol Port Tx2 - ANT Insertion loss IL Tx1 - ANT ANT - Rx1 ANT - Rx2 ANT - Tx1 Isolation ISO ANT - Tx2 Tx2 - Rx1, Rx2 Tx1 - Rx1, Rx2 VSWR VSWR 2fo Harmonics 3fo 2fo 3fo P1dB compression input power Control current Supply current Leakage current P1dB ICTL IDD IIK 1 GSM Tx - ANT DCS Tx - ANT GSM Tx - ANT DCS Tx - ANT 1 2 2 1 2 VCTL = 3V STBY = H STBY = L Condition 1 2 3 4 3 4 1 2 Min. Typ. 0.5 0.6 0.55 0.7 20 17 20 20 1.2 -40 -34 -40 -34 36 36 80 0.5 90
(Ta = 25C) Max. 0.7 0.8 0.75 0.9 Unit dB dB dB dB dB dB dB dB -36 -30 -36 -30 dBm dBm dBm dBm dBm dBm 120 1.0 A mA A
Electrical characteristics are measured with all RF ports terminated in 50. Harmonics measured with Tx inputs harmonically matched. The use of harmonic matching is recommended to ensure optimum performance. 1 2 3 4 Power Power Power Power incident incident incident incident on on on on GSM Tx, Pin = 34dBm, 880 to 915MHz, VDD = 5.0V, GSM Tx enabled DCS Tx, Pin = 32dBm, 1710 to 1785MHz, VDD = 5.0V, DCS Tx enabled ANT, Pin = 10dBm, 925 to 960MHz, VDD = 5.0V, GSM Rx enabled ANT, Pin = 10dBm, 1805 to 1880MHz, VDD = 5.0V, DCS Rx enabled
Supply Voltage Value (VDD) Mode GSM/DCS Tx GSM/DCS Rx Min. 4.5 2.7 Typ. 5 3 Max. 5.7 4 Unit V V
CMOS Logic Value Logic High Low Min. 2.4 0 Typ. 2.8 Max. 3.2 0.4 Unit V V
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CXG1121TN
Recommended Circuit
9
GND
Tx1
8 47pF
10 GND
GND
7
11 ANT 47pF 12 GND
Tx2
6 22pF
GND
5
13 VDD 100pF 14 GND 15 Band Select 100pF 16 Tx/Rx 100pF
Rx1
4 47pF
GND
3
Rx2
2 22pF
STDBY
1 100pF
Note) Capacitors are required on all RF ports for DC blocking (22pF - 47pF). Decoupling capacitors are required on VDD and on control lines (100pF).
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CXG1121TN
Application Note (1) Operating from Regulated Supplies between 3V and 2.7V
Logic Lines
8
Tx1
6
Tx2 CXG1121TN 11 ANT
4
Rx1
2
Rx2 13 VDD
VDD between 5.7V and 4.5V during Tx
Additional components C: 0603 CAP F2 R: 200R D: Low Turn-on voltage diode
1
C
D Timeslot waveform
R
Regulated supply between 3V and 2.7V
Technique Allows use of CXG1121TN SP4T in handsets with regulated supplies between 3V and 2.7V. The CXG1121TN is for 5V nominal battery voltage but works well down to a VDD of 4.5V. This technique is only necessary for Tx modes. Fundamentally, the timeslot waveform is added to the supply voltage to give a VDD between 5.7V and 4.5V (depending on supply) during Tx modes. This technique is suitable for up to 4 consecutive Tx timeslots (i.e.GPRS Class 12). 1 This waveform may be taken from the PA ramping input (or drain supply in case of drain power control) or via the Tx ON/OFF logic. 2 Minimum and recommended value of capacitance C depends on GPRS class and is given by the following table. Number of consecutive Tx timeslots 1 2 4 Minimum and recommended value of capacitance C (F) 1.0 2.0 2.0 -5-
CXG1121TN
Application Note (2) Impedance Matching for Harmonic Minimization This note outlines the method used to find the source impedance to present to a transmit port at the second harmonic frequency (2fo) to reduce the second harmonic level at the antenna. This should be carried out for a set of devices that represent the process variants. This way a compromise can be found that suits all variants. The necessary equipment is shown immediately below.
Power Meter
Fundamental, fo
Second Harmonic, 2fo
Signal Generator
B.P.F.
10dB Coupler
Diplexer
Load Pull Tuner
DC Block
D.U.T.
DC Block
Spectrum Analyzer
The device should be mounted on a PWB with 50 tracks running from all RF pins to SMA connectors on the PWB edge (DUT). All ports should be externally DC blocked and unused ports should be terminated in 50. All measurements should be performed at the incident powers for which the harmonic levels are specified in this document. The 2nd harmonic level at the antenna port is measured using the spectrum analyzer and the vertical and horizontal position of the load pull stub adjusted such that this level is minimized. The device should then be removed from the board and an SMA connector mounted such that the source impedance seen by the transmit port at 2fo can be measured using a VNA. Measurements should be de-embedded to the end of the SMA center pin. A network should then be designed to match the impedance of the low pass filter (LPF), which usually comes in front of the device, to the 2fo source impedance that gives sufficiently reduced 2fo levels for all devices measured. The network should be designed to maintain a good match and insertion loss at the fundamental frequency. -6-
CXG1121TN
Package Outline
Unit: mm
16PIN TSSOP (PLASTIC)
1.2MAX 4.1 2.05 A 16
X
S B 9 X2 0.2 SAB 0.08 S
0.1
(3.0)
0.1 0.05 0.25
2.9 0.1
X
0.5
0.1
SA B
0 to 8
0.08 M S A B
0.2 0.02 + 0.036 0.22 - 0.03 DETAIL B
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE TSSOP-16P-L01 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.03g
LEAD PLATING SPECIFICATIONS ITEM LEAD MATERIAL SOLDER COMPOSITION PLATING THICKNESS SPEC. COPPER ALLOY Sn-Bi Bi:1-4wt% 5-18m
0.1 0.01 + 0.026 0.12 - 0.02
0.45 0.1
1
8
X4
3.9
-7-
Sony Corporation

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