View AN30210A_276678.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Voltage Regulators
AN30210A
Power supply control IC for a digital still camera
Overview
The AN30210A is a low voltage operative IC which has 1-ch., 5 V output sharing self-biasing voltage and PWM DC-DC converter control outputs of 6-ch. It is configured with step-up 3 channels, step-up/down 1 channel, stepdown 1 channel and 2 channels for transformer drive. Since its minimum operating voltage is as low as 1.5 V, it can be operated by two dry batteries. All channels operate synchronously and a synchronous rectification method is used for the low output voltage channel, thus achieving a high precision output voltage with VREF 1%. It also is capable of driving directly the output power MOSFET of each channel.
9.000.20 7.000.20 48 33 32
Unit: mm
(0.50) 7.000.20
17
49
64
1.400.10
y
0.40 0.16+0.10 -0.05
1.70max.
1 (0.50)
16
9.000.20
(1.00)
ar
Seating plane
0.100.10
0.15
+0.10 -0.05
0 to10 0.500.25
Features
* Operating supply voltage range: 1.5 V to 7.2 V * High precision reference voltage circuit built-in (1%) * All channels are synchronous operation in PWM control * Synchronous rectification for the low output voltage channel (Synchronous rectification can be stopped by the external signal at the low load: STOP) * ON/OFF (sequence control) pin attached for each and all channels. Soft-start pins for each channel (Simultaneous soft start is available with one external capacitor.) * Timer latch circuit for short-circuit protection circuit (Selectable for each channel separately or all channels simultaneously) * Control frequency reduction is available by an external signal at the low load. * Maximum duty cycle 88% (Adjustment range of 0% to 100% with an external resistor) * Low power dissipation and high speed operation thanks to 0.6 m CMOS process
LQFP064-P-0707
Applications
* Digital still cameras
Pr e
lim
SDH00015EEB
in
Note) The package of this product will be changed to lead-free type (LQFP064-P-0707B). See the new package dimensions section later of this datasheet.
Publication date: December 2002
1
AN30210A
Block Diagram
SCP VREF 58 60 COSC 32
(H:Frequency down)
H-start RT 57 56
1.40 V 0.55 V
SCP0
CT 17
CTL0 46 44 SVCC 48 VBAT
VREF
(High temperature: H) Temp. det. TOSH 24 (H :Total shut-down) (POR) VREF
R S Q Q (POR) S Q S.C.P.0 DisC R
(Overvoltage: L)
Overvoltage
(Voltage down: L)
Voltage descent
47 VBATL 43 DI 42 DEI 41 DO 25 DRV0
VREF 1.26 V (allowance: 1%)
VCC U.V.L.O.
OSC
(VBATL input: H)
VBAT U.V.L.O. 1.5 V/ 2.5 V (Voltage down: L)
(DisC)
VREF
1.6V PWM0
ar
VREF VO0 VREF 51 IN0 21 PVCC1 28 Out1 30 7 13 23 22 20 19 8 45 18 34 33 31 29 PGND1 SS1 PNSW2 PVCC2 HO2 MO2 LO2 SS2 PNSW3 STOP PVCC3 HO3 MO3 LO3 VCC Dead time PVCC1 cont.
PGND1
26 PGND0 27 ASIST 6 SS0 52 VO0 53 EO0
y
VCC 9 SS3 5 SS VBAT VBAT IN6
Latch
VCC
Voltage step-up for IC drive VCC
5 V/0.05 A
(POR) Latch
1.6 V
Error amp.0
EO1 VO1
55 VREF 54
S.C.P. comp.
in
PWM1 PWM2 PWM3 Dead time cont. PVCC1
PGND1
R S
Q Q
VBAT Voltage step-up IN1
Ch.1 5 V/1 A
VREF Error amp.1 (POR) Latch
1.6 V
EO2 VO2 CTL2 H-start
62 VREF 61
S.C.P. comp.
R S
lim
Q Q
IN1 35 CTL1 H-start
Voltage step-up/down SW (at step-down) IN2
Ch.2 3.3 V/0.5 A
VREF
IN2 36
Error amp.2
(POR) Latch
1.6 V
EO3 VO3
Pr e
Error amp.3 (POR) Latch
R S Q Q 1.6 V
50 VREF 49
S.C.P. comp.
R S
Q Q
VBAT Voltage step-down IN3
Ch.3 1.5 V/0.3 A 1.8 V/0.3 A
IN3 37 CTL3 H-start EO4 VO4
VREF
Transformer drive IN4
Ch.4-1 CCD main (15 V/30 mA) Ch.4-2 CCD sub (-8 V/10 mA)
64 VREF 63
S.C.P. comp.
VREF PWM4
PVCC1 16 DRV4
PGND1
CTL4 H-start EO5 VO5
IN4 38
Error amp.4
(POR) Latch
R S Q Q
10 SS4
1.6 V
2 VREF 1
S.C.P. comp.
Transformer drive IN5
Ch.5-1 LCD (12.4 V/30 mA) Ch.5-2 LCD (3.7 V/60 mA)
VREF PWM5 Error amp.5 (POR) Latch
PVCC1 15 DRV5
PGND1
IN5 39 CTL5 H-start EO6 VO6
11 SS5 VBAT 14 DRV6
1.6 V
4 VREF 3
S.C.P. comp.
R S
Q Q
PVCC1 VREF PWM6
Voltage step-up
Ch.6 Back light 7 V/100 mA
PGND1
IN6 40 CTL6 H-start
Error amp.6 59 SGND
12 SS6
2
SDH00015EEB
AN30210A
Pin Descriptions
Pin No. Symbol 1 2 3 4 5 IN5 EO5 IN6 EO6 SS Description Ch.5 error amplifier inverting input pin Ch.5 error amplifier output pin Ch.6 error amplifier inverting input pin Ch.6 error amplifier output pin Ch.1 to ch.3 common soft-start setting pin 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 SS0 SS1 SS2 SS3 SS4 SS5 SS6 Ch.0 soft-start setting pin Ch.1 soft-start setting pin Ch.2 soft-start setting pin Ch.3 soft-start setting pin Ch.4 soft-start setting pin Ch.5 soft-start setting pin Ch.6 soft-start setting pin 45 46 Pin No. Symbol 33 34 35 36 37 38 39 40 41 42 43 44 HO3 PVCC3 CTL1 CTL2 CTL3 CTL4 CTL5 CTL6 DO DEI DI SVCC Description Ch.3 high-side driver pin Ch.3 US driver power supply pin Ch.1 on/off start-up input pin Ch.2 on/off start-up input pin Ch.3 on/off start-up input pin Ch.4 on/off start-up input pin Ch.5 on/off start-up input pin Ch.6 on/off start-up input pin Dropper error amplifier output pin
Dropper output monitor pin Supply voltage application pin for signal block
PNSW2 Ch.2 high-side/P-ch., N-ch. switching pin DRV6 DRV5 DRV4 CTL0 STOP LO2 MO2 PVCC1 HO2 Ch.6 driver output pin Ch.5 driver output pin Ch.4 driver output pin Ch.0 on/off start-up input pin
Synchronous rectification stop pin Ch.2 low-side driver output pin Ch.2 middle-side output pin
lim
Ch.1, ch.2/L, ch.3/L, ch.4 to ch.6 driver power supply pin
22 23 24
Pr e
PVCC2 TOSH Overcurrent individual/ DRV0 Ch.0 step-up output pin ASIST Out1 LO3 Ch.1 driver output pin driver GND MO3 COSC low load
Ch.2 high-side driver output pin Ch.2 US driver power supply pin
total shutdown switching pin 57 RT
25 26 27 28 29 30
PGND0 Ch.0 step-up output GND Assist transistor driver output pin 58 59 60 VREF SGND SCP
Ch.3 low-side driver output pin
PGND1 Ch.1, ch.2/L, ch.3/L, ch.4 to ch.6 61 62 63 64
SDH00015EEB
31 32
Ch.3 middle-side output pin Control frequency switching pin at
in
47 48 49 50 51 52 53 54 55 56 VBATL VBAT IN3 EO3 IN0 VO0 EO0 IN1 EO1 CT IN2 EO2 IN4 EO4
ar
SCP0 connection pin connection pin Signal GND
PNSW3 Ch.3 high-side/P-ch., N-ch. switching pin Short-circuit protection time constant setup capacitance connection pin for ch.0 Battery low-voltage application pin Battery voltage application pin
Ch.3 error amplifier inverting input pin Ch.3 error amplifier output pin Ch.0 error amplifier inverting input pin Ch.0 output monitor pin Ch.0 error amplifier output pin Ch.1 error amplifier inverting input pin Ch.1 error amplifier output pin Oscillator frequency setup capacitor
Oscillator frequency setup resistor
Reference voltage output pin
Short-circuit protection time constant setup capacitor connection pin for ch.1 to ch.6 Ch.2 error amplifier inverting input pin Ch.2 error amplifier output pin Ch.4 error amplifier inverting input pin Ch.4 error amplifier output pin 3
y
Dropper error amplifier inverting input pin
AN30210A
Absolute Maximum Ratings
Parameter Supply voltage VBAT / VBATL voltage Supply current Power dissipation
*2 *1
Symbol SVCC VBAT / VBATL ICC PD Topr Tstg VDRV0 PVCC1 IDRV0P PNSW2 PNSW3 VCTL0/1/2/3/4/5/6 IREF VVO0 VDI
Rating 6.9 7.5/6.0 QFS - 64 -20 to +85 -55 to +125 VBAT + 0.1 SVCC + 0.1 3.5 SVCC + 0.1 SVCC + 0.1 SVCC + 0.1 -5
Unit V V mA mW C C V V mA
Operating ambient temperature Storage temperature
*1
DRV0 allowable application voltage Power VCC1 allowable application voltage DRV0 allowable peak current
*4
Control input allowable application voltage 0/1/2/3/4/5/6 Reference supply allowable application current Allowable application voltage to output voltage detection input 0 Allowable application voltage to output voltage detection input D1 Error amplifier (0 to 6) allowable application voltage to input pin
ar
SVCC + 0.1 SVCC + 0.1 - 0.2 to SVCC - 0.2 to SVCC SVCC + 0.1 SVCC + 0.1 SVCC + 0.1 SVCC + 0.1 SVCC + 0.1
Ch.3 high-side transistor switching input allowable application voltage *3
y
Ch.2 high-side transistor switching input allowable application voltage *3
V V V mA V V V V V V V V V
Error amplifier (dropper) allowable application voltage to input pin Low frequency setting pin input allowable application voltage *3
Pr e
Synchronous rectification stop pin input application voltage *3
Total shutdown pin input allowable voltage *3 Allowable application voltage between PVCC2 and MO2
Allowable application voltage between PVCC3 and MO3
Note) *1: Except for the power dissipation, operating ambient temperature and storage temperature, all ratings are for Ta = 25C. *2: Ta = 85C. For the independent IC without a heat sink. Note that applications must observe the derating curve for the relationship between the IC power consumption and the ambient temperature. *3: Do not apply external currents or voltages to any pins not specifically mentioned. For the circuit currents, '+' denotes current flowing into the IC, and '-' denotes current flowing out of the IC. *4: t < 10 ms, VDS < 5 V
4
lim
VIN0/1/2/3/4/5/6 VDEI COSC STOP TOSH PVMO2 PVMO3
SDH00015EEB
in
AN30210A
Recommended Operating Range
Parameter Supply voltage Symbol SVCC VBAT VBATL Range 4.5 to 5.5 2.8 to 7.2 1.5 to 4.6 Unit V
Electrical Characteristics (Unless otherwise specified, Ta = 25C 2C)
Parameter Reference voltage Reference voltage Line regulation Load regulation SVCC low voltage protection Circuit operation start voltage Circuit operation stop voltage VBAT low voltage protection Circuit operation start voltage Circuit operation stop voltage Circuit operation start voltage Circuit operation stop voltage Dropper amp. block Output sink current Output leak current Output block Output transistor N-ch. on resistance (ch.0) VBATLON At VBATL input VBATLOFF At VBATL input VBATON At VBAT input SVCCON SVCCOFF VREF Line Load IREF = - 0.1 mA SVCC = 4.5 V to 5.5 V IREF = 0 mA to -1.0 mA 1.256 1.269 1.282 -24 3 -12 15 V mV mV Symbol Conditions Min Typ Max Unit
y
3.8 3.6 4.0 3.8 2.05 2.00 2.28 2.23 8 PVCC-0.1 PVCC-0.1 PVCC-0.1 16 0.6 3 3 3 3 3 3
ar
4.2 4.0
V V
1.331 1.418 1.505 1.251 1.338 1.425 2.51 2.46 2
V V V V
VBATOFF At VBAT input
lim
IRS IRL RON0 IL0 VH1/4/5/6 VL1/4/5/6 IOL = 1 mA IO = 30 mA RN1/4/5/6 RP1/4/5/6 VLOH2 VLOL2 VHOH2 VHOL2 R2LN R2LP R2HN R2HP IOL = 1 mA IOL = 1 mA IO = 30 mA IO = 30 mA
At VBATL = 3 V input At VBATL = 3 V input IDRV0 = 30 mA VDRV0 = 5.0 V IOH = -1 mA
in
mA A A V V V V V V
1.2 2 0.1 10 10 0.1 MO2+0.1 10 10 10 10
Output leak current (ch.0)
Output high voltage (ch.1, 4, 5, 6) Output low voltage (ch.1, 4, 5, 6) N-ch. on resistance (ch.1, 4, 5, 6) P-ch. on resistance (ch.1, 4, 5, 6)
Pr e
IO = -30 mA IOH = -1 mA IOH = -1 mA
Low-side high output voltage (ch.2) Low-side low output voltage (ch.2) High-side high output voltage (ch.2) High-side low output voltage (ch.2) LO2 pin N-ch. on resistance (ch.2) LO2 pin P-ch. on resistance (ch.2) HO2 pin N-ch. on resistance (ch.2) HO2 pin P-ch. on resistance (ch.2)
IO = -30 mA IO = -30 mA
SDH00015EEB
5
AN30210A
Electrical Characteristics (continued) (Unless otherwise specified, Ta = 25C 2C)
Parameter Output block (continued) Low-side high output voltage (ch.3) Low-side low output voltage (ch.3) High-side high output voltage (ch.3) High-side low output voltage (ch.3) LO3 pin N-ch. on resistance (ch.3) LO3 pin P-ch. on resistance (ch.3) HO3 pin N-ch. on resistance (ch.3) HO3 pin P-ch. on resistance (ch.3) Ch.0 output maximum duty ratio Ch.1 output maximum duty ratio VLOH3 VLOL3 VHOH3 VHOL3 R3LN R3LP R3HN R3HP Dumax0 Dumax1 IOH = -1 mA IOL = 1 mA IOH = -1 mA IOL = 1 mA IO = 30 mA IO = -30 mA IO = 30 mA IO = -30 mA At VBATL = 3 V input At VBATL = 3 V input PVCC-0.1 PVCC-0.1 79 81 78 82 3 3 3 3 85 87 85 88 0.1 MO3+0.1 10 10 10 10 91 93 92 94 V V V V % % % % Symbol Conditions Min Typ Max Unit
Ch.4/5/6 output maximum duty ratio Dumax4/5/6 At VBATL = 3 V input Oscillator Ch.0 start-up oscillation frequency 1 Ch.0 start-up oscillation frequency 2 Ch.0 start-up output duty ratio 1 Ch.0 start-up output duty ratio 2 Ch.0 to ch.6 oscillation frequency Ch.0 to ch.6 low oscillation frequency fST1 fST2 DuST1 DuST2 FOUT
At VBAT = 3 V input At VBAT = 3 V input
in
At VBATL = 3 V input At VBATL = 3 V input
ar
110 110 45 46 465 15 1.23 1.0 -28 0.5 1.12 1.07
Ch.2/3 output maximum duty ratio Dumax2/3 At VBATL = 3 V input
y
270 270 53 54 515 25 1.27 - 0.25 - 0.15 -22.5 1.24 1.217
430 430 61 62 565 35
kHz kHz % % kHz kHz
Error amplifier (ch.0 to ch.6) Input threshold voltage IN0/1/2/3/4/5/6 Input bias voltage IN0/1/2/3/4/5/6
lim
0/1/2/3/4/5/6
CT = 180 pF, RT = 33 k COSC = 0 V, VBATL = 3 V CT = 180 pF, COSC = 5 V RT = 33 k, VBATL = 3 V
FLOUT
0/1/2/3/4/5/6
Pr e
VTH IB
1.31 0.2 -17
V A V V A mA
0/1/2/3/4/5/6
0/1/2/3/4/5/6
High-level output voltage EO0/1/2/3/4/5/6 Low-level output voltage EO0/1/2/3/4/5/6 Output source current EO0/1/2/3/4/5/6 Output sink current EO0/1/2/3/4/5/6
VEH VEL ISO
0/1/2/3/4/5/6
0/1/2/3/4/5/6
0/1/2/3/4/5/6
ISI
0/1/2/3/4/5/6
Ch.0 short-circuit protection circuit block Standby pin voltage Latch threshold voltage 1 Latch threshold voltage 2 6 VSCP0 VLTH01 VLTH02 At VBATL input or VBAT input At VBATL input At VBAT input
SDH00015EEB
0.1 1.36 1.31
V V V
AN30210A
Electrical Characteristics (continued) (Unless otherwise specified, Ta = 25C 2C)
Parameter Symbol Conditions Min Typ Max Unit Ch.0 short-circuit protection circuit block (continued) Pin voltage after latch operation Charge current 1 Charge current 2 VSLT0 ICHG01 ICHG02 At VBATL input or VBAT input At VBATL input, VSCP0 = 0 V At VBAT input, VSCP0 = 0 V 0.1 V A A -2.92 -2.22 -1.52 -3.16 -2.22 -1.28
Ch.1 to ch.6 short-circuit protection circuit Pin voltage at standby Timer threshold voltage ch.1 to ch.6 Pin voltage at latch operation ch.1 to ch.6 Charge current Control Pin current CTL0/1/2/3/4/5/6 Input high voltage CTL0/1/2/3/4/5/6 Input low voltage CTL0/1/2/3/4/5/6 Current consumption Startup average quiscent consumption current 1 Startup average quiscent consumption current 2 IBATL IBAT ICTL
0/1/2/3/4/5/6
VSCP VLTH
1/2/3/4/5/6
0.1
V V V A A V V
1.142 1.268 1.394 VSCP = 0 V VCTL = 2.7 V 0.1
VSLT
1/2/3/4/5/6
ICHG1
ar
-1 2.7 1.5 1.5 1.5
y
500 450 3 5 5 PVCC2/ PVCC3 MO2/ MO3
-1.660 -1.282 - 0.904 1 0.3
VCTLH
0/1/2/3/4/5/6
VCTLL
0/1/2/3/4/5/6
lim
ISBL ISB
in
Ch.0 with no outside-transistor At VBATL input, SS0 = 0 V Ch.0 with no outside-transistor At VBAT input, SS0 = 0 V Ch.0 to ch.6 at output off CTL0 to CTL6 = 0 V (VBATL = 3 V) CTL0 to CTL6 = 0 V (VBAT = 3 V) Refer to " Usage Note, 5" (page 20) Refer to " Usage Note, 5" (page 20)
SDH00015EEB
700 650 8 10 10 0.3 0.3 0.3
A A mA A A V V V V V V V V
Average quiscent current consumption ICC(AV)
Standby current 2
Operation mode switching block ch.2 P-ch./N-ch. configuration setting voltage ch.2 N-ch./N-ch. configuration setting voltage
Synchronous rectification stop voltage Synchronous rectification stop release voltage Low oscillation-frequency setting voltage Low oscillation-frequency release voltage Total shutdown setting voltage Total shutdown release voltage
Note) Unless otherwise specified, VBAT (VBATL) = 3 V, SVCC = PVCC1 = PVCC4 = 5 V, CREF = 0.1 F
Pr e
Standby current 1
7
AN30210A
Electrical Characteristics (continued) (Unless otherwise specified, Ta = 25C 2C)
* Design reference data
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter Reference voltage VREF temperature characteristics SVCC low voltage protection Voltage difference between operation start and stop (SVCC) VBAT low voltage protection Voltage difference between operation start and stop (VBATL) Voltage difference between operation start and stop (VBAT) Error amplifier (ch.0 to ch.6) VTH temperature characteristics Open loop gain Oscillator Frequency supply voltage characteristics Frequency temperature characteristics Startup oscillator Frequency temperature characteristics output 1 Frequency temperature characteristics output 2
Symbol
Conditions Ta = 0C to 70C SVCCON - SVCCOFF > 0
Target value 1.0 0.2
Unit
VREFdt SVCC
%
V
VBATL VBAT
VBATLON - VBATLOFF > 0 VBATON - VBATOFF > 0
0.07
V V
VTHdt AV fdV fdT
Ta = 0C to 70C
ar
y
1.5 60 10 3 25 25 20 20 1.6 1.6 5.3 125 3 6
0.05
% dB
SVCC = 4.5 V to 5.5 V RT = 33 k, CT = 180 pF Ta = -20C to 85C RT = 33 k, CT = 180 pF Ta = 0C to 70C At VBATL = 3 V input Ta = 0C to 70C At VBAT = 3 V input VBATL = 1.5 V to 4.6 V VBAT = 2.8 V to 7.2 V
in
% %
lim
fSTT1 fSTT2 fSTVD1 fSTVD2 VTHSB VTHSS VTHS ROAN ROAP
% % % %
Supply voltage characteristics 1 Supply voltage characteristics 2
Short-circuit protection circuit
Comparator threshold voltage (VBAT) Overvoltage protection circuit
Pr e
At VBATL input At VBATL input
V V
Comparator threshold voltage (SVCC)
Overvoltage circuit operation voltage Thermal protection circuit Circuit operation stop temperature Assist driver circuit N-ch. on resistance P-ch. on resistance
At VBATL input
V C
8
SDH00015EEB
AN30210A
Terminal Equivalent Circuits
Pin No. 1 Equivalent circuit SVCC Description IN5: Ch.5 error amplifier inverting input pin In/Out In
VREF
1
SVCC
VREF IN5
2
3
in lim
SVCC 4
SVCC
IN6: Ch.6 error amplifier inverting input pin
ar
In Out In 9
VREF
3
4
Pr e
EO6: Ch.6 error amplifier output pin Source current: -20 A (typ.) Sink current: 0.5 mA (min.)
VREF IN6
5
VREFH 64 k 5 1 k 112 k PWM1 to PWM3
SS: Ch.1 to ch.3 common soft-start time setting pin Connect a capacitor between this pin and GND. * Potential dividing resistance for threshold setting 64 k (typ.) 112 k (typ.) VREFH (typ.) = (306 k/200 k) x VREF (typ.)
SDH00015EEB
y
2
EO5: Ch.5 error amplifier output pin Source current: -20 A (typ.) Sink current: 0.5 mA (min.)
Out
AN30210A
Terminal Equivalent Circuits (continued)
Pin No. 6 Equivalent circuit VREFH EO0 CT 64 k 6 1 k 112 k PWM0 Description SS0: Ch.0 soft-start time setting pin Connect a capacitor between this pin and GND. * Potential dividing resistance for threshold setting 64 k (typ.) 112 k (typ.) VREFH (typ.) = (306 k/200 k) x VREF (typ.) SS1: Ch.1 soft-start time setting pin Connect a capacitor between this pin and GND. * Potential dividing resistance for threshold setting 64 k (typ.) 112 k (typ.) VREFH (typ.) = (306 k/200 k) x VREF (typ.) SS2: Ch.2 soft-start time setting pin Connect a capacitor between this pin and GND. * Potential dividing resistance for threshold setting 64 k (typ.) 112 k (typ.) VREFH (typ.) = (306 k/200 k) x VREF (typ.) SS3: Ch.3 soft-start time setting pin Connect a capacitor between this pin and GND. * Potential dividing resistance for threshold setting 64 k (typ.) 112 k (typ.) VREFH (typ.) = (306 k/200 k) x VREF (typ.) SS4: Ch.4 soft-start time setting pin Connect a capacitor between this pin and GND. * Potential dividing resistance for threshold setting 64 k (typ.) 112 k (typ.) VREFH (typ.) = (306 k/200 k) x VREF (typ.) SS5: Ch.5 soft-start time setting pin Connect a capacitor between this pin and GND. * Potential dividing resistance for threshold setting 64 k (typ.) 112 k (typ.) VREFH (typ.) = (306 k/200 k) x VREF (typ.) In/Out In
7
VREFH EO1 CT 64 k 7 1 k 112 k PWM1 SS
In
8
ar
y
VREFH EO2 CT 64 k 8 1 k 112 k PWM2 SS
In
9
lim
PWM3 SS PWM4 PWM5
in
SDH00015EEB
VREFH EO3 CT 64 k 9 1 k 112 k
In
10
Pr e
VREFH EO4 CT
In
64 k
10
1 k 112 k
11
VREFH EO5 CT 64 k 11 1 k 112 k
In
10
AN30210A
Terminal Equivalent Circuits (continued)
Pin No. 12 Equivalent circuit VREFH EO6 CT 64 k 12 1 k 112 k PWM6 Description SS6: Ch.6 soft-start time setting pin Connect a capacitor between this pin and GND. * Potential dividing resistance for threshold setting 64 k (typ.) 112 k (typ.) VREFH (typ.) = (306 k/200 k) x VREF (typ.) PNSW2: Ch.2; HO2 high-side output FET P-ch., N-ch. switching pin Driven by HO2, FET P-ch., N-ch. switching over * High: P-ch. (connect to PVCC2 ) Low: N-ch. (connect to MO2) DRV6: Ch.6 output pin CMOS type output ON resistance N-ch.: 10 (max.) P-ch.: 10 (max.) In/Out In
13
In
13
14
ar
y
PVCC1 PWM6 14
Out
15
lim
PVCC1 15 PGND1
PVCC1 16 PGND1
PGND1
in
SDH00015EEB
PWM5
DRV5: Ch.5 output pin CMOS type output ON resistance N-ch.: 10 (max.) P-ch.: 10 (max.)
Out
16
Pr e
PWM4
DRV4: Ch.4 output pin CMOS type output ON resistance N-ch.: 10 (max.) P-ch.: 10 (max.)
Out
17
CTL0: Ch.0 on/off controlt pin
In
17
11
AN30210A
Terminal Equivalent Circuits (continued)
Pin No. 18 Equivalent circuit Description STOP: Synchronous rectification stop pin When STOP is high, ch.2 and ch.3 synchronous rectification stop. In/Out In
SVCC 200 k
18 200 k
19
PVCC1
20
PVCC2
HO2
lim
21
PVCC2 22 MO2
20
in
SDH00015EEB
MO2: Ch.2 output pin (high-side) Low potential side Synchronous rectification system output stage CMOS type output circuit
ar
PGND1
y
19
LO2: Ch.2 output pin (low-side) Synchronous rectification system output stage CMOS type output circuit On resistance N-ch.: 10 (max.) P-ch.: 10 (max.)
Out
Out
21
PVCC1: Output system supply voltage application pin 1 Power supply pin for ch.1, ch.2/L, ch.3/L, ch.4 to ch.6 driver HO2: Ch.2 output pin (high-side) High potential side Synchronous rectification system output stage CMOS type output circuit On resistance N-ch.: 10 (max.) P-ch.: 10 (max.)
22
Out
Pr e
23
23
PVCC2: Output system supply voltage application pin 2 Power supply pin for ch.2 US driver TOSH: Total shutdown pin When TOSH is high, all outputs are stopped if the output is short circuited.
24
SVCC 200 k 24
SVCC 200 k
In
12
AN30210A
Terminal Equivalent Circuits (continued)
Pin No. 25 Equivalent circuit
VBAT2 25
Description DRV0: Power supply output pin for ch.0 IC (5 V) drive For internal power supply of this IC Open drain type On resistance N-ch.: 1.2 (max.) PGND0: Output system grounding pin 0 Ch.0 output ASIST: Power supply auxiliary output pin for ch.0 IC drive For internal power supply of this IC Connect in parallel with DRV0 for ch.0 capacity increase On resistance (design reference data) N-ch.: 3 (typ.) P-ch.: 6 (typ.) Out1: Ch.1 output pin CMOS type output circuit On resistance N-ch.: 10 (max.) P-ch.: 10 (max.)
In/Out Out
PGND0
26 26 27
PGND0
VBATL 27 PGND0
PVCC1
28
29
lim
PGND1
in
SDH00015EEB
28
ar
y
Out
PVCC1
Pr e
29
PGND1
LO3: Ch.3 output pin (low-side) Synchronous rectification system output stage CMOS type output circuit On resistance N-ch.: 10 (max.) P-ch.: 10 (max.) PGND1: Output system ground pin 1 Grounding pin for ch.1, ch.2/L, ch.3/L, ch.4 to ch.6 driver MO3: Ch.3 output pin (high-side) Low potential side Synchronous rectification system output stage CMOS type output circuit
Out
30
PGND1
30
31
PVCC3
Out
HO2
31
13
AN30210A
Terminal Equivalent Circuits (continued)
Pin No. 32 Equivalent circuit Description COCS: Low frequency setting pin When COCS is high, the triangular wave oscillation frequency is switched over to low frequency (20 kHz/typ.) In/Out In
SVCC 200 k
32 200 k
33
PVCC3
33
MO3
34
ar
HO3: Ch.3 output pin (high-side) High potential side Synchronous rectification system output stage CMOS type output circuit On resistance N-ch.: 10 (max.) P-ch.: 10 (max.)
Out
y
35
in
SDH00015EEB
34
PVCC3: Output system supply voltage application pin 3 Power supply pin for ch.3 high-side driver CTL1: Ch.1 on/off start-up input pin
In
35
36
lim
CTL2: Ch.2 on/off control pin
In
37
Pr e
36
CTL3: Ch.3 on/off control pin
In
37
38
CTL4: Ch.4 on/off control pin
In
38
14
AN30210A
Terminal Equivalent Circuits (continued)
Pin No. 39 Equivalent circuit Description CTL5: Ch.5 on/off control pin In/Out In
39
40
CTL6: Ch.6 on/off control pin
In
40
41
150
42
in
46
SDH00015EEB
VBATL
DEI: Ch.0 dropper error amplifier inverting input pin
ar
41
DO: Ch.0 dropper error amplifier output pin When connecting the power supply to VBAT pin, connect this pin with the base of output PNP transistor of regulator amplifier which stabilizes the power supply voltage SVCC for ch.0: IC drive at 5 V. Then ch.0 output voltage is controlled.
y
Out
In
VREF
43
lim
44
43 64.64 k 42 20 k
Pr e
DI: Ch.0 dropper output monitor pin The output voltage is set by the potential dividing resistance between (DI) and SGND. * Potential dividing resistance 64.64 k (typ.) 20 k (typ.)
In
44
SVCC: Signal system supply voltage application pin PNSW3: Ch.3; HO3 high-side output FET P-ch., N-ch. switching pin Driven by HO3, FET P-ch., N-ch. switching over * High: P-ch. (connect to PVCC3 ) Low: N-ch. (connect to MO3) SCP0: Time constant setting capacitor connection pin for ch.0 output short-circuit protection
45
In
45
46
VBATL
Out
15
AN30210A
Terminal Equivalent Circuits (continued)
Pin No. 47 Equivalent circuit Description VBATL: Battery voltage application pin (low voltage) VBAT: Battery voltage application pin (high voltage) IN3: Ch.3 error amplifier inverting input pin In/Out
47
48
48
49
SVCC
In
VREF
49
SVCC
VREF IN3
50
51
lim
SVCC 53
in
SDH00015EEB
50
EO3: Ch.3 error amplifier output pin Source current: -20 A (typ.) Sink current: 0.5 mA (min.)
ar
y
Out
SVCC
IN0: Ch.0 error amplifier inverting input pin
In
52
Pr e
VREF
52 71.135 k 51 25.275 k
VO0: Ch.0 output voltage detection pin The output voltage is set by the potential dividing resistance between VO0 and SGND * Potential dividing resistance 71.135 k (typ.) 25.275 k (typ.) EO0: Ch.0 error amplifier output pin Source current: -20 A (typ.) Sink current: 0.5 mA (min.)
In
53
Out
VREF IN0
16
AN30210A
Terminal Equivalent Circuits (continued)
Pin No. 54 Equivalent circuit SVCC Description IN1: Ch.1 error amplifier inverting input pin In/Out In
VREF
54
SVCC
VREF IN1
55
56
in
57
SDH00015EEB
SVCC 500 56
CT: Triangular wave oscillation frequency setting capacitor connection pin
ar
Out Out Out 17
57
SVCC
58
Pr e
SVCC
59
59
lim
500 VREF
58
RT: Triangular wave oscillation frequency setting resistor connection pin
VREF: Reference voltage output pin
SGND: Signal system grounding pin
y
55
EO1: Ch.1 error amplifier output pin Source current: -20 A (typ.) Sink current: 0.5 mA (min.)
Out
AN30210A
Terminal Equivalent Circuits (continued)
Pin No. 60 Equivalent circuit Description SCP: Time constant setting capacitor connection pin for ch.1 to ch.6 output short-circuit protection In/Out Out
SVCC 300 60
VREF
61
SVCC
IN2: Ch.2 error amplifier inverting input pin
In
61
62
in
SDH00015EEB
SVCC
VREF IN2
EO2: Ch.2 error amplifier output pin Source current: -20 A (typ.) Sink current: 0.5 mA (min.)
ar
Out
63
lim
SVCC 64
62
SVCC
IN4: Ch.4 error amplifier inverting input pin
y
In EO4: Ch.4 error amplifier output pin Source current: -20 A (typ.) Sink current: 0.5 mA (min.) Out
VREF
64
18
Pr e
VREF 63
VREF IN4
AN30210A
Usage Notes
1. VBAT rise up speed with VBAT pin (pin 48) input Outside IC Inside IC VBAT pin 48 Rb VB C1 Step-down voltage circuit 47 VBATL pin td VBATL pin Time t (s) Figure 1. Peripheral circuit for VBAT pin and VBATL pin Figure 2. VBATL pin voltage in the VBAT pin input mode Voltage V (V) ton VBAT pin
2. VBAT voltage fall speed at VBAT pin (pin 48) input
Outside IC Inside IC VBAT pin 48 Rb VB C1
lim
Step-down voltage circuit
From A < 3 x C1 x (Rb + ZIC) C1 > A/(3 x (Rb + ZIC)) A / (3 x ZIC) . Equation (1) C1 can be calculated by substituting 500 s for A and 3 k for ZIC in the equation (1) Thus C1 > 0.055 F
C1: Bypass capacitor Rb: Internal impedance of the battery ZIC: Internal impedance of the IC 3 k A : Minimum time not exceeding the withstand voltage of VBAT pin at VBAT pin input: 500 s
in
VBAT pin sequence VBATL pin sequence
2.5 V system, low voltage protection operation area
Pr e
C2 47 VBATL pin
ar
A voltage propagation delay time (td) from VBAT pin (pin 48) to VBATL (pin 47) is made at the battery input to pin 48. If the voltage rise speed (ton) of the VBAT pin exceeds the specified value, the voltage also exceeds the pin's withstand voltage. Therefore, you are requested to use a bypass capacitor (C1 in fig.1) of more than 0.055 F capacitance. The related equation is:
y
1.5 V system, low voltage protection operation area
Time
*: There is a possibility that malfunction occurs depending on the capacity value of C1 and C2.
Figure 3. Peripheral circuit for VBAT pin and VBATL pin
Figure 4. Example of operation error
SDH00015EEB
19
AN30210A
Usage Notes (continued)
2. VBAT voltage fall speed at VBAT pin (pin 48) input (continued) * On operation of the low voltage protection circuit when battery is applied to VBAT pin. VBAT low voltage protection circuit operating voltage (VUOFF) characteristic in a battery voltage fall time of pin 48 is likely to go wrong operation area depending on the capacitance of C1 and C2. (See Figure 4.) Therefore, use it based on the relation of (C1/C2) > 2 000. The calculation equation is as follows: VBAT pin (pin 48) fall time> VBATL pin (pin 47) fall time leads to: 3 x C1 x ZHIC > 3 x C2 x ZLIC C1: VBAT pin bypass capacitor (C1/C2) > (ZLIC/ZHIC) (ZLIC/R) ....... (1) C2: VBATL pin capacitor Rb: Internal impedance of the battery ZHIC: Internal impedance of the IC measured from VBAT ZLIC: Internal impedance of the IC measured from VBATL R: Load without battery (VB) 5 (worst case) You can calculate (C1/C2) > 2 000 using the equation (1). Example) For C2 = 0.1 F, you can get C1 = 200 F. 3. This control IC is designed to operate by receiving ch.0 DC-DC output voltage under a low input voltage operation. For this reason, since its protection circuit is designed on the basis of the above operation, do not adopt any using method other than the application circuit examples. (Ex: The using method of directly applying the voltage to SVCC ) 4. Power dissipation The power dissipation P of this IC is proportional to the supply voltage. It also changes depending on the output load of ch.0, and the FET input capacitance and the oscillation frequency of ch.1 to ch.6. After referring to the PD Ta curve on its sheet No., use the IC under its allowable power dissipation on the basis of the following equation (Reference expression) VOUT1 x IOUT1 x ROUT (VOUT1 - VBAT) x IOUT P = (SVCC - VBEQ1 - )x + 6 x SVCC x Ciss x f hFEQ1 x VBAT hFEQ1 x VBAT + SVCC x ICC + VBAT x IBAT < PD VBEQ1 : Ch.0 NPN transistor base-emitter voltage hFEQ1 : Ch.0 NPN transistor current amplification ratio ROUT : Ch.0 NPN transistor bias current limiting resistance Ciss : Ch.1 to ch.6 output connection FET input capacitance f : Oscillation frequency ICC : SVCC , PVCC1 , PVCC2 and PVCC3 pin current IBAT : VBAT or VBATL pin current 5. PNSW2: Ch.2 high-side P-ch., N-ch. switching pin * In the case of P-ch., connect to PVCC2 * In the case of N-ch., connect to MO2 PNSW3: Ch.2 high-side P-ch., N-ch. switching pin * In the case of P-ch., connect to PVCC3 * In the case of N-ch., connect to MO3
Pr e
20
lim
SDH00015EEB
in
ar
y
AN30210A
Application Notes
[1] Functional outline descriptions 1. Functional outline description figure 1) After power supply connection, turn on the control pin CTL0. 2) PWM control operates to step-up the supply voltage and this voltage is applied to SVCC pin. 3) When SVCC becomes higher than 4.2 V, the oscillation changes over from the internal oscillator to the triangular wave oscillator and SVCC is at 5 V. This becomes the power supply for the entire IC and the whole IC starts its operations.
Power supply pin for 2 systems VBAT: Lithium secondary battery, unit-3 type 4 pcs. VBATL: Unit-3 type battery 2 pcs.
On/off controllable by control pin independent to all channels. CTL1 ch.1
1
Low voltage, overvoltage, temperature and output short-circuit protection circuit Reference voltage
VBATL
VBAT
in
CMOS
Triangle wave oscillator
PWM control
ar
SVCC ch.0 stepup Voltage Voltage ch.1 stepup 1
Output
Error amplifier CTL2 ch.2
2
PWM comparator
lim
Error amplifier Error amplifier Error amplifier Error amplifier Error amplifier
CMOS
Output
PWM comparator CMOS
CTL3 ch.3
3
Output
CMOS
PWM comparator
Pr e
4
CTL4 ch.4
Output
PWM comparator CMOS
ch.5
5
Output
PWM comparator CMOS PWM comparator
ch.6
6
Output
+ side of error amplifier is connected to the reference voltage of IC to set the output voltage.
Figure 1. Configuration example
Note) Voltage set-up: Transform to a voltage higher than supply voltage Voltage step-down: Transform to a voltage lower than supply voltage
y
Ch.1: Exclusive-use for diode method voltage step-up Ch.2: Synchronous rectification method Voltage step-up or stepdown is automatically set by power supply pin selection VBAT pin: Step-down VBATL pin: Step-up Ch.3: Voltage step-down Synchronous rectification method Ch.4, ch.5: Transformer drive * Usage: LCD, CCD drive * Output number and voltage are determined by transformer design Ch.6: For diode method voltage step-up ch.2 Voltage
step-up/ step-down 2
Incorporating various protection circuit Low voltage, overvoltage, temperature and output short-circuit
Power supply CTL0
ch.3 Voltage stepdown
3
ch.4 Transformer drive
4
ch.5 Transformer drive
5
ch.6 Voltage stepup 6
SDH00015EEB
21
AN30210A
Application Notes (continued)
[1] Functional outline descriptions (continued) 2. Outline of rise time operation (Refer to the rise time timing chart on the next page) 1) Connect the power supply to VBATL pin (pin 47) (1.5 V to 4.6 V) or VBAT pin (pin 48) (2.8 V to 7.2 V). 2) When ch.0 (power supply for IC drive) control pin (CTL0: Pin17) is turned on, the pulse voltage output is given to DRV0 pin (pin 25) by the PWM control circuit and the voltage of IC power supply pin SVCC (pin 44) rises. * Since the timer of the short-circuit protection circuit for ch.0 operates for the period until ch.0 error amplifier output voltage (EO0: pin 53) stabilizes, consideration should be given to the rise setting of each part. (SCP0 pin voltage increases due to the charging of timer setting capacitor connected to SCP0 pin (pin 46)). (Refer to "[2] Functional Descriptions of Each Block 6. Timer latch type short-circuit protection circuit block for ch.0") * IC output pin voltage of each channel is not generated until each CTL pin is turned on. 3) After turning on the control pin of each channel, the PWM output pulse voltage is given from IC output pin of each channel and the power supply circuit output voltage of each channel is generated. * Since the timer of the short-circuit protection circuit for ch.1 to ch.6 operates (SCP pin: pin 60 voltage increase) for the period until the error amplifier output voltage of each channel (EO1 to EO6) stabilizes, consideration should be given to the rise setting of each part. (Refer to "[2] Functional descriptions of each block 7. Timer latch type short-circuit protection circuit block for ch.1 to ch.6") 4) If any one of the power supply circuit output pin voltages of ch.1 to ch.6 drops in the steady-state due to overloading or short circuiting, the error amplifier output voltage of relevant channel increases and the timer of the short-circuit protection circuit for ch.1 to ch.6 operates. * If SCP pin voltage becomes a value higher than the threshold, ch.1 to ch.6 PWM output pulse stops so as to turn off the power supply circuit. (1) When TOSH pin (pin 24) is high: All channels stop simultaneously. (2) When TOSH pin (pin 24) is low: Only the short circuited channel stops. (Refer to "[2] Functional descriptions of each block 7. Timer latch type short-circuit protection circuit block for ch.1 to ch.6") 5) If SVCC voltage drops to a point under 4.0 V due to overloading or short circuiting, the PWM pulse of ch.1 to ch.6 stops. Moreover the timer of the short-circuit protection circuit for ch.0 starts, and the voltage of the terminal SCP0 rises when the output of EO0 becomes more than the threshold voltage. The PWM pulse of ch.0 stops when the voltage of the terminal SCP0 becomes more than the threshold voltage. Ch.0 PWM pulse stops so as to turn off the power supply circuit. (Refer to "[2] Functional descriptions of each block 6. Timer latch type short-circuit protection circuit block for ch.0")
Pr e
22
lim
SDH00015EEB
in
ar
y
AN30210A
Application Notes (continued)
[1] Functional outline descriptions (continued) 3. Rising timing chart (typical chart) 1
VBAT or VBATL switch on
CTL0 pin
Off
VBAT pin VBATL pin
CTL0 pin on
VBAT , VBATL Low voltage protection circuit stop voltage (No circuit operation at lower than this voltage)
VBAT: 2.23 V (typ.)/VBATL: 1.338 V (typ.)
5 V (typ.) Ch.0 SVCC pin IC drive power supply
SVCC low voltage protection circuit cancel (4.2 V typ.)
The oscillation wave forms for PWM output
SS0 pin Max. duty EO0 pin
Ch.0 PWM output
in
ch.1 to ch.6 in steady-state
Each SS1 to SS6 pin Each EO1 to EO6 pin CT pin Each ch.1 to ch.6 PWM output Each CTL1 to CTL6 pin Ch.0 Short-circuit protection SCP0 pin Ch.1 to ch.6 Short-circuit protection SCP pin
Pr e
Off
1) 2)
Ch.0 soft start output rise operation Short-circuit protection circuit operates until the output stabilizes. Power supply connection VBAT or VBATL
lim
On
3)
The oscillation wave forms for PWM output
Ch.1 to ch.6 rise Short-circuit protection circuit operates until and output stabilizes.
Note) For 1) to 4), refer to the description on the previous page.
ar
Output short-circuit occurrence
y
4)
Ch.1 to ch.6 Short-circuit protection circuit operation
SS0 pin voltage
Max. Duty setting voltage Error amplifier output voltage (EO0)
Error amplifier output voltage Each EO1 to EO6 Each SS1 to SS6 pin voltage
Ch.0 timer latch Short-circuit protection threshold voltage 1.24 V/1.217 V Ch.1 to ch.6 timer latch Short-circuit protection threshold voltage 1.269 V All outputs stop or short circuited channels stop
SDH00015EEB
23
AN30210A
Application Notes (continued)
[1] Functional outline descriptions (continued) 4. Rising timing chart (typical chart) 2: Short-circuit protection circuit operation for ch.0
VBAT or VBATL switch on CTL0 pin Off VBAT pin VBATL pin Ch.0 pin on VBAT , VBATL Low voltage protection circuit stop voltage VBAT: 2.23 V (typ.)/VBATL: 1.338 V (typ.) SVCC pin output short-circuit occurrence Short-circuit protection circuit operation start for ch.0 Ch.0 SVCC pin IC drive power supply 5 V (typ.) 4.2 V (typ.)
SVCC low voltage protection circuit cancel (4.2 V typ.)
SS0 pin voltage
The oscillation wave forms for PWM output SS0 pin Max. duty EO0 pin
Ch.0 PWM output
lim
in
Ch.0 timer latch Short-circuit protection threshold voltage 1.24 V/1.217 V 5) All outputs stop 1) 2)
Ch.0 Soft start output rise operation Short-circuit protection circuit operates until the output stabilizes. Ch.0 Short-circuit protection circuit operation
Ch.0 Short-circuit protection SCP0 pin
[2] Function descriptions of each block 1. Reference voltage block This block consists of band gap circuit and provides 1.26 V (typ.) reference voltage output with a temperature compensation accuracy of 1%. The reference voltage is stabilized at a supply voltage (SVCC ) over 4.2 V (typ.). This voltage is used as the reference voltage for error amplifier 0 to 6, the regulator amplifier and the short-circuit protection circuit, etc. 2. Triangular wave oscillation block 1) PWM operation After ch.0 (Built-in IC power supply) start up, the triangular wave with high wave value of approx. 1.40 V and low wave value of approx. 0.55 V by the timing capacitor on CT pin (pin 56) and RT pin (pin 57) connection resistor is generated, and the connection is made inside the IC to the non-reverse input of PWM comparator of each channel.
Pr e
Power supply connection VBAT or VBATL
24
SDH00015EEB
ar
y
0V
Error amplifier output voltage (EO0)
Max. duty setting voltage
AN30210A
Application Notes (continued)
[2] Functional descriptions of each block (continued) 2. Triangular wave oscillation block (continued) 2) PWM operation (continued) fOSC = IO = 2 x 1 IO = t1 + t2 2 x CT x (VCTH - VCTL) VRT =2 x VREF Charge VCTH
VCTL t1 t2 Discharge
RT RT VCTH - VCTL = 0.85 V 1 f [Hz] 0.67 x CT x RT
T Figure 2. Triangular oscillation waveform
Notes) When setting the oscillation frequency, the recommended value for the timing capacitor connected to CT pin (pin 56) is 180 pF and the resistor to RT pin (pin 57) is 33 k.
4. SVCC low voltage protection circuit block This part protects the system from breakdown or degradation due to a malfunction control in the generation transition state of the internal power supply of IC (SVCC) by the ch.0 (Built-in IC power supply) start and stop. For the period until SVCC pin voltage (ch.0 output voltage) (pin 44) reaches 4.2 V (typ.) in its rise time, the output drive transistor is cut off (100% quiescent period) by setting SCP0 pin (pin 46), each SS pin (pin 7 to pin 12) and each EO pin (pin 55, pin 62, pin 50, pin 64, pin 2 and pin 4) at 0 V.
Pr e
3. VBAT , VBATL low voltage protection circuit block This part protects the system from breakdown or degradation due to a malfunction control in the transition state of VBAT or VBATL start and stop. 1) VBAT input time For the period until VBAT pin (pin 48) voltage reaches 2.28 V (typ.) in its rise time, and when it goes below 2.23 V in its fall time, ch.0 (internal power supply of IC) output is completely stopped by cutting off the bias to the startup oscillation circuit. 2) VBATL input time For the period until VBATL pin (pin 47) voltage reaches 1.418 V (typ.) in its rise time, and when it goes below 1.338 V in its fall time, ch.0 (internal power supply of IC) output is completely stopped by cutting off the bias to the startup oscillation circuit.
lim
in
3) Frequency change-over It is possible to change over the triangular oscillation frequency by COCS pin (Pin32) setting. (1) COCS pin is high: Oscillation frequency decreases (20 kHz typ.) (2) COCS pin is low: Oscillation frequency normal (550 kHz typ.)
ar
However, since the above equations are for the calculation when the oscillation frequency of the product specifications is at 550 kHz, the time for loosting charge if the frequency is variable, the amount of overshoot and under shoot are not taken into consideration. When the frequency is variable, the calculation value obtained from the above equations is just a standard. Confirm the final result with the actual equipment.
y
SDH00015EEB
25
AN30210A
Application Notes (continued)
[2] Functional descriptions of each block (continued) 4. SVCC low voltage protection circuit block (continued)
SVCC operation start voltage (4.2 V typ.) VBAT , VBATL operation start voltage VBAT: 2.30 V (typ.) VBATL: 1.433 V (typ.) SVCC VBAT , VBATL CT pin voltage waveform SS pin voltage waveform Error amplifier output voltage (EO)
Out pin voltage waveform
Figure 3. Low voltage protection circuit operation timing chart at VBAT , VBATL and SVCC start time (Typical chart)
5. Error amplifier block This part is the error amplifier for NPN transistor input. It detects the output voltage from the DC-DC converter and inputs the amplified signal to PWM comparator. The non-reverse input of each channel (reference side) is set at 1.26 V (typ.) of the internal reference voltage. It is possible to carry out an arbitrary gain setting and phase compensation by the connection of a resistor and capacitor between EO pin and IN pin of each channel.
* Ch.0 VO0 52 IN0 51
lim
PWM comparator VREF (1.26 V) PWM comparator VREF (1.26 V)
Pr e
Error amplifier EO0 53 * Ch.2 Ch.2 output Error amplifier IN2 61 EO2 62
26
in
* Ch.1 Ch.1 output * Ch.3 Ch.3 output
ar
IN1 54 EO1 55 VREF (1.26 V) IN3 49 EO3 50 VREF (1.26 V)
Ch.0 start up oscillation (f = 270 kHz typ.) (without output for ch.1 to ch.6)
Figure 4. Connection of each channel error amplifier
SDH00015EEB
y
Error amplifier PWM comparator Error amplifier PWM comparator
AN30210A
Application Notes (continued)
[2] Functional descriptions of each block (continued) 5. Error amplifier block (continued) * Ch.4 Ch.4 output Error amplifier PWM comparator VREF (1.26 V) * Ch.5 Ch.5 output Error amplifier PWM comparator VREF (1.26 V)
IN4 63
IN5 1
EO4 64 * Ch.6 Ch.6 output
EO5 2
IN6 3
Error amplifier PWM comparator VREF (1.26 V)
EO6 4
Figure 4. Connection of each channel error amplifier (continued) 1) Ch.0 part output voltage setting Ch.0 has a built-in voltage setting resistor so that the output voltage is set at 5.0 V (typ.). 2) Ch.1 to ch.6 part output voltage setting The voltage for ch.1 to ch.6 can be set by the connection of external voltage setting resistors as shown in the following diagram.
Ch.* output R1 IN*
lim
Error amplifier VREF (1.26 V)
6. Timer latch type short-circuit protection circuit block for ch.0 This block protects an external main switching device, flywheel diode and choke coil from breakdown or degradation if ch.0 output is maintained in an overloading or short circuiting condition for a certain period of time. This protection circuit recognizes a drop of ch.0 output, which is the IC's SVCC power supply, as short circuiting and operates the protection circuit. If ch.0 output voltage (SVCC ) drops and goes below the latch threshold voltage described later, the timer circuit is operated by the output reversing of the short-circuit detection comparator (S.C.P. comp.), and the protection enable capacitor externally attached to SCP0 pin (Pin46) starts charging. Unless ch.0 output voltage (SVCC ) returns to the normal voltage range (SVCC > 4.2 V) until the voltage of this capacitor reaches; with VBATL input: 1.24 V (typ.) with VBAT input: 1.217 V (typ.), the latch circuit is set, and the output drive transistor is cut off, and the quiescent period becomes 100%. SDH00015EEB 27
Pr e
R2 EO*
PWM comparator
Figure 5. Output voltage setting
in
ar
VOUT = VREF x R1 + R2 [V] R2 R1 + R2 = 1.26 V x [V] (typ.) R2
y
AN30210A
Application Notes (continued)
[2] Functional descriptions of each block (continued) 6. Timer latch type short-circuit protection circuit block for ch.0 (continued) Also, this short-circuit protection circuit stops all of them from ch.1 to ch.6 because of ch.0 output, that is SVCC , is short-circuit. The short-circuit protection can be canceled by either the following 1) or 2) method. 1) Once reduce VBATL (pin 47) or VBAT (pin 48) potential to a voltage below the lower threshold voltage limit of VBAT , VBATL low voltage protection circuit, and restart . 2) Bringing down CTL0 pin (pin 17) to low-level, and restart.
Note) When the power supply is started up, it is recognized as short-circuit state so that SCP0 pin voltage (pin 46) starts charging. For this reason, it is necessary to set SCP0 pin capacitance so as to start up DC-DC converter output voltage before the IC sets the short-circuit detection and latch circuit
Circuit operation stop voltage (4.2 V typ.) Short-circuit detection SVCC CT pin voltage waveform
Out pin voltage
in
Timer time TSCP0
SDH00015EEB
SCP0 pin voltage
Figure 6. Ch.0 output short-circuit protective operation timing chart (Typical chart)
7. Timer latch type short-circuit protection circuit block for ch.1 to ch.6 1) This block protects an external main switching device, flywheel diode and choke coil from breakdown or degradation if each output is maintained in an overloading or short circuiting condition for a certain period of time. This protection circuit detects short-circuit by the output signal of each error amplifier. If the output voltage of DC-DC converter drops and any one of the pin voltages of EO1 to EO6 (pin 55, pin 62, pin 50, pin 64, pin 2 and pin 4) exceeds 1.6 V (typ.), the timer circuit is operated by the output reversing of the short-circuit detection comparator (S.C.P. comp.), and the protection enable capacitor externally attached to SCP pin (pin 60) starts charging. Unless the error amplifier output voltage returns to the normal voltage range until the voltage of this capacitor reaches 1.268 V (typ.), the latch circuit is set, the output drive transistor is cut off and the quiescent period becomes 100%. The short-circuit protection can be canceled by either the following 1) or 2) method. (1) Once reduce VBATL (pin 47) or VBAT (pin 48) potential to a voltage below the lower threshold voltage limit of VBAT , VBATL low voltage protection circuit, and restart . (2) Bring down CTL0 pin (pin 17) to low-level, and restart. 28
Pr e
CSCP0 x VLTH0 CSCP0 x 1.24 CSCP0 x 106 = [s] (typ.) TSCP0 = = ICHG0 2.22 A 1.79 CSCP0 x VLTH0 CSCP0 x 1.217 CSCP0 x 106 * CSCP0: SCP0 pin connection capacitance = [s] (typ.) TSCP0 = = 2.22 A 1.82 ICHG0: SCP0 pin charge current ICHG0
lim
ar
VLTH0
Error amplifier output voltage (EO)
y
AN30210A
Application Notes (continued)
[2] Functional descriptions of each block (continued) 7. Timer latch type short-circuit protection circuit block for ch.1 to ch.6 (continued) 2) Total shutdown setting TOSH pin (pin 24) setting allows the selection of channels whose operation is stopped by the short-circuit protection circuit, either only short-circuit channel or all ch.0 to ch.6 channels. (1) TOSH pin (pin 24) is high: All channels shutdown (2) TOSH pin (pin 24) is low: Only short-circuit channel shutdown
Note) When the power supply is started up, it is recognized as short-circuit state so that SCP pin voltage (pin 60) starts charging. For this reason, it is necessary to set SCP pin capacitance so as to start up DC-DC converter output voltage before the IC sets the short-circuit detection and latch circuit. A care must be taken especially when applying the softstart because the startup time extends.
Output voltage
SS pin voltage waveform Error amplifier output voltage (EO)
in
SS* pin CSS
SDH00015EEB
Out pin voltage
SCP pin voltage
Figure 7. Ch.1 to ch.6 output short-circuit protective operation timing chart (Typical chart)
TSCP =
CSCP x VLTH CSCP x 1.268 CSCP x 106 = [s] (typ.) = ICHG 1.282 A 0.989
lim
8. PWM comparator block PWM comparator controls the output pulse On period according to the input voltage. It puts the output pin of each channel in high-level and turns on the output transistor during the period when the triangular wave voltage of CT pin (pin 56) is lower than each SS* pin voltage and each EO* pin voltage. The maximum duty ratio is internally set by the triangular wave voltage and each SS* pin setting voltage. The maximum duty ratio is internally set at 88% (typ.) for all channels. However, it can be set at any value from 0% to 100% by the connection of a resistor between each SS pin and SGND (pin 59) or VREF pin (pin 58). Also, the softstart which gradually expands the On period of the output pulse at the startup time operates by a capacitor connection between each SS pin and GND. * Max-Du setting equation
Pr e
MaxDu = where, RO2 VSS = VREF' x [V] RO1 + RO2 VCTH = 1.40 V (typ.) VCTL = 0.55 V (typ.) VREF' = 1.94 V (typ.)
VSS - VCTL x 100 [%] VCTH - VCTL
ar
VLTH Timer time TSCP
* CSCP: SCP pin connection capacitance ICHG: SCP pin charge current
Figure 8. Output Du and softstart setting diagram
y
0V
CT pin voltage waveform
VREF' RO1 IC built-in resistance RO2
29
AN30210A
Application Notes (continued)
[2] Functional descriptions of each block (continued) 8. PWM comparator block (continued)
CT pin voltage VCTH SS pin voltage Error amplifier output VCTL Out pin voltage
Softstart time
Maximum duty
lim
VBAT2 25
PWM1 28 Out1
9. Ch.0 output part 1) Operational explanation (1) Output circuit is open drain configuration. (2) Exclusive-use for voltage step-up circuit (3) Output stage has built-in power MOSFET (N-ch.) and on-state resistance is 1.2 (max.). (4) Exclusive-use for IC's internal power supply and the setting voltage is 5 V. * The circuit block of ch.0 output part and the peripheral circuit example are shown in figure 10.
26 PGND0
Figure 10 10. Ch.1 output part 1) Operational explanation (1) Output circuit is CMOS configuration. * The circuit block of ch.1 output part and the peripheral circuit example are shown in figure 11.
21 PVCC1
Pr e
30 PGND1
30
SDH00015EEB
in
VBAT VBATL VCC VO0 DRV0
Tr1 Figure 11
ar
VCC VBAT VBATL Out IN1
Actually measured value and calculated value may not agree due to the delay of PWM comparator operation and the shift of VCTH , VXTL value of triangular wave oscillation. Adjust with actually mounted circuit board.
y
Figure 9. PWM comparator operation and softstart operation timing chart (Typical chart)
AN30210A
Application Notes (continued)
[2] Functional descriptions of each block (continued) 11. Ch.2 output block 1) Operational explanation (1) The output circuit is synchronous rectification method. (2) The output stage for both HO2 (pin 22) and LO2 (pin 19) is CMOS configuration. (3) It is set up at either the voltage step-up or step-down by the selection of the the supply voltage connection pin. i) If the power supply is connected to VBATL pin (pin 47), it is set at the voltage step-up. ii) If the power supply is connected to VBAT pin (pin 48), it is set at the voltage step-down. (4) The setting of PNSW2 pin (pin 13) allows the selection of either N-ch. or P-ch. for the HO2 output driven external SW device. i) PNS pin is high: P-ch. FET drive (connect to PVCC2 ) ii) PNS pin is low: N-ch. FET drive (connect to MO2) (5) The synchronous rectification is stopped by STOP pin (pin 18) setting. i) STOP pin is high: Synchronous rectification stops a) Voltage step-up time: HO2 output stops b) Voltage step-down time: LO2 output stops At that time, a rectification diode is required in place of the stopped FET. ii) STOP pin is low: Synchronous rectification operates The synchronous rectification stop is performed at the same time with ch.3.
in
13 PNSW2 23 PVCC2 22 HO2 20 MO2 19 LO2 Tr2 18 STOP
2) Voltage step-up time * Ch.2 output part circuit block and the voltage step-up time peripheral circuit example are shown in figure 12.
lim
Dead time cont. PVCC1 PGND1
Voltage step-up/ step-down changeover PWM2
Pr e
Figure 12 (1) PWM output voltage * The PWM output voltage is supplied from HO2 pin (pin 22) and LO2 pin (pin 19) to drive FET Tr1 and Tr2 respectively. Both pin voltages are as shown in figure 13. * When Tr2 is On, the current flows through the path from the power supply (VBATL ) coil Tr2 GND and the electric power is supplied to the coil. At this time, Tr1 is Off. HO2 Tr1 On * Next when Tr2 is Off, Tr1 goes On, and the electric pin voltage power accumulated in the coil is supplied to the outOff put through Tr1. LO2 (2) Quiescent period pin voltage Tr2 On * The PMW output voltages given from HO2 pin (pin 22) and LO2 (pin 19) are provided with the quiesOff cent period td in which both become off state as shown in figure 13. This is provided for the preventd : 80 ns (typ.) td td tion of simultaneous turning On of Tr1 and Tr2. Figure 13
SDH00015EEB
ar
D L Tr1
y
VCC VBATL Out IN2
31
AN30210A
Application Notes (continued)
[2] Functional descriptions of each block (continued) 11. Ch.2 output block (continued) 3) Voltage step-down time * Ch.2 output part circuit block and the voltage step-down time peripheral circuit example are shown in figure 14.
13 PNSW2 Voltage step-up/ step-down changeover PWM2 Dead time cont. 23 PVCC2 22 HO2 20 MO2 PVCC1 19 LO2 PGND1 Tr2 18 STOP Figure 14 Tr1 VCC VBAT Out
Pr e
32
(1) PWM output voltage * The PWM output voltage is supplied from HO2 pin (pin 22) and LO2 pin (pin 19) to drive FET Tr1 and Tr2 respectively. Both pin voltages are as shown in figure 15. * When Tr1 is On, the current flows through the path from the power supply (VBAT ) Tr1 coil HO2 Tr1 On output and the electric power is supplied to the coil. pin voltage At this time, Tr2 is off. Off * Next when Tr1 is Off, Tr2 goes On, and the electric LO2 power accumulated in the coil is supplied to the outTr2 On pin voltage put through Tr2. (2) Quiescent period Off * As same as the case of voltage step-up, the PMW output voltages given from HO2 pin (pin 22) and td: 80 ns (typ.) td td LO2 (pin 19) are provided with the quiescent peFigure 15 riod td in which both become Off state as shown in figure 15. This is provided for the prevention of simultaneous turning on of Tr1 and Tr2.
lim
SDH00015EEB
in
ar
y
IN2
AN30210A
Application Notes (continued)
[2] Functional descriptions of each block (continued) 11. Ch.2 output block (continued) 4) Bootstrap circuit A bootstrap circuit is provided for driving N-ch. MOSFET: Tr1. This bootstrap circuit is provided for keeping the gate-source voltage of N-ch. MOSFET: Tr1 over the gate threshold voltage by increasing highlevel of HO2 pin (pin 22) to a voltage higher than Vcc when N-ch. MOSFET: Tr1 is On. (1) Operational explanation of bootstrap circuit i) Voltage step-up case
D L 22 HO2 20 MO2 PVCC1 19 LO2 PGND1 Tr2 Out IN2 CB Tr1 [Each part voltage outline chart] VCC
HO2 LO2 PVCC2 VCC VOUT VBATL GND
23 PVCC2
MO2 VON2
a) Off period of N-ch MOSFET (Tr1) * N-ch MOSFET (Tr2) is On (LO2: High) in the period when Tr1 is Off, and the source voltage (VMO2 ) of Tr1 corresponds to a portion of Tr2 (VON2 ) voltage drop which is approximately equal to GND voltage. (*1) * When the forward voltage of diode D is VD , the potential VPVCC2 of IC's internal output circuit power supply PVCC2 becomes; VPVCC2 = VCC - VD and the charge voltage VCB of capacitor CB for bootstrap becomes; VCB = (VPVCC2 ) - VON2 VCC - VD b) On-period of N-ch MOSFET (Tr1) * Tr2 is Off in the period when Tr1 is On, and the current is being supplied from the power supply VBATL to the output through coil L and Tr1. When the voltage drop of Tr1 is VON1 , the source voltage (VMO2 ) of Tr1 becomes; VMO2 = VOUT + VON1 and it approximately equal to the output voltage (VOUT ). (*1) * The potential VPVCC2 of IC's internal output circuit power supply PVCC2 is maintained because the capacitor for bootstrap CB is being charged for the period t1 so that it becomes; VPVCC2 = VMO2 + VCB * The voltage (VHO2 ) of the output pin HO2 of IC is at the voltage approximately equal to the power supply voltage PVCC2 since the output circuit inside the IC is high. Therefore, VGS1 which is the gate-source voltage of Tr1 is; VGS1 = VHO2 - VMO2 VPVCC2 - VMO2 = VCB here, VCB is charged at VCC - VD during the Off period of Tr1 so that the voltage sufficient to turn On Tr1 can be maintained.
Note) *1 : It is desirable to use MOSFET with low On resistance for Tr1/Tr2.
Pr e
lim
in
Figure 16
ar
a b
y
VD
SDH00015EEB
33
AN30210A
Application Notes (continued)
[2] Functional descriptions of each block (continued) 11. Ch.2 output block (continued) 4) Bootstrap circuit (continued) (1) Operational explanation of bootstrap circuit (continued) ii) Voltage step-down case [Each part voltage outline chart] 23 PVCC2 Tr1 22 HO2 20 MO2 PVCC1 19 LO2 PGND1 Tr2 Figure 17 VCC CB Out
MO2 HO2 LO2 PVCC2 VCC VBAT VOUT
VD
a) Off period of N-ch MOSFET (Tr1) * N-ch MOSFET (Tr2) is On (LO2: High) in the period when Tr1 is Off, and the source voltage (VMO2) of Tr1 corresponds to a portion of Tr2 (VON2) voltage drop which is approximately equal to GND voltage. (*2) * When the forward voltage of diode D is VD , the potential VPVCC2 of IC's internal output circuit power supply PVCC2 becomes; VPVCC2 = VCC - VD and the charge voltage VCB of capacitor CB for bootstrap becomes; VCB = (VPVCC2) - VON2 VCC - VD b) On-period of N-ch MOSFET (Tr1) * Tr2 is Off in the period when Tr1 is On, and the current is being supplied from the power supply VBAT to the output through coil L and Tr1. When the voltage drop of Tr1 is VON1 , the source voltage (VMO2 ) of Tr1 becomes; VMO2 = VBAT - VON1 and it approximately equal to the output voltage (VBAT ). (*2) * The potential VPVCC2 of IC's internal output circuit power supply PVCC2 is maintained because the capacitor for bootstrap CB is being charged for the period t1 so that it becomes; VPVCC2 = VMO2 + VCB * The voltage (VHO2 ) of the output pin HO2 of IC is at the voltage approximately equal to the power supply voltage PVCC2 since the output circuit inside the IC is high. Therefore, VGS1 which is the gate-source voltage of Tr1 is; VGS1 = VHO2 - VMO2 VPVCC2 - VMO2 = VCB here, VCB is charged at VCC - VD during the Off period of Tr1 so that the voltage sufficient to turn On Tr1 can be maintained.
Note) *2 : It is desirable to use MOSFET with low On resistance for Tr1/Tr2.
Pr e
34
lim
SDH00015EEB
in
ar
y
a b
VON2
GND
AN30210A
Application Notes (continued)
[2] Functional descriptions of each block (continued) 11. Ch.2 output block (continued) 4) Bootstrap circuit (continued) (2) Bootstrap circuit usage notes i) Operating power supply voltage range Use an operating power supply voltage with a sufficient margin since PVCC2 pin voltage (pin 23) exceeds VCC as shown below when N-ch. MOSFET (Tr1), being a switching device, is turned on. VPVCC2 VMO2 + VCC - VD VCC + VOUT + VON1 - VD: Voltage step-up time VPVCC2 VMO2 + VCC - VD VCC + VBAT - VON1 - VD: Voltage stap-down time ii) Bootstrap capacitor constant setting The bootstrap capacitor pulls up PVCC2 pin voltage to a point over VCC by capacitance coupling with the source side of N-ch. MOSFET when it is turn-on. At this time, the bootstrap capacitor is discharged by the gate drive current of N-ch. MOSFET. A too small capacitance value setting for the bootstrap capacitor may cause the efficiency drop due to switching loss increase. Therefore, a sufficiently large capacitance setting value should be taken as compared with the gate input capacitance. 12. Ch.3 output block 1) Operational explanation (1) The output circuit is synchronous rectification method. (2) The output stage is CMOS configuration for both HO3 (pin 33) and LO3 (pin 29). (3) Exclusive-use for voltage step-down circuit. (4) The setting of PNSW3 pin (pin 45) allows the selection of either N-ch. or P-ch. for the HO3 output driven external SW device. i) PNSW pin is high: P-ch. FET drive (connect to PVCC3 ) ii) PNSW pin is low: N-ch. FET drive (connect to MO3) (5) LO3 (pin 29) output is turned off and the synchronous rectification is stopped by setting of STOP pin (pin 18). i) STOP pin is high: Synchronous rectification stops At that time, a rectification diode is required in place of the stopped FET. ii) STOP pin is low: Synchronous rectification operates The synchronous rectification stop is carried out simultaneously with ch.2. (6) The circuit operation is similar to ch.2 voltage step-down circuit. (7) The quiescent period is also similar to ch.2 voltage step-down circuit. (8) The bootstrap circuit is also similar to ch.2 voltage step-down circuit.
Pr e
PWM3 Dead time cont. PVCC1 PGND1
lim
45 PNSW3 34 PVCC3 33 HO3 31 MO3 29 LO3 18 STOP
in
Tr1 Tr2 Figure 18
Refer to the items for ch.2 for the concrete circuit operations.
ar
VCC VBAT VBATL Out IN3
y
SDH00015EEB
35
AN30210A
Application Notes (continued)
[2] Functional descriptions of each block (continued) 13. Ch.4 output block 1) Operational explanation (1) Output circuit is CMOS configuration. The circuit block of ch.4 to ch.6 output part and the peripheral circuit example are shown in figure 19.
PVCC1 VBAT VBATL Out Tr1 IN4 to IN6
PWM4 to PWM6 DRV4 to DRV6
PGND1 Figure 19
Pr e
VREF
15. Regulator amplifier block 1) Operational explanation (1) A regulator amplifier is built in this IC which makes up a three terminal voltage regulator by the connection of an external PNP transistor to DI pin (pin 43) and DO pin (pin 41). Ch.0 output is exclusive-use for voltage step-up circuit control. Therefore, if the power supply input is from VBAT pin, it is possible to maintain ch.0 output in stabile state by using the regulator amplifier as shown below. (2) Output circuit is open drain configuration. (3) Output sink current is 20 mA (typ.). The circuit block of the regulator output part and the peripheral circuit example are shown in figure 20. 43 DI 42 DEI 41 DO 25 DRV0 29 PGND0 VBAT
lim
14. CTL block Each ch.0 to ch.6 channel turns On each time by bringing CTL* pin (CTL0 to CTL6) for each ch.0 to ch.6 to high-level. Each channel turns Off if CTL* pin is brought to low-level (< 0.3 V). 1) The maximum applied voltage for each CTL* pin: Bring it under SVCC (pin 44) + 0.1 V 2) This IC's ch.0 output is IC's power supply (SVCC ) so that On/Off operation of other channels can not be performed unless ch.0 is started up.
36
SDH00015EEB
in
Figure 20
ar
SVCC
y
AN30210A
Application Notes (continued)
[2] Functional descriptions of each block (continued) 16. Overvoltage protection circuit block The protection circuit stops ch.0 output completely by cutting off the bias to the startup oscillation circuit if VBATL pin (pin 47) voltage exceeds 4.2 V (typ.). 17. Thermal protection circuit block This IC is incorporating the built-in temperature detection circuit. The protection circuit stops all channel outputs completely by cutting off the bias to the startup oscillation circuit if the temperature inside the IC exceeds 125C (typ.). 18. Assist driver circuit block 1) Operational explanation (1) The output circuit is CMOS configuration. (2) As the supplement to ch.0, an external power transistor is connected and used in parallel with ch.0. The output part circuit block is shown in figure 21.
25 DRV0
26 PGND0 PWM0 VBAT Asisut driver 27
Pr e
lim
in
Figure 21
ASIST
ar
37
SDH00015EEB
y
AN30210A
Application Circuit Example
* Application circuit example 1 (4 pcs of unit-3 battery: 3.6 V to 7.2 V)
SCP VREF 58 60 COSC 32
(H:Frequency down)
H-start RT 57 56
1.40 V 0.55 V
SCP0
CT 17
CTL0 46 44 SVCC 48 VBAT
Voltage descent Overvoltage
(POR) S Q S.C.P.0 DisC R
VREF 1.26 V (allowance: 1%) VREF
VCC U.V.L.O.
(Voltage down: L)
OSC
(VBATL input: H)
(High temperature: H) Temp. det. TOSH 24 (H :Total shut-down) (POR) VREF
R S Q Q
(Overvoltage: L)
VBAT U.V.L.O. 1.5 V/ 2.5 V (Voltage down: L)
47 VBATL 43 DI 42 DEI 41 DO
Latch VREF
1.6V PWM0
(DisC)
y
25 DRV0 26 PGND0 27 ASIST 6 SS0 52 VO0 53 EO0 51 IN0 21 PVCC1 28 Out1 30 7 13 23 22 20 19 8 45 18 34 33 31 29 PGND1 SS1 PNSW2 PVCC2 HO2 MO2 LO2 SS2 PNSW3 STOP PVCC3 HO3 MO3 LO3 VCC VCC 9 SS3 5 SS VBAT PVCC1 16 DRV4
PGND1
VCC
ar
VREF VO0 VREF Error amp.0 Dead time PVCC1 cont.
PGND1
Voltage step-up for IC drive VCC
5 V/0.05 A
(POR) Latch
1.6 V
in
PWM1 PWM2 PWM3 Dead time cont. PVCC1
PGND1
EO1 VO1
55 VREF 54
S.C.P. comp.
R S
Q Q
VBAT Voltage step-up IN1
Ch.1 5 V/1 A
VREF Error amp.1 (POR) Latch
lim
R S Q Q
IN1 35 CTL1 H-start
1.6 V
EO2 VO2
62 VREF 61
S.C.P. comp.
VBAT
Voltage step-up/down SW (at step-down)
Ch.2 3.3 V/0.5 A
VREF
IN2
IN2 36 CTL2 H-start
1.6 V
Error amp.2
(POR) Latch EO3 VO3 50 VREF 49 S.C.P. comp.
R S Q Q
VBAT Voltage step-down IN3
Ch.3 1.5 V/0.3 A 1.8 V/0.3 A
IN3 37 CTL3 H-start EO4 VO4
Pr e
Error amp.3 (POR) Latch
R S Q Q 1.6 V
VREF
Transformer drive IN4
Ch.4-1 CCD main (15 V/30 mA) Ch.4-2 CCD sub (-8 V/10 mA)
64 VREF 63
S.C.P. comp.
VREF PWM4
CTL4 H-start EO5 VO5 CTL5 H-start EO6 VO6
IN4 38
Error amp.4
(POR) Latch
1.6 V
10 SS4
2 VREF 1
S.C.P. comp.
R S
Q Q
VBAT IN5
Transformer drive
Ch.5-1 LCD (12.4 V/30 mA) Ch.5-2 LCD (3.7 V/60 mA)
VREF PWM5 Error amp.5 (POR) Latch
PVCC1 15 DRV5
PGND1
IN5 39
1.6 V
11 SS5 VBAT 14 DRV6 IN6
4 VREF 3
S.C.P. comp.
R S
Q Q
PVCC1 VREF PWM6
Voltage step-up
Ch.6 Back light 7 V/100 mA
PGND1
IN6 40 CTL6 H-start
Error amp.6 59 SGND
12 SS6
38
SDH00015EEB
AN30210A
Application Circuit Example (continued)
* Application circuit example 2 (Li secondary battery -1: 2.8 V to 4.2 V) * Ch.2, ch.3 output FET (High-side): Using N-ch. FET
SCP VREF 58 60 COSC 32
(H:Frequency down)
H-start RT 57 56
1.40 V 0.55 V
SCP0
CT 17
CTL0 46 44 SVCC 48 VBAT
Voltage descent Overvoltage
(POR) S Q S.C.P.0 DisC R
VREF 1.26 V (allowance: 1%) VREF
VCC U.V.L.O.
(Voltage down: L)
OSC
(VBATL input: H)
(High temperature: H) Temp. det. TOSH 24 (H :Total shut-down) (POR) VREF
R S Q Q
(Overvoltage: L)
VBAT U.V.L.O. 1.5 V/ 2.5 V (Voltage down: L)
47 VBATL 43 DI 42 DEI 41 DO
Latch VREF
1.6V PWM0
(DisC)
y
25 DRV0 26 PGND0 27 ASIST 6 SS0 52 VO0 53 EO0 51 IN0 21 PVCC1 28 Out1 30 7 13 23 22 20 19 8 45 18 34 33 31 29 PGND1 SS1 PNSW2 PVCC2 HO2 MO2 LO2 SS2 PNSW3 STOP PVCC3 HO3 MO3 LO3 VCC VO1 VCC 9 SS3 5 SS VBAT PVCC1 16 DRV4
PGND1
ar
VREF VO0 VREF Error amp.0 Dead time PVCC1 cont.
PGND1
VCC
Voltage step-up for IC drive VCC
5 V/0.05 A
(POR) Latch
1.6 V
in
PWM1 PWM2 PWM3 Dead time cont. PVCC1
PGND1
EO1 VO1
55 VREF 54
S.C.P. comp.
R S
Q Q
VBAT VO1 Voltage step-up IN1
Ch.1 5 V/1 A
VREF Error amp.1
IN1 35 CTL1 H-start
1.6 V
(POR) Latch S.C.P. comp.
R S Q Q
lim
VREF
R S Q Q R S Q Q
EO2 VO2
62 VREF 61
Voltage step-up/down SW (at step-down)
Ch.2 3.3 V/0.5 A
IN2
IN2 36 CTL2 H-start
1.6 V
Error amp.2
(POR) Latch EO3 VO3 50 VREF 49 S.C.P. comp.
Pr e
Error amp.3 (POR) Latch
1.6 V
VBAT Voltage step-down IN3
Ch.3 1.5 V/0.3 A 1.8 V/0.3 A
CTL3 H-start EO4 VO4
IN3 37
VREF
Transformer drive IN4
Ch.4-1 CCD main (15 V/30 mA) Ch.4-2 CCD sub (-8 V/10 mA)
64 VREF 63
S.C.P. comp.
VREF PWM4
CTL4 H-start EO5 VO5 CTL5 H-start EO6 VO6
IN4 38
Error amp.4
(POR) Latch
1.6 V
10 SS4
2 VREF 1
S.C.P. comp.
R S
Q Q
VBAT IN5
Transformer drive
Ch.5-1 LCD (12.4 V/30 mA) Ch.5-2 LCD (3.7 V/60 mA)
VREF PWM5 Error amp.5 (POR) Latch
PVCC1 15 DRV5
PGND1
IN5 39
1.6 V
11 SS5 VBAT 14 DRV6 IN6
4 VREF 3
S.C.P. comp.
R S
Q Q
PVCC1 VREF PWM6
Voltage step-up
Ch.6 Back light 7 V/100 mA
PGND1
IN6 40 CTL6 H-start
Error amp.6 59 SGND
12 SS6
SDH00015EEB
39
AN30210A
Application Circuit Example (continued)
* Application circuit example 3 (Li secondary battery -2: 2.8 V to 4.2 V) * Ch.2, ch.3 output FET (High-side): Using P-ch. FET
SCP VREF 58 60 COSC 32
(H:Frequency down)
H-start RT 57 56
1.40 V 0.55 V
SCP0
CT 17
CTL0 46 44 SVCC 48 VBAT
Voltage descent Overvoltage
(POR) S Q S.C.P.0 DisC R
VREF 1.26 V (allowance: 1%) VREF
VCC U.V.L.O.
(Voltage down: L)
OSC
(VBATL input: H)
(High temperature: H) Temp. det. TOSH 24 (H :Total shut-down) (POR) VREF
R S Q Q
(Overvoltage: L)
VBAT U.V.L.O. 1.5 V/ 2.5 V (Voltage down: L)
47 VBATL 43 DI 42 DEI 41 DO
Latch VREF
1.6V PWM0
(DisC)
y
25 DRV0 26 PGND0 27 ASIST 6 SS0 52 VO0 53 EO0 51 IN0 21 PVCC1 28 Out1 30 7 13 23 22 20 19 8 45 18 34 33 31 29 PGND1 SS1 PNSW2 PVCC2 HO2 MO2 LO2 SS2 PNSW3 STOP PVCC3 HO3 MO3 LO3 VO1 VO1 9 SS3 5 SS VBAT PVCC1 16 DRV4
PGND1
ar
VREF VO0 VREF Error amp.0 Dead time PVCC1 cont.
PGND1
VCC
Voltage step-up for IC drive VCC
5 V/0.05 A
(POR) Latch
1.6 V
in
PWM1 PWM2 PWM3 Dead time cont. PVCC1
PGND1
EO1 VO1
55 VREF 54
S.C.P. comp.
R S
Q Q
VBAT VO1 Voltage step-up IN1
Ch.1 5 V/1 A
VREF Error amp.1
IN1 35 CTL1 H-start
1.6 V
(POR) Latch S.C.P. comp.
R S Q Q
lim
VREF
R S Q Q R S Q Q
EO2 VO2
62 VREF 61
Voltage step-up/down SW (at step-down) IN2
Ch.2 3.3 V/0.5 A
IN2 36 CTL2 H-start
1.6 V
Error amp.2
(POR) Latch EO3 VO3 50 VREF 49 S.C.P. comp.
Pr e
Error amp.3 (POR) Latch
1.6 V
Voltage step-down IN3
Ch.3 1.5 V/0.3 A 1.8 V/0.3 A
CTL3 H-start EO4 VO4
IN3 37
VREF
Transformer drive IN4
Ch.4-1 CCD main (15 V/30 mA) Ch.4-2 CCD sub (-8 V/10 mA)
64 VREF 63
S.C.P. comp.
VREF PWM4
CTL4 H-start EO5 VO5 CTL5 H-start EO6 VO6
IN4 38
Error amp.4
(POR) Latch
1.6 V
10 SS4
2 VREF 1
S.C.P. comp.
R S
Q Q
VBAT IN5
Transformer drive
Ch.5-1 LCD (12.4 V/30 mA) Ch.5-2 LCD (3.7 V/60 mA)
VREF PWM5 Error amp.5 (POR) Latch
PVCC1 15 DRV5
PGND1
IN5 39
1.6 V
11 SS5 VBAT 14 DRV6 IN6
4 VREF 3
S.C.P. comp.
R S
Q Q
PVCC1 VREF PWM6
Voltage step-up
Ch.6 Back light 7 V/100 mA
PGND1
IN6 40 CTL6 H-start
Error amp.6 59 SGND
12 SS6
40
SDH00015EEB
AN30210A
Application Circuit Example (continued)
* Application circuit example 4 (2 pcs of unit-3 battery -1 : 1.5 V to 3.6 V) * Ch.2, ch.3 output FET (High-side): Using N-ch. FET
SCP VREF 58 60 COSC 32
(H:Frequency down)
H-start RT 57 56
1.40 V 0.55 V
SCP0
CT 17
CTL0 46 44 SVCC 48 VBAT
Voltage descent Overvoltage
(POR) S Q S.C.P.0 DisC R
VREF 1.26 V (allowance: 1%) VREF
VCC U.V.L.O.
(Voltage down: L)
OSC
(VBATL input: H)
(High temperature: H) Temp. det. TOSH 24 (H :Total shut-down) (POR) VREF
R S Q Q
(Overvoltage: L)
VBAT U.V.L.O. 1.5 V/ 2.5 V (Voltage down: L)
47 VBATL 43 DI 42 DEI 41 DO
Latch VREF
1.6V PWM0
(DisC)
y
25 DRV0 26 PGND0 27 ASIST 6 SS0 52 VO0 53 EO0 51 IN0 21 PVCC1 28 Out1 30 7 13 23 22 20 19 8 45 18 34 33 31 29 PGND1 SS1 PNSW2 PVCC2 HO2 MO2 LO2 SS2 PNSW3 STOP PVCC3 HO3 MO3 LO3 VCC VBATL VO2 VCC VO1 9 SS3 VBATL SS 5 PVCC1 16 DRV4
PGND1
ar
VREF VO0 VREF Error amp.0 Dead time PVCC1 cont.
PGND1
VCC
Voltage step-up for IC drive VCC
5 V/0.05 A
in
PWM1 PWM2 PWM3 Dead time cont. PVCC1
PGND1
(POR) Latch
1.6 V
EO1 VO1
55 VREF 54
S.C.P. comp.
R S
Q Q
VBATL VO1 IN1
Voltage step-up
Ch.1 5 V/1 A
VREF Error amp.1
IN1 35 CTL1 H-start
1.6 V
(POR) Latch S.C.P. comp.
R S Q Q
lim
VREF
R S Q Q R S Q Q
EO2 VO2 CTL2 H-start
62 VREF 61
Voltage step-up/down SW (at step-down)
Ch.2 3.3 V/0.5 A
IN2 36
Error amp.2
IN2
(POR) Latch
1.6 V
EO3 VO3
Pr e
50 VREF 49 Error amp.3 (POR) Latch
1.6 V
S.C.P. comp.
VO3 Voltage step-down IN3
Ch.3 1.5 V/0.3 A 1.8 V/0.3 A
CTL3 H-start EO4 VO4
IN3 37
VREF
Transformer drive IN4
Ch.4-1 CCD main (15 V/30 mA) Ch.4-2 CCD sub (-8 V/10 mA)
64 VREF 63
S.C.P. comp.
VREF PWM4
CTL4 H-start EO5 VO5 CTL5 H-start EO6 VO6
IN4 38
Error amp.4
(POR) Latch
1.6 V
10 SS4
2 VREF 1
S.C.P. comp.
R S
Q Q
VBATL IN5
Transformer drive
Ch.5-1 LCD (12.4 V/30 mA) Ch.5-2 LCD (3.7 V/60 mA)
VREF PWM5 Error amp.5 (POR) Latch
PVCC1 15 DRV5
PGND1
IN5 39
1.6 V
11 SS5 VBATL 14 DRV6 IN6
4 VREF 3
S.C.P. comp.
R S
Q Q
PVCC1 VREF PWM6
Voltage step-up
Ch.6 Back light 7 V/100 mA
PGND1
IN6 40 CTL6 H-start
Error amp.6 59 SGND
12 SS6
SDH00015EEB
41
AN30210A
Application Circuit Example (continued)
* Application circuit example 5 (2 pcs of unit-3 battery -2 : 1.5 V to 3.6 V) * Ch.2, ch.3 output FET (High-side): Using P-ch. FET
SCP VREF 58 60 COSC 32
(H:Frequency down)
H-start RT 57 56
1.40 V 0.55 V
SCP0
CT 17
CTL0 46 44 SVCC 48 VBAT
Voltage descent Overvoltage
(POR) S Q S.C.P.0 DisC R
VREF 1.26 V (allowance: 1%) VREF
VCC U.V.L.O.
(Voltage down: L)
OSC
(VBATL input: H)
(High temperature: H) Temp. det. TOSH 24 (H :Total shut-down) (POR) VREF
R S Q Q
(Overvoltage: L)
VBAT U.V.L.O. 1.5 V/ 2.5 V (Voltage down: L)
47 VBATL 43 DI 42 DEI 41 DO
Latch VREF
1.6V PWM0
(DisC)
y
25 DRV0 26 PGND0 27 ASIST 6 SS0 52 VO0 53 EO0 51 IN0 21 PVCC1 28 Out1 30 7 13 23 22 20 19 8 45 18 34 33 31 29 PGND1 SS1 PNSW2 PVCC2 HO2 MO2 LO2 SS2 PNSW3 STOP PVCC3 HO3 MO3 LO3 VO1 VO1 9 SS3 VBATL SS 5 PVCC1 16 DRV4
PGND1
ar
VREF VO0 VREF Error amp.0 Dead time PVCC1 cont.
PGND1
VCC
Voltage step-up for IC drive VCC
5 V/0.05 A
in
PWM1 PWM2 PWM3 Dead time cont. PVCC1
PGND1
(POR) Latch
1.6 V
VBATL VO1 IN1 Voltage step-up
Ch.1 5 V/1 A
EO1 VO1
55 VREF 54
S.C.P. comp.
R S
Q Q
VREF Error amp.1
IN1 35 CTL1 H-start
1.6 V
(POR) Latch S.C.P. comp.
R S Q Q
lim
VREF
R S Q Q R S Q Q
VBATL VO2
EO2 VO2
62 VREF 61
Voltage step-up/down SW (at step-down)
Ch.2 3.3 V/0.5 A
IN2 36 CTL2 H-start
1.6 V
Error amp.2
IN2
(POR) Latch EO3 VO3 50 VREF 49 S.C.P. comp.
Pr e
Error amp.3 (POR) Latch
1.6 V
VO3 IN3
Voltage step-down
Ch.3 1.5 V/0.3 A 1.8 V/0.3 A
CTL3 H-start EO4 VO4
IN3 37
VREF
Transformer drive IN4
Ch.4-1 CCD main (15 V/30 mA) Ch.4-2 CCD sub (-8 V/10 mA)
64 VREF 63
S.C.P. comp.
VREF PWM4
CTL4 H-start EO5 VO5 CTL5 H-start EO6 VO6
IN4 38
Error amp.4
(POR) Latch
1.6 V
10 SS4
2 VREF 1
S.C.P. comp.
R S
Q Q
VBATL IN5
Transformer drive
Ch.5-1 LCD (12.4 V/30 mA) Ch.5-2 LCD (3.7 V/60 mA)
VREF PWM5 Error amp.5 (POR) Latch
PVCC1 15 DRV5
PGND1
IN5 39
1.6 V
11 SS5 VBATL 14 DRV6 IN6
4 VREF 3
S.C.P. comp.
R S
Q Q
PVCC1 VREF PWM6
Voltage step-up
Ch.6 Back light 7 V/100 mA
PGND1
IN6 40 CTL6 H-start
Error amp.6 59 SGND
12 SS6
42
SDH00015EEB
AN30210A
Recommended Operating Conditions
Parameter Timing resister Timing capacitor Oscillator frequency Constant setting capacitance at ch.0 short-circuit and VBATL over-voltage protection operating Constant setting capacitance at ch.1 to ch.6 short-circuit and thermal protection operating Constant setting capacitance at soft start Symbol RT CT fOUT CSCP0 CSCP CSS Recommended value 33 180 550 0.15 0.1 20 Unit k pF kHz F F nF
New Package Dimensions (Unit: mm)
9.000.20 7.000.20 48 49 33
lim
1 0.40 (1.00) 0 to 10 0.500.20
64
17
Pr e
(0.50)
0.150.05
Seatingplane
0.100.10
1.400.10 1.70 max
16 0.160.05
7.000.20 9.000.20
in
(0.50)
SDH00015EEB
ar
32
y
43
* LQFP064-P-0707B (Lead-free package)
Request for your special attention and precautions in using the technical information and semiconductors described in this material
(1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this material is limited to showing representative characteristics and applied circuits examples of the products. It neither warrants non-infringement of intellectual property right or any other rights owned by our company or a third party, nor grants any license. (3) We are not liable for the infringement of rights owned by a third party arising out of the use of the product or technologies as described in this material. (4) The products described in this material are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: * Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. * Any applications other than the standard applications intended. (5) The products and product specifications described in this material are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (6) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage, and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (7) When using products for which damp-proof packing is required, observe the conditions (including shelf life and amount of time let standing of unsealed items) agreed upon when specification sheets are individually exchanged. (8) This material may be not reprinted or reproduced whether wholly or partially, without the prior written permission of Matsushita Electric Industrial Co., Ltd.
2002 JUL

▲Up To Search▲

Price & Availability of AN30210A

	To Download AN30210A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .