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HCF4536B
PROGRAMMABLE TIMER
s
s
s
s
s
s s
s s
24 FLIP-FLOP STAGES - COUNTS FROM 20 TO 224 LAST 16 STAGES SELECTABLE BY BCD SELECT CODE GROUP SELECT INDICATES ONE OR MORE PRIORITY INPUTS QUIESCENT CURRENT SPECIFIED UP TO 20V STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES"
DIP
ORDER CODES
PACKAGE DIP TUBE HCF4536BEY T&R
DESCRIPTION HCF4536B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP package. HCF4536B is a programmable timer consisting of 24 ripple-binary counter stages. The salient feature of this device is its flexibility. The device can count from 1 to 224 or the first 8 stages can be bypassed to allow an output, selectable by a 4-bit code, from any one of the remaining 16 stages. It PIN CONNECTION
can be driven by an external clock or an RC oscillator that can be constructed using on-chip components. Input IN1 serves as either the external clock input or the input to the on-chip RC oscillator. OUT1 and OUT2 are connection terminals for the external RC components. In addition, an on-chip monostable circuit is provided to allow a variable pulse width output. Various timing functions can be achieved using combinations of these capabilities. A logic "1" on the 8-BYPASS input enables a bypass of the first 8 stages and makes stage 9 the first counter stage of the last 16 stages. Selection of 1 of 16 outputs is accomplished by the decoder and the BCD inputs A, B, C, and D. MONO IN is the timing input
October 2002
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HCF4536B
for the on-chip monostable oscillator. Grounding of the MONO IN terminal through a resistor of 10 K or higher, disables the one shot circuit and connects the decoder directly to the DECODE OUT terminal. A resistor to VDD and a capacitor to ground from the MONO IN terminal enables the INPUT EQUIVALENT CIRCUIT one-shot circuit and controls its pulse width. A fast test mode is enabled by a logic "1" on 8-BYPASS, SET, and RESET. This mode divides the 24-stage counter into three 8-stage sections to facilitate a fast test sequence.
PIN DESCRIPTION
PIN No 9, 10, 11, 12 1 2 15 6 3 4, 5 13 7 14 8 16 SYMBOL A, B, C, D SET RESET NAME AND FUNCTION
Binary Select Input Set input Reset Input Monostable OscillatorTimMONO IN ing Input 8Bypass input( bypass 8BYPASS the first 8 stages) External Clock Input or IN1 RC oscillator Input OUT1, OUT2 Outputs DECODE Decode Out Terminal OUT CLOCK Clock Inhibit Input INHIBIT OSC. Oscillator Inhibit Input INHIBIT VSS Negative Supply Voltage VDD Positive Supply Voltage
FUNCTIONAL DIAGRAM
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HCF4536B
TRUTH TABLE
In1 Set L L X X X L H
X : Don't Care
Reset L L L H L L L
Clock Inh L L L L H L L
Osc. Inh L L L L L X
Out1
Out2
Decode Out No Change Advance to Next State
H L L L L
L L L
H H H
H L No Change No Change Advance to Next State
DECODE OUT SELECTION TABLE
NUMBER OF STAGES IN DIVIDER CHAIN D L L L L L L L L H H H H H H H H C L L L L H H H H L L L L H H H H B L L H H L L H H L L H H L L H H A 8-BYPASS = 0 L H L H L H L H L H L H L H L H 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 8-BYPASS = 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
BLOCK DIAGRAM
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LOGIC DIAGRAM
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HCF4536B
LOGIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol VDD VI II PD Top Tstg Supply Voltage DC Input Voltage DC Input Current Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature Storage Temperature Parameter Value -0.5 to +22 -0.5 to VDD + 0.5 10 200 100 -55 to +125 -65 to +150 Unit V V mA mW mW C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage.
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HCF4536B
RECOMMENDED OPERATING CONDITIONS
Symbol VDD VI Top Supply Voltage Input Voltage Operating Temperature Parameter Value 3 to 20 0 to VDD -55 to 125 Unit V V C
DC SPECIFICATIONS
Test Condition Symbol Parameter VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 VO (V) |IO| VDD (A) (V) 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 18 TA = 25C Min. Typ. 0.04 0.04 0.04 0.08 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 -3.2 -1 -2.6 -6.8 1 2.6 6.8 10-5 5 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 3.5 7 11 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 Max. 5 10 20 100 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 Value -40 to 85C Min. Max. 150 300 600 3000 4.95 9.95 14.95 0.05 0.05 0.05 -55 to 125C Min. Max. 150 300 600 3000 Unit
IL
Quiescent Current
A
VOH
High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Output Drive Current
VOL
VIH
VIL
IOH
IOL
Output Sink Current Input Leakage Current Input Capacitance
0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18
<1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1
V
V
V
V
mA
mA
II
Any Input Any Input
0.1
7.5
1
1
A
pF
CI
The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
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DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25C, CL = 50pF, RL = 200K, tr = tf = 20 ns)
Test Condition Symbol Parameter VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Min. Value (*) Typ. 1 0.5 0.35 2.5 0.8 0.6 4 1.5 1 150 75 50 300 125 80 3 1 0.75 100 50 40 200 75 50 200 100 60 3 1 0.75 2.5 1 0.6 3.5 1.5 1 Unlimited 0.5 1.5 2.5 1 3 5 Max. 2 1 0.7 5 0.6 1.2 8 3 2 300 150 100 600 250 160 6 2 1.5 200 100 80 400 150 100 400 200 120 6 2 1.5 5 2 1.6 7 3 2 s Unit
tPLH tPHL Propagation Delay Time (Clock to Q1, 8-Bypass High) Propagation Delay Time (Clock to Q1, 8-Bypass Low) Propagation Delay Time (Clock to Q16) Propagation Delay Time (Qn to Qn+1) tPLH Propagation Delay Time
s
s
ns
ns
tPHL
Reset to Qn
s
tTHL tTLH Transition Time
ns
tW
Pulse Width Clock
ns
Set
ns
Reset
s
Recovery Time Set
s
Reset
s
tr, tf
Clock Input Rise or Fall Time Maximum Clock Input Frequency
s
fCL
MHz
(*) Typical temperature coefficient for all VDD value is 0.3 %/C.
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HCF4536B
TYPICAL APPLICATIONS Time Internal Configuration Using External Clock; Set and Clock Inhibit Functions Time Internal Configuration Using On-Chip RC oscillator and Reset Input to Initiate Time Interval
Time Internal Configuration Using Ext. Ck; Reset and Output Monostable to Achieve a Pulse Out
Use of HCF4098B and HCF4536B to get Decode Pulse 8 Clock Pulses after Reset Pulses
TIMING DIAGRAM
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FUNCTIONAL TEST SEQUENCE Inputs In 1 H H L H L L L Set L H H H H L Reset H H H H H L 8-Bypass H H H H H L Outputs Decade Out Q1 Thru Q24 L L L COMMENTS All 24 steps are in reset mode Counter is in three 8-stage section in parallel mode First "H" to "L" Transition of Clock 255 "H" to "L" transitions are clocked in the counter H H The 255 "H" to "L" Transition Counter converted back to 24 stages in series mode. Set and Reset must be connected together and simultaneously go from "H" to "L" In1 switches to a "H" Counter Ripples from an all "H" state to an all "L" state
H L
L L
L L
L L
H L
FUNCTIONAL TEST SEQUENCE Test function has been included for the reduction of test time required to exercise all 24 counter stages.This test function divides the counter into three 8-stage section and 255 counts are loaded in each of the 8-stage sections in parallel. All TEST CIRCUIT flip-flops are now at a "H". The counter is now returned to the normal 24-steps in series configuration. One more pulse is entered into In1 which will cause the counter to ripple from an all "H" state to an all "L" state.
CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200K RT = ZOUT of pulse generator (typically 50)
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HCF4536B
WAVEFORM : PROPAGATION DELAY TIMES, PULSE WIDTH CLOCK
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HCF4536B
Plastic DIP-16 (0.25) MECHANICAL DATA
mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 TYP. MAX. inch
P001C
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HCF4536B
SO-16 MECHANICAL DATA
DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010
PO13H
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HCF4536B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com
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