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19-2578; Rev 0; 10/02
Single/Dual LVDS Line Receivers with "In-Path" Fail-Safe
General Description
The MAX9171/MAX9172 single/dual low-voltage differential signaling (LVDS) receivers are designed for high-speed applications requiring minimum power consumption, space, and noise. Both devices support switching rates exceeding 500Mbps while operating from a single 3.3V supply. The MAX9171 is a single LVDS receiver and the MAX9172 is a dual LVDS receiver. Both devices conform to the ANSI TIA/EIA-644 LVDS standard and convert LVDS to LVTTL/LVCMOS-compatible outputs. A fail-safe feature sets the outputs high when the inputs are undriven and open, terminated, or shorted. The MAX9171/MAX9172 are available in 8-pin SO packages and space-saving thin QFN and SOT23 packages. For lower skew devices, refer to the MAX9111/ MAX9113 data sheet. o Input Accepts LVDS and LVPECL o In-Path Fail-Safe Circuit o Space-Saving 8-Pin QFN and SOT23 Packages o Fail-Safe Circuitry Sets Output High for Open, Undriven Shorted, or Undriven Terminated Output o Flow-Through Pinout Simplifies PC Board Layout o Guaranteed 500Mbps Data Rate o Second Source to DS90LV018A and DS90LV028A (SO Packages Only) o Conforms to ANSI TIA/EIA-644 Standard o 3.3V Supply Voltage o -40C to +85C Operating Temperature Range o Low Power Dissipation
Features
MAX9171/MAX9172
Applications
Multipoint Backplane Interconnect Laser Printers Digital Copiers Cellular Phone Base Stations LCD Displays Network Switches/Routers Clock Distribution
Ordering Information
PART MAX9171EKA-T MAX9171ESA MAX9171ETA* MAX9172EKA-T MAX9172ESA MAX9172ETA* TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C PINPACKAGE 8 SOT23-8 8 SO 8 Thin QFN 8 SOT23-8 8 SO 8 Thin QFN TOP MARK AALX -- -- AALY -- --
*Future product--contact factory for availability.
Pin Configurations
MAX9171
VCC GND OUT N.C.
MAX9171
MAX9172
MAX9172
IN- 1 IN+ 2 N.C. 3 N.C. 4
8 VCC 7 OUT 6 N.C. 5 GND
1 2 3 4
8 IN7 IN+ 6 N.C. 5 N.C.
IN1- 1 IN1+ 2 IN2+ 3 IN2- 4
8 VCC 7 OUT1 6 OUT2 5 GND
VCC 1 GND 2 OUT1 3 OUT2 4
8 IN17 IN1+ 6 IN2+ 5 IN2-
SO/QFN*
SOT23
SO/QFN*
SOT23
________________________________________________________________ Maxim Integrated Products
1
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Single/Dual LVDS Line Receivers with "In-Path" Fail-Safe MAX9171/MAX9172
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +4.0V IN_+, IN_- to GND .................................................-0.3V to +4.0V OUT_ to GND ............................................-0.3V to (VCC + 0.3V) Continuous Power Dissipation (TA = +70C) 8-Pin SOT23 (derate 8.9mW/C above +70C) ...........714mW 8-Pin SO (derate 5.9mW/C above +70C) .................471mW 8-Pin QFN (derate 24.4mW/C above +70C) ..........1951mW Operating Temperature Range ..........................-40C to +85C Junction Temperature .....................................................+150C Storage Temperature Range ............................-65C to +150C ESD Protection Human Body Model (IN_+, IN_-) ...................................13kV Lead Temperature (soldering, 10s) ................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, differential input voltage |VID| = 0.1V to 1.2V, receiver input voltage = 0 to VCC, common-mode voltage VCM = |VID/2| to (VCC - |VID/2|), TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = 3.3V, |VID| = 0.2V, VCM = 1.2V, TA = +25C.) (Notes 1, 2)
PARAMETER LVDS INPUTS (IN_+, IN_-) Differential Input High Threshold Differential Input Low Threshold Input Current (Noninverting Input) Power-Off Input Current (Noninverting Input) Input Current (Inverting Input) Power-Off Input Current (Inverting Input) LVCMOS/LVTTL OUTPUTS (OUT_) Output High Voltage Output Low Voltage Output Short-Circuit Current POWER SUPPLY Supply Current ICC Inputs open MAX9171 MAX9172 3.6 7.0 6 9 mA VOH VOL IOS Open, undriven short, or IOH = -4.0mA undriven parallel termination VID = 0V IOL = 4.0mA, VID = -100mV VOUT_ = 0 (Note 3) -45 2.7 2.7 3.2 3.2 0.1 -77 0.4 -120 V mA V VTH VTL IIN+ IIN+OFF IINIIN-OFF Figure 1 Figure 1 Figure 1 VIN+ = 0 to 3.6V, VIN- = 0 to 3.6V, VCC = 0 or open (Figure 1) Figure 1 VIN+ = 0 to 3.6V, VIN- = 0 to 3.6V, VCC = 0 or open (Figure 1) -100 +0.5 -0.5 -0.5 -0.5 -40 -40 -2.1 0 +4.4 0 -5.0 +0.5 +10.0 +0.5 0 mV mV A A A A SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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Single/Dual LVDS Line Receivers with "In-Path" Fail-Safe
SWITCHING CHARACTERISTICS
(VCC = 3.0V to 3.6V, CL = 15pF, |VID| = 0.2V, VCM = 1.2V, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = 3.3V, TA = +25C.) (Notes 4, 5, 6)
PARAMETER Differential Propagation Delay High to Low Differential Propagation Delay Low to High Differential Pulse Skew |tPHLD - tPLHD| Differential Channel-to-Channel Skew (MAX9172) Differential Part-to-Part Skew Rise Time Fall Time Maximum Operating Frequency SYMBOL tPHLD tPLHD tSKD1 tSKD2 tSKD3 tSKD4 tTLH tTHL fMAX Figures 2, 3 Figures 2, 3 Figures 2, 3 (Note 7) Figures 2, 3 (Note 8) Figures 2, 3 (Note 9) Figures 2, 3 (Note 10) Figures 2, 3 Figures 2, 3 All channels switching, VOL(MAX) = 0.4V, VOH(MIN) = 2.7V, 40% < duty cycle < 60% 250 0.55 0.51 300 CONDITIONS MIN 1.0 1.0 TYP 1.65 1.62 30 40 MAX 2.5 2.5 400 500 1 1.5 0.8 0.8 UNITS ns ns ps ps ns ns ps MHz
MAX9171/MAX9172
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to GND except VTH, VTL, and VID. Note 2: All devices are 100% production tested at TA = +25C and are guaranteed by design for TA = -40C to +85C, as specified. Note 3: Short only one output at a time. Do not exceed the absolute maximum junction temperature specification. Note 4: AC parameters are guaranteed by design and not production tested. Note 5: CL includes scope probe and test jig capacitance. Note 6: Pulse generator output conditions: tR = tF < 1ns (0% to 100%), frequency = 250MHz, 50% duty cycle, VOH = 1.3V, VOL = 1.1V. Note 7: tSKD1 is the magnitude of the difference of differential propagation delays in a channel. tSKD1 = |tPHLD - tPLHD|. Note 8: tSKD2 is the magnitude of the difference of the tPLHD or tPHLD of one channel and the tPLHD or tPHLD of the other channel on the same part. Note 9: tSKD3 is the magnitude of the difference of any differential propagation delays between parts at the same VCC and within 5C of each other. Note 10: tSKD4 is the magnitude of the difference of any differential propagation delays between parts operating over the rated supply and temperature ranges.
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Single/Dual LVDS Line Receivers with "In-Path" Fail-Safe MAX9171/MAX9172
Typical Operating Characteristics
(VCC = 3.3V, VCM = 1.2V, |VID| = 0.2V, fIN = 200MHz, CL = 15pF, TA = +25C, unless otherwise specified.)
OUTPUT HIGH VOLTAGE vs. SUPPLY VOLTAGE
MAX9171 toc01
OUTPUT LOW VOLTAGE vs. SUPPLY VOLTAGE
MAX9171 toc02
OUTPUT SHORT-CIRCUIT CURRENT vs. SUPPLY VOLTAGE
OUTPUT SHORT-CIRCUIT CURRENT (mA) VID = +200mV, OUTPUT SHORTED TO GROUND -70
MAX9171 toc03
3.6 IOH = -4mA 3.5 OUTPUT HIGH VOLTAGE (V) 3.4 3.3 3.2 3.1 3.0 2.9 3.0 3.1 3.2 3.3 3.4 3.5
100 IOL = +4mA OUTPUT LOW VOLTAGE (mV) 95
-65
90
-75
85
-80
80 3.6 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)
-85 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V)
DIFFERENTIAL THRESHOLD VOLTAGE vs. SUPPLY VOLTAGE
MAX9171 toc04
MAX9172 SUPPLY CURRENT vs. FREQUENCY
MAX9171 toc05
MAX9172 SUPPLY CURRENT vs. TEMPERATURE
f = 1MHz BOTH CHANNELS SWITCHING SUPPLY CURRENT (mA)
MAX9171 toc06
-35 DIFFERENTIAL THRESHOLD VOLTAGE (mV)
40
9
SUPPLY CURRENT (mA)
-40 HIGH-LOW -45
30
8
20
BOTH CHANNELS SWITCHING
7
-50
LOW-HIGH
10 ONE CHANNEL SWITCHING
-55 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V)
0 0.1 1
6 10 FREQUENCY (MHz) 100 1000 -40 -15 10 35 60 85 TEMPERATURE (C)
DIFFERENTIAL PROPAGATION DELAY vs. SUPPLY VOLTAGE
MAX9171 toc07
DIFFERENTIAL PROPAGATION DELAY vs. TEMPERATURE
DIFFERENTIAL PROPAGATION DELAY (ns)
MAX9171 toc08
2.5 DIFFERENTIAL PROPAGATION DELAY (ns)
2.0
1.9
2.0 tPHLD tPLHD 1.5
1.8 tPHLD 1.7 tPLHD 1.6
1.0 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V)
1.5 -40 -15 10 35 60 85 TEMPERATURE (C)
4
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Single/Dual LVDS Line Receivers with "In-Path" Fail-Safe
Typical Operating Characteristics (continued)
(VCC = 3.3V, VCM = 1.2V, |VID| = 0.2V, fIN = 200MHz, CL = 15pF, TA = +25C, unless otherwise specified.)
DIFFERENTIAL PULSE SKEW vs. SUPPLY VOLTAGE
MAX9171 toc09
MAX9171/MAX9172
DIFFERENTIAL PULSE SKEW vs. TEMPERATURE
MAX9171 toc10
DIFFERENTIAL PROPAGATION DELAY vs. DIFFERENTIAL INPUT VOLTAGE
DIFFERENTIAL PROPAGATION DELAY (ns) fIN = 20MHz 2.5
MAX9171 toc11
120 DIFFERENTIAL PULSE SKEW (ps)
200 DIFFERENTIAL PULSE SKEW (ps)
3.0
90
160
120
60
2.0
80
tPHLD tPLHD
30
40
1.5
0 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V)
0 -40 -15 10 35 60 85 TEMPERATURE (C)
1.0 100 600 1100 1600 2100 2600 DIFFERENTIAL INPUT VOLTAGE (mV)
DIFFERENTIAL PROPAGATION DELAY vs. COMMON-MODE VOLTAGE
MAX9171 toc12
TRANSITION TIME vs. TEMPERATURE
MAX9171 toc13
DIFFERENTIAL PROPAGATION DELAY vs. LOAD
DIFFERENTIAL PROPAGATION DELAY (ns) fIN = 20MHz
MAX9171 toc14
2.5 DIFFERENTIAL PROPAGATION DELAY (ns) fIN = 20MHz 2.2
700
2.4
2.2 tPHLD 2.0 tPLHD 1.8
TRANSITION TIME (ps)
600 tTLH 500 tTHL 400
1.9 tPHLD 1.6 tPLHD
1.3
1.6
1.0 0.1 0.6 1.1 1.6 2.1 2.6 3.1 COMMON-MODE VOLTAGE (V)
300 -40 -15 10 35 60 85 TEMPERATURE (C)
1.4 10 20 30 LOAD (pF) 40 50
TRANSITION TIME vs. LOAD
MAX9171 toc15
DIFFERENTIAL PULSE SKEW vs. INPUT TRANSITION TIME
MAX9171 toc16
2100
300 DIFFERENTIAL PULSE SKEW (ps) 250 200 150 100 50 0
1700 TRANSITION TIME (ps)
1300 tTLH 900 tTHL 500
100 10 20 30 LOAD (pF) 40 50
1.0
1.5
2.0
2.5
3.0
INPUT TRANSITION TIME (ns)
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Single/Dual LVDS Line Receivers with "In-Path" Fail-Safe MAX9171/MAX9172
MAX9171 Pin Description
PIN SOT23 1 2 3 4, 5, 6 7 8 -- SO/QFN 8 5 7 3, 4, 6 2 1 (QFN only) NAME VCC GND OUT N.C. IN+ INEP FUNCTION Positive Power-Supply Input. Bypass with a 0.1F and a 0.001F capacitor to GND with the smallest capacitor closest to the pin. Ground Receiver Output No Connection. Not internally connected. Noninverting Differential Receiver Input Inverting Differential Receiver Input Exposed Paddle. Solder to PC board ground.
MAX9172 Pin Description
PIN SOT23 1 2 3 4 5 6 7 8 -- SO/QFN 8 5 7 6 4 3 2 1 (QFN only) NAME VCC GND OUT1 OUT2 IN2IN2+ IN1+ IN1EP FUNCTION Positive Power-Supply Input. Bypass with a 0.1F and a 0.001F capacitor to GND with the smallest capacitor closest to the pin. Ground Receiver Output 1 Receiver Output 2 Inverting Differential Receiver Input 2 Noninverting Differential Receiver Input 2 Noninverting Differential Receiver Input 1 Inverting Differential Receiver Input 1 Exposed Paddle. Solder to PC board ground.
Detailed Description
LVDS Inputs
The MAX9171/MAX9172 feature LVDS inputs for interfacing high-speed digital circuitry. The LVDS interface standard is a signaling method intended for point-topoint communication over controlled-impedance media, as defined by the ANSI TIA/EIA-644 standards. The technology uses low-voltage signals to achieve fast transition times and minimize power dissipation and noise immunity. The MAX9171/MAX9172 convert LVDS
signals to LVCMOS/LVTTL signals at rates in excess of 500Mbps. These devices are capable of detecting differential signals as low as 100mV and as high as 1.2V within a 0 to VCC input voltage range. Table 1 is the input-output function table.
Fail-Safe
The MAX9171/MAX9172 fail-safe drives the receiver output high when the differential input is: * Open * Undriven and shorted * Undriven and terminated Without fail-safe, differential noise at the input may switch the receiver and appear as data to the receiving system. An open input occurs when a cable and termination are disconnected. An undriven, terminated input occurs when a cable is disconnected with the termination still connected across the receiver inputs or when the driver of a receiver is in high impedance. An undriven, shorted input can occur due to a shorted cable.
Table 1. Input-Output Function Table
INPUTS (IN_+) - (IN_-) 0mV -100mV Open Undriven short Undriven parallel termination OUTPUT OUT_ High Low High High High
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Single/Dual LVDS Line Receivers with "In-Path" Fail-Safe
In-Path vs. Parallel Fail-Safe
VCC 2.5A IN_+
MAX9171/MAX9172
OUT_ 40mV IN_-
5A
Figure 1. Input with In-Path Fail-Safe Network Equivalent Circuit
IN_+ PULSE GENERATOR IN_-
OUT_ 15pF
50
50
Figure 2. Propagation Delay and Transition Test Time Circuit
The MAX9171/MAX9172 have in-path fail-safe that is compatible with in-path fail-safe receivers, such as the DS90LV018A and DS90LV028A. Refer to the MAX9111/ MAX9113 data sheet for pin-compatible receivers with parallel fail-safe and lower jitter. Refer to the MAX9130 data sheet for a single LVDS receiver with parallel failsafe in an SC70 package. The MAX9171/MAX9172 with in-path fail-safe are designed with a +40mV input offset voltage, a 2.5A current source between V CC and the noninverting input, and a 5A current sink between the inverting input and ground (Figure 1). If the differential input is open, the 2.5A current source pulls the input to VCC 0.7V and the 5A source sink pulls the inverting input to ground, which drives the receiver output high. If the differential input is shorted or terminated with a typical value termination resistor, the +40mV offset drives the receiver output high. If the input is terminated and floating, the receiver output is driven high by the +40mV offset, and the 2:1 current sink to current source ratio (5A:2.5A) pulls the inputs to ground. This can be an advantage when switching between drivers on a multipoint bus because the change in common-mode voltage from ground to the typical driver offset voltage of 1.2V is not as much as the change from VCC to 1.2V (parallel fail-safe pulls the bus to VCC). Figure 2 shows the propagation delay and transition test time circuit and Figure 3 shows the propagation delay and transition test time waveforms.
1.3V
IN_1.2V (0V DIFFERENTIAL) IN_+ tPLHD tPHLD VID = 0.2V
1.1V
VOH 80% 1.5V 80% 1.5V 20% VOL
20% OUT_
tTLH
tTHL
Figure 3. Propagation Delay and Transition Time Waveforms _______________________________________________________________________________________ 7
Single/Dual LVDS Line Receivers with "In-Path" Fail-Safe MAX9171/MAX9172
ESD Protection
ESD protection structures are incorporated on all pins to protect against electrostatic discharges encountered during handling and assembly. The receiver inputs of the MAX9171/MAX9172 have extra protection against static electricity. These pins are protected to 13kV without damage. The structures withstand ESD during normal operation and when powered down. The receiver inputs of these devices are characterized for protection to the limit of 13kV using the Human Body Model.
Termination
The MAX9171/MAX9172 require an external termination resistor. The termination resistor should match the differential impedance of the transmission line. Termination resistance values may range between 90 to 132, depending on the characteristic impedance of the transmission medium. When using the MAX9171/MAX9172, minimize the distance between the input termination resistors and the MAX9171/MAX9172 receiver inputs. Use a single 1% surface-mount resistor.
Human Body Model
Figure 4a shows the Human Body Model, and Figure 4b shows the current waveform it generates when discharged into a low-impedance load. This model consists of a 100pF capacitor charged to the ESD test voltage, which is then discharged into the test device through a 1.5k resistor.
Board Layout
For LVDS applications, a four-layer PC board that provides separate power, ground, LVDS signals, and output signals is recommended. Separate the input LVDS signals from the output signals to prevent crosstalk. Solder the exposed pad on the QFN package to a pad connected to the PC board ground plane by a matrix of vias. Connecting the exposed pad is not a substitute for connecting the ground pin. Always connect pin 5 on the QFN package to ground.
RC 1M CHARGE-CURRENT LIMIT RESISTOR HIGHVOLTAGE DC SOURCE Cs 100pF RD 1500 DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST
Applications Information
Supply Bypassing
Bypass VCC with high-frequency surface-mount ceramic 0.1F and 0.001F capacitors in parallel, as close to the device as possible, with the 0.001F capacitor closest to the device. For additional supply bypassing, place a 10F tantalum or ceramic capacitor at the point where power enters the circuit board.
Differential Traces
Input trace characteristics affect the performance of the MAX9171/MAX9172. Use controlled-impedance PC board traces to match the cable characteristic impedance. Eliminate reflections and ensure that noise couples as common mode by running the differential traces close together. Reduce skew by matching the electrical length of traces. Each channel's differential signals should be routed close to each other to cancel their external magnetic field. Maintain a constant distance between the differential traces to avoid discontinuities in differential impedance. Avoid 90 turns and minimize the number of vias to further prevent impedance discontinuities.
Figure 4a. Human Body ESD Test Modules
IP 100% 90% AMPERES 36.8% 10% 0 0 tRL TIME
Ir
PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE)
tDL CURRENT WAVEFORM
Cables and Connectors
Transmission media typically have a controlled differential impedance of about 100. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Balanced cables tend to pick up noise as common mode, which is rejected by the LVDS receiver.
Figure 4b. Human Body Current Waveform
Chip Information
TRANSISTOR COUNT: 624 PROCESS: CMOS
8
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Single/Dual LVDS Line Receivers with "In-Path" Fail-Safe
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
SOT23, 8L.EPS
MAX9171/MAX9172
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9
Single/Dual LVDS Line Receivers with "In-Path" Fail-Safe MAX9171/MAX9172
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
9LUCSP, 3x3.EPS
10
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Single/Dual LVDS Line Receivers with "In-Path" Fail-Safe
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX9171/MAX9172
PACKAGE OUTLINE, 6, 8 & 10L, QFN THIN (DUAL), EXPOSED PAD, 3x3x0.80 mm
21-0137
C
COMMON DIMENSIONS SYMBOL A D E A1 L k A2 MIN. 0.70 2.90 2.90 0.00 0.20 MAX. 0.80 3.10 3.10 0.05 0.40
0.25 MIN 0.20 REF.
PACKAGE VARIATIONS PKG. CODE T633-1 T833-1 T1033-1 N 6 8 10 D2 1.50-0.10 1.50-0.10 1.50-0.10 E2 2.30-0.10 2.30-0.10 2.30-0.10 e 0.95 BSC 0.65 BSC 0.50 BSC JEDEC SPEC MO229 / WEEA MO229 / WEEC MO229 / WEED-3 b 0.40-0.05 0.30-0.05 0.25-0.05 [(N/2)-1] x e 1.90 REF 1.95 REF 2.00 REF
PACKAGE OUTLINE, 6, 8 & 10L, QFN THIN (DUAL), EXPOSED PAD, 3x3x0.80 mm
21-0137
C
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
6, 8, &10L, QFN THIN.EPS

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