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October 2003 rev 1.0
ASM1232LP/LPS
5V P Power Supply Monitor and Reset Circuit
* * Low-cost surface mount packages: 8-pin/16-pin SO, 8-pin DIP and 8-pin Micro SO packages Wide operating temperature -40C to +85C (N/EMA suffixed devices)
General Description
The ASM1232LP/LPS is a fully integrated microprocessor supervisor. It can halt and restart a "hung-up" microprocessor, restart a microprocessor after a power failure. It has a watchdog timer and external reset override. A precision temperature-compensated reference and
Applications
* * * * * * Microproessor Systems Computers Controllers Portable Equipment Intelligent Instuments Automotive Systems
comparator circuits monitor the 5V, VCC input voltage status. During power-up or when the VCC power supply falls outside selectable tolerance limits, both RESET and RESET become active. When VCC rises above the threshold voltage, the reset signals remain active for an additional 250ms minimum, allowing the power supply and system microprocessor to stabilize. The trip point tolerance signal, TOL, selects the trip level tolerance to be either 5% or 10%. Each device has both a push-pull, active HIGH reset output and an open drain active LOW reset output. A debounced manual reset input, PBRST, activates the reset outputs for a minimum period of 250ms. There is a watchdog timer to stop and restart a microprocessor that is "hung-up". The watchdog timeouts periods are selectable: 150ms, 610ms and 1.200ms. If the ST input is not strobed LOW before the time-out period expires, a reset is generated. Devices are available in 8-pin DIP, 16-pin SO and compact 8pin MicroSO packages.
Typical Operating Circuit
+5V
ASM1232LP/LPS
ST RESET GND TD TOL
10k I/O
P
RESET
Block Diagram ASM1232LP/LPS
VCC Tolerance Selection + TOL Reference RESET RESET
Key Features
* * * * * * * * 5V supply monitor Selectable watchdog period Debounce manual push-button reset input Precision temperature-compensated voltage reference and comparator. Power-up, power-down and brown out detection 250ms minimum reset time Active LOW open drain reset output and active HIGH push-pull output Selectable trip point tolerance: 5% or 10%
ST PBRST TD
VCC 40k
Push Button Debounce Voltage Sense Comparators Watchdog Transition Detector Reset & Watchdog Timer
GND
Alliance Semiconductor 2575 Augustine Drive . Santa Clara, CA 95054 . Tel: 408.855.4900 . Fax: 408.855.4999 . www.alsc.com
Notice: The information in this document is subject to change without notice
October 2003 rev 1.0
ASM1232LP/LPS
Pin Configuration
DIP/SO/MicroSO
PBRST TD TOL GND 8 ASM1232LP 2 ASM1232LPS-2 7 ASM1232LPCMA 3 6 ASM1232LPEMA 1 4 5 VCC ST RESET RESET NC 1
SO
16 NC 15 VCC 14 NC ST NC RESET NC RESET
PBRST 2 NC TD NC TOL NC GND 3 4 5 6 7 8
ASM1232LPSN 13
12 11 10 9
Pin Description
Pin # 8-Pin Package 1 2 Pin # 16-Pin Package 2 4 Pin Name PBRST TD Function Debounced manual pushbutton RESET input. Watchdog time delay selection. (tTD = 150ms for TD = GND, tTD = 610ms for TD=Open, and tTD = 1200ms for TD = VCC). Selects 5% (TOL connected to GND) or 10% (TOL connected to VCC) trip point tolerance. Ground. Active HIGH reset output. RESET is active: 1. If VCC falls below the reset voltage trip point. 5 9 RESET 2. If PBRST is LOW. 3. If ST is not strobed LOW before the timeout period set by TD expires. 4. During power-up. Active LOW reset output. (See RESET). Strobe input. 5V power. No internal connection.
3 4
6 8
TOL GND
6 7 8 -
11 13 15 1,3,5,7, 10,12,14,16
RESET ST VCC NC
5V P Power Supply Monitor and Reset Circuit
Notice: The information in this document is subject to change without notice
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ASM1232LP/LPS
Detailed Description
The ASM1232LP/LPS monitors the microprocessor or microcontroller power supply and generates reset signal, both active HIGH and Active LOW, that halt processor operation whenever the power supply voltage levels are outside a predetermined tolerance.
VCC VCCTP(MIN)
tR VCCTP(MAX) VCCTP tRPU RESET VOH
~ ~
RESET and RESET outputs RESET is an active HIGH signal developed by a CMOS push-pull output stage and is the logical opposite to RESET.
VOL RESET
~~ ~~
RESET is an active LOW signal. It is developed with an open drain driver. A pull up resistor of typical value 10k to 50k is required to connect with the output.
Figure 1: Timing Diagram : Power Up
Trip Point Tolerance Selection The TOL input is used to determine the level VCC can vary below 5V without asserting a reset. With TOL conected to VCC, RESET and RESET become active whenever VCC falls below 4.5V. RESET and RESET become active when the VCC falls below 4.75V if TOL is connected to ground. After VCC has risen above the trip point set by TOL, RESET and RESET remain active for a minimum time period of 250ms. On power-down, one VCC falls below the reset threshold RESET stays LOW and is guaranteed to be 0.4V or less until VCC drops below 1.2V. The active HIGH reset signal is valid down to a VCC level of 1.2V also.
RESET VOH RESET tRPD VCC
VCCTP (MAX) VCCTP VCCTP (MIN)
tF
Figure 2: Timing Diagram : Power Down
Tolerance Select TOL = VCC TOL = GND
Tolerance
TRIP Point Voltage (V) Min Nom 4.37 4.62 Max 4.49 4.74
Application Information
Manual Reset Operation Push-button switch input, PBRST, allows the user to override the internal trip point detection circuits and issue reset signals. The pushbutton input is debounced and is pulled HIGH through an internal 40k resistor.
10% 5%
4.25 4.5
~ ~~
VOL
~~
5V P Power Supply Monitor and Reset Circuit
Notice: The information in this document is subject to change without notice
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October 2003 rev 1.0
When PBRST is held LOW for the minimum time tPB, both resets become active and remain active for a minimum time period of 250ms after PBRST returns HIGH. The debounced input is guaranteed to recognize pulses greater than 20ms. No external pull-up resistor is required, since PBRST is pulled HIGH by an internal 40k resistor.
ST
ASM1232LP/LPS
power-up after the supply voltage returns to an in-tolerance condition, the reset signal remains active for 250ms minimum, be detected.
Valid Strobe Valid Strobe Invalid Strobe
allowing
the
power
supply
and
system
microprocessor to stabilize. ST pulses as short as 20ns can
The PBRST can be driven from a TTL or CMOS logic line or shorted to ground with a mechanical switch.
tPB tPDLY VIL VIH
RESET
tST tRST tTD (min) tTD (max)
~
PBRST
Note: ST is ignored whenever a reset is active
Figure 5: Timing Diagram: Strobe Input
Timeouts periods of approximately 150ms, 610ms or 1,200ms are selected through the TD pin.
VOH VOL
~ ~
tRST
RESET RESET
Figure 3: Timing Diagram: Pushbutton Reset
ASM1232LP/LPS
1 2 3 4
PBRST TD TOL GND VCC 8 ST RESET RESET
Figure 4: Application Circuit: Pushbutton Reset
Watchdog Timer and ST Input A watchdog timer stops and restarts a microprocessor that is "hung-up". The P must toggle the ST input within a set period (as selectable through TD input) to verify proper software execution. If the ST is not toggled low within the minimum timeout period, reset signals become active. In
~~ ~~
5V 7 6 5
I/O
TD Voltage level
Watchdog Time-out Period (ms) Min Nom 150 610 1200 Max 250 1000 2000
GND Floating VCC
62.5 250 500
The watchdog timer can not be disabled. It must be strobed
P RESET 5V
with a high-to-low transition to avoid watchdog timeout and reset.
ASM1232 LP/LPS
1 2 3 4
PBRST TD TOL GND VCC 8 ST RESET
MREQ 10k
7 6 5
P RESET Address
Bus
Decoder
Figure 6: Application Circuit: Watchdog Timer
5V P Power Supply Monitor and Reset Circuit
Notice: The information in this document is subject to change without notice
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ASM1232LP/LPS
Absolute Maximum Ratings
Parameter Voltage on VCC Voltage on ST, TD Voltage on PBRST, RESET, RESET Operating Temperature Range (N/EMA suffixed devices) Operating Temperature Range (others) Soldering Temperature (for 10 sec) Storage Temperature
Min -0.5 -0.5 -0.5 -40 0
Max 7 VCC + 0.5 VCC + 0.5 +85 70 +260
Unit V V V C C C C
-55
+125
Note: 1. Voltages are measured with respect to ground 2. These are stress ratings only and functional implication is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
DC Electrical Characteristics
Unless otherwise stated, 4.5V <= VCC<= 5.5V and over the operating temperature range of 0C to 70C (-40C to +85C. for N/EMA devices). All voltages are referenced to ground.
Parameter Supply Voltage ST and PBRST Input High Level ST and PBRST Input Low Level VCC Trip Point (TOL = GND) VCC Trip Point (TOL = VCC) Watchdog Timeout Period Watchdog Timeout Period Watchdog Timeout Period Output Voltage Output Current Output Current
Symbol VCC VIH VIL VCCTP VCCTP tTD tTD tTD VOH IOH IOL
Conditions
Min 4.5 2 -0.3 4.50 4.25
Typ
Max 5.5 VCC + 0.3 0.8
Unit V V V V V ms ms ms A mA mA 5 of 9
4.62 4.37 150 1200 610 VCC - 0.1 -10
4.74 4.49 250 2000 1000
TD = GND TD = VCC TD Floating I=-500A, Note 3 Output = 2.4V, Note 2 Output = 0.4V
62.5 500 250 VCC - 0.5 -8 10
5V P Power Supply Monitor and Reset Circuit
Notice: The information in this document is subject to change without notice
October 2003 rev 1.0
Parameter Input Leakage RESET Low Level Internal Pull-up Resistor Operating Current (CMOS) Input Capacitance Output Capacitance PBRST Manual Reset Minimum Low Time Reset Active Time ST Pulse Width VCC Fail Detect to RESET or RESET VCC Slew Rate PBRST Stable LOW to RESET and RESET Active VCC Detect to RESET or RESET inactive VCC Slew Rate ICC1 CIN COUT tPB tRST tST tRPD tF tPDLY tRPU tR tRISE = 5s 4.25V to 4.75V 250 0 4.75V to 4.25V 300 Note 4 PBRST = VIL 20 250 20 Symbol IIL VOL Note 1 Note 3 Note 1 Conditions Min -1.0
ASM1232LP/LPS
Typ
Max 1.0 0.4
Unit A V k
40 30 5 10
A pF pF ms
610
1000
ns ns
5
8
s s
20 610 1000
ms ms ns
Notes 1. PBRST is internally pulled HIGH to VCC through a nominal 40k resistor. 2. RESET is an open drain output. 3. RESET remains within 0.5V of VCC on power-down until VCC falls below 2V. RESET remains within 0.5V of ground on power-down until VCC falls below 2.0V. 4. Must not exceed the minimum watchdog time-out period (tTD). The watchdogcircuit cannot be disabled. To avoid a reset, ST must be strobed.
5V P Power Supply Monitor and Reset Circuit
Notice: The information in this document is subject to change without notice
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ASM1232LP/LPS
Package Information
MicroSO (8-Pin)
D a
Inches Min
A A1 A2 b C
L
Millimeteres Max Min
0.050 0.75 0.25 0.13 2.90 0.65 BSC 4.90 BSC 2.90 0.40 0 1.35 0.10 0.33 0.19 1.27 0.157 0.244 0.050 0.197 0.210 0.195 0.022 0.070 0.045 0.400 0.325 0.280 0.430 0.060 0.150 2.92 3.81 3.80 5.80 0.40 4.80 0.38 2.92 0.36 1.14 0.80 9.02 0.13 7.62 6.10 2.54 7.62 10.92 4.00 6.20 1.27 2.00 5.33 4.95 0.56 1.78 1.14 10.16 8.26 7.11 3.10 0.70 6 1.75 0.25 0.51 0.25
Max
0.10 0.15 0.95 0.40 0.23 3.10
MicroSO (8-Pin)
E1 E
0.0020 0.0295 0.0098 0.0051 0.1142
0.0433 0.0059 0.0374 0.0157 0.0091 0.1220
A2 A e A1
0.10mm 0.004in
D e E E1 L a
C
0.0256 BSC 0.193 BSC 0.1142 0.0157 0 0.053 0.004 0.013 0.007 0.050 0.150 0.228 0.016 0.189 0.015 0.115 0.014 0.045 0.030 0.355 0.005 0.300 0.240 0.100 0.300 0.115 0.1220 0.0276 6
b
SO (8-Pin)
C
SO (8-Pin)
A
L
0.069 0.010 0.020 0.010
E
H
A1 B C e E H L D A
D
A1
A
Plastic DIP (8-Pin)
Plastic DIP (8-Pin)
D1 E E1
A1 A2 b b2 b3 D D1 E E1
A2 A L A1 eA eB
0 - 15
D
e eA
C
eB eC L
b2 b
5V P Power Supply Monitor and Reset Circuit
Notice: The information in this document is subject to change without notice
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October 2003 rev 1.0
ASM1232LP/LPS
SO (16-Pin)
SO (16-Pin)* Inches Min
E H C L
A A1 B C D E e H 0.926 0.0040 0.013 0.0091 0.3977 0.2914 0.394 0.016 0
Millimeters Max Min
2.35 0.10 0.33 0.23 10.10 7.40 10.00 0.40 0
Max
2.65 0.30 0.51 0.32 10.50 7.60 1.27 BSC 10.65 1.27 8
0.1043 0.0118 0.020 0.0125 0.4133 0.2662 0.419 0.050 8
D A e
B
0.050 BSC
L
A1
* JEDEC Drawing MS-013AA
Ordering Information
Part Number ASM1232LP ASM1232LPS ASM1232LPS-2 ASM1232LPCMA ASM1232LPEMA ASM1232LPN ASM1232LPSN-2 ASM1232LPSN
Package 8-DIP 16-SO 8-SO 8-MicroSO 8-MicroSO 8-DIP 8-SO 16-SO
Operating Temperature Range 0C To 70C 0C To 70C 0C To 70C 0C To 70C -40C To 85C -40C To 85C -40C To 85C -40C To 85C
Maximum Supply Current (A) 30 30 30 30 30 30 30 30
Voltage Monitoring Application 5V 5V 5V 5V 5V 5V 5V 5V
5V P Power Supply Monitor and Reset Circuit
Notice: The information in this document is subject to change without notice
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ASM1232LP/LPS
Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel: 408 - 855 - 4900 Fax: 408 - 855 - 4999 www.alsc.com
Copyright (c) Alliance Semiconductor All Rights Reserved Preliminary Information Part Number: ASM1232LP/LPS Document Version: 1.0
(c) Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.

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