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Integrated Circuit Systems, Inc.
ICS9248-150
Frequency Generator for Multi-Processor Servers
Recommended Application: ServerWorks Grand Champion Systems Output Features: * 8 - Differential CPU Clock Pairs @ 3.3V * 1 - 3V 33MHz PCI clocks * 1 - 48MHz clock * 1 - Inverted 48MHz clock * 1 - 14.318MHz reference output Features: * Up to 200MHz frequency support * Support power management: Power Down Mode * Supports Spread Spectrum modulation: 0 to -0.5% down spread. * Uses external 14.318MHz crystal * Select logic for Differential Swing Control, Test mode, Tristate, Power down, Spread Spectrum. * External resistor for current reference * FS pins for frequency select Key Specifications: * PCI Output jitter <500ps * CPU Output jitter <150ps * 48MHz Output jitter <350ps * REF Output jitter < 1000ps
PCICLK VDD48 FS0/48MHz FS1/48MHz# GND48 VDDCPU CPUCLKT0 CPUCLKC0 GNDCPU CPUCLKT1 CPUCLKC1 VDDCPU CPUCLKT2 CPUCLKC2 GNDCPU CPUCLKT3 CPUCLKC3 VDDCPU REF SPREAD# GNDREF X1 X2 VDDREF
Pin Configuration
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 SEL100/133 GNDPCI VDDA GNDA PD# VDDCPU CPUCLKT4 CPUCLKC4 GNDCPU CPUCLKT5 CPUCLKC5 VDDCPU CPUCLKT6 CPUCLKC6 GNDCPU CPUCLKT7 CPUCLKC7 VDDCPU MULTSEL0 MULTSEL1 GND GNDI REF I REF VDDI REF
48-Pin SSOP and TSSOP
Functionality
SEL133/100 0 0 0 0 1 1 1 1 FS0 0 0 1 1 0 0 1 1 FS1 0 1 0 1 0 1 0 1 Function Active 100MHz 100MHz Test Mode 100MHz Test Mode Tristate all outputs Active 133MHz 133MHz Test Mode Active 200MHz Reser ved
Block Diagram
PLL2
ICS9248-150
48MHz 48MHz#
X1 X2
XTAL OSC PLL1 Spread Spectrum
REF
CPU DIVDER
8 8
CPUCLKT (7:0) CPUCLKC (7:0) PCICLK
Analog Power Groups
VDD48, GND48 = 48MHz, PLL2 VDDA=VDD (core supply voltage 3.3V) GNDA=Ground for core supply
PCI DIVDER
Digital Power Group
VDDREF, GNDREF = REF, Xtal
PD# SPREAD# MULTSEL(1:0) SEL100/133 FS(1:0)
Control Logic Config. Reg. I REF
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ICS9248-150
General Description
ICS9248-150 is a main clock for ServerWorks Grand Champion Systems. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. ICS9248-150 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
Pin Configuration
PIN NUMBER 1 2, 6, 12, 18, 24, 31, 37, 43, 3 4 5, 9, 15, 21, 28, 34, 40, 47 33, 36, 39, 42, 16, 13, 10, 7 32, 35, 38, 41, 17, 14, 11, 8 19 20 22 23 25, 46 26 29, 30 44 27, 45 48
PIN NAME
PCICLK VDD FS0 48MHz FS1 48MHz# GND CPUCLKT (7:0) CPUCLKC (7:0) REF SPREAD# X1 X2 VDDI REF VDDA, I REF MULTSEL(1:0) PD# GNDI REF GNDA SEL100/133
TYPE
OUT PWR IN OUT IN OU T PWR OUT OUT OUT IN X2 Cr ystal Input PCI clock output 3.3V power supply Frequency select pin 48MHz clock output Frequency select pin
DESCRIPTION
Inver ted 48MHz clock output Ground pins for 3.3V supply "True" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. "Complementar y" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. Reference output 14.318MHz Invokes Spread Spectrum functionality on the Differential host clocks, Active Low 14.318MHz Cr ystal input
X1 Cr ystal Output 14.318MHz Cr ystal output PWR OUT IN IN PWR IN Analog power supply 3.3V This pin establishes the reference current for the CPUCLK pairs. This pin takes a fixed precision resistor tied to ground in order to establish the required current. CPU swing select inputs Invokes power-down mode. Active Low. Analog Ground pins for 3.3V supply CPU Frequency Select. Low=100MHz, High=133MHz
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ICS9248-150
Truth Table
SEL 133/100 0 0 0 0 1 1 1 1 FS0 0 0 1 1 0 0 1 1 FS1 0 1 0 1 0 1 0 1 CPUCLK MHz 10 0 100 100 Tristate 133 133 200 TCLK/2 PCICLK MHZ 33 33 Disable Tristate 33 33 33 TCLK/8 48 MHz 48 Disable Disable Tristate 48 Disable 48 TCLK/2
CPUCLK Buffer Configuration
Conditions Iout Vdd = nominal (3.30V) Configuration All combinations of M0, M1 and Rr shown in table below All combinations of M0, M1 and Rr shown in table below Load Nominal test load for given configuration Nominal test load for given configuration Min Max
-7% I nominal +7% I nominal -12% I nominal +12% I nominal
Iout
Vdd = 3.30 5%
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ICS9248-150
CPUCLK Swing Select Functions
MULTSEL0 0 0 0 0 1 1 1 1 MULTSEL1 0 0 1 1 0 0 1 1 Board Target Trace/Term Z 60 ohms 50 ohms 60 ohms 50 ohms 60 ohms 50 ohms 60 ohms 50 ohms Reference R, Iref= Vdd/(3*Rr) Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Output Current Ioh = 5*Iref Ioh = 5*Iref Ioh = 6*Iref Ioh = 6*Iref Ioh = 4*Iref Ioh = 4*Iref Ioh = 7*Iref Ioh = 7*Iref Voh @ Z, Iref=2.32mA 0.71V @ 60 0.59V @ 50 0.85V /2 60 0.71V @ 50 0.56V @ 60 0.47V @ 50 0.99V @ 60 0.82V @ 50
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
30 (DC equiv) 25 (DC equiv) 30 (DC equiv) 25 (DC equiv) 30 (DC equiv) 25 (DC equiv) 30 (DC equiv) 25 (DC equiv)
Ioh = 5*Iref Ioh = 5*Iref Ioh = 6*Iref Ioh = 6*Iref Ioh = 4*Iref Ioh = 4*Iref Ioh = 7*Iref Ioh = 7*Iref
0.75V @ 30 0.62V @ 20 0.90V @ 30 0.75V @ 20 0.60 @ 20 0.5V @ 20 1.05V @ 30 0.84V @ 20
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ICS9248-150
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . 5.5 V GND -0.5 V to VDD +0.5 V 0C to +70C 115C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Operating Supply Current Powerdown Current Input Frequency Pin Inductance Input Capacitance1
1, 2
SYMBOL CONDITIONS VIH VIL I IH VIN = V DD I IL1 VIN = 0 V; Inputs with no pull-up resistors I IL2 VIN = 0 V; Inputs with pull-up resistors I DD3.3OP I DD3.3PD Fi Lpin CIN COUT CINX TSTAB TREC t PZH,t PZL t PHZ,t PLZ CL = 0 pF; Select @ 100 MHz CL = 0 pF; Input address to VDD or GND VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins CPU Freq. = 100/133 MHz CPU Freq. = 200 MHz CPU Freq. = 100/133 MHz CPU Freq. = 200 MHz Output enable delay (all outputs) Output disable delay (all outputs)
MIN 2 VSS - 0.3 -5 -5 -200
TYP
MAX VDD + 0.3 0.8 5
UNITS V V mA mA
181 52 14.318
250 60 7 5 6 45 8 10.5 8 10.5 10 10
mA mA MHz nH pF pF pF ms ms ms ms ns ns
27
Clk Stabilization
Clk Recovery1, 3 Delay 1
1 2
1 1
Guaranteed by design, not 100% tested in production. From VDD = 3.3V to 1% of target frequency 3 From deassertion of PD# to 1% of target frequency
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ICS9248-150
Electrical Characteristics - CPU
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Diff. Crossover Volta Duty Cycle Skew CPUT0:7 Skew CPU C0:7 Jitter
1 2
SYMBOL RDSP2B
1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 2.375 V VOL @MIN = 1.2 V, VOL @MAX = 0.3 V VOL = 20%, VOH = 80% VOH = 80%, VOL = 20% VDD = 3.3V VT = 50% VT = 50% VT = 50% VT = 50%
MIN
TYP 714 714
MAX UNITS V V mA mA ps ps % % ps ps ps
RDSN2B VOH2B VOL2B IOH2B IOL2B2 tr2B1 tf2B1 Vx dt2B1 t sk2B
1
2 -27 27 175 175 45 45 324 501 50 51.2 83.8 78.5 86 0.4 -27 30 700 700 55 55 100 100 150
2
t sk2B1 tjcyc-cyc
1
Guaranteed by design, not 100% tested in production. IOWT can be varied and is selectable thru the MULTSEL pin.
Electrical Characteristics - REF
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL FO1 RDSP11 VOH1 VOL1 IOH1 I OL1 tr11 tf11 dt11 t sk11 tjcyc-cyc
1
CONDITIONS VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 20 2.4 -29 29 1 1 45
TYP MAX UNITS 14.318 MHz 48 60 0.4 -23 27 1.6 2.4 53.5 305 4 4 55 N/A 1000 V V mA mA ns ns % ps ps
Guaranteed by design, not 100% tested in production.
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ICS9248-150
Electrical Characteristics - PCI
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL FO1 RDSP11 VOH1 VOL1 IOH1 I OL1 tr11 tf11 dt11 t sk11 t jcyc-cyc
1
CONDITIONS VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 12 2.4 -33 30 0.5 0.5 45
TYP 33.3 33
MAX UNITS MHz 55 V 0.55 -33 38 V mA mA ns ns % ps ps
1.2 1.2 49.9 139.7
2 2 55 N/A 500
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 48MHz
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL FO1 RDSP11 VOH1 VOL1 I OH1 I OL1 t r11 t f11 dt11 tsk11 t jcyc-cyc
1
CONDITIONS VO = V DD*(0.5) I OH = -1 mA I OL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 20 2.4 -29 29 1 1 45
TYP 48 48
MAX UNITS MHz 60 0.4 -23 27 V V mA mA ns ns % ps ps
1.3 1.6 52.5 175
4 4 55 N/A 350
Guaranteed by design, not 100% tested in production.
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ICS9248-150
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power down latency should be as short as possible but conforming to the sequence requirements shown below.
PD#
CPUCLKT CPUCLKC VCO Crystal
Notes: 1. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 3. The shaded sections on the VCO and the Crystal signals indicate an active clock.
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ICS9248-150
N
c
SYMBOL
L
INDEX AREA
E1
E
12 D h x 45
A A1
A A1 b c D E E1 e h L N
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 15.75 16.00
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 48
10-0034
D (inch) MIN .620 MAX .630
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP Package
Ordering Information
ICS9248yF-150-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type Prefix ICS, AV = Standard Device
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ICS9248-150
N
c
L
INDEX AREA
E1
E
12 D
a
A2 A1
A
In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 8.10 BASIC 0.319 BASIC E E1 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N 0 8 0 8 aaa -0.10 -.004 VARIATIONS N 48
10-0039
-Ce
b SEATING PLANE
D mm. MIN 12.40 MAX 12.60 MIN .488
D (inch) MAX .496
aaa C
Reference Doc.: JEDEC Publication 95, MO-153
6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil) (240 mil)
Ordering Information
ICS9248yG-150-T
Example:
ICS XXXX y G - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type Prefix ICS, AV = Standard Device
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ICS9248-150
Revision History
Rev. E Issue Date Description 6/9/2005 Removed PCI Skew from Electrical Characteristics Table. Page # 7
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