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IDT74FCT16601AT/CT FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
FEATURES:
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IDT74FCT16601AT/CT
DESCRIPTION:
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0.5 MICRON CMOS Technology High-speed, low-power CMOS replacement for ABT functions Typical tSK(o) (Output Skew) < 250ps Low input and output leakage 1A (max.) ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) VCC = 5V 10% High drive outputs (-32mA IOH, 64mA IOL) Power off disable outputs permit "live insertion" Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V, TA = 25C Available in SSOP and TSSOP packages
The FCT16601T 18-bit registered transceivers are built using advanced dual metal CMOS technology. These high-speed, low-power 18-bit registered bus transceivers combine D-type latches and D-type flip-flops to allow data flow in either direction in a transparent, latched or clocked mode. Each direction has an independent latch enable, an independent clock with a clock enable, and an independent output enable. The package is organized with a flow-through signal pin organization to ease board layout. All inputs are designed with hysteresis for improved noise margin. This transceiver is ideally suited for high speed memory interfaces which utilize high speed synchronous writes, by clocking the data into a high speed register. Reads can then be performed in a transparent or latched mode utilizing the same transceiver. The FCT16601T are ideally suited for driving high-capacitance loads and low-impedance backplanes. The output buffers are designed with power off disable capability to allow "live insertion" of boards when used as backplane drivers.
FUNCTIONAL BLOCK DIAGRAM
OEAB CLKE NAB CLKAB LEA B LEB A CLKBA
1 56 55 2
28
30
CLKE NBA OEBA
29
27
3
A1
CE 1D C1 CLK CE 1D C1 CLK
54
B1
TO 17 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
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(c) 2001 Integrated Device Technology, Inc.
MAY 2001
DSC-5446/-
IDT74FCT16601AT/CT FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
OEAB LEAB A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LEBA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 CLKENAB CLKAB B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 CLKBA CLKENBA
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM(2) TSTG IOUT Description Terminal Voltage with Respect to GND Storage Temperature DC Output Current Max -0.5 to +7 -0.5 to VCC+0.5 -65 to +150 -60 to +120 Unit V V C mA VTERM(3) Terminal Voltage with Respect to GND
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All device terminals except FCT162XXX Output and I/O terminals. 3. Output and I/O terminals for FCT162XXX.
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 3.5 3.5 Max. 6 8 Unit pF pF
NOTE: 1. This parameter is measured at characterization but not tested.
FUNCTION TABLE(1, 4)
CLKENAB X X X H L L L L OEAB H L L L L L L L Inputs LEAB X H H L L L L L CLKAB X X X X # # L H A X L H X L H X X Outputs B Z L H B(2) L H B(2) B(3)
SSOP/ TSSOP TOP VIEW
PIN DESCRIPTION
Pin Names OEAB OEBA LEAB LEBA CLKAB CLKBA Ax Bx CLKENAB CLKENBA Description A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B Latch Enable Input B-to-A Latch Enable Input A-to-B Clock Input B-to-A Clock Input A-to-B Data Inputs or B-to-A 3-State Outputs B-to-A Data Inputs or A-to-B 3-State Outputs A to B Clock Enable Input B to A Clock Enable Input
NOTES: 1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA. 2. Output level before the indicated steady-state input conditions were established. 3. Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. 4. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-Impedance = LOW-to-HIGH Transition
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IDT74FCT16601AT/CT FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, VCC = 5.0V 10%
Symbol VIH VIL IIH IIL IOZH IOZL VIK IOS VH ICCL ICCH ICCZ Parameter Input HIGH Level Input LOW Level Input HIGH Current (Input pins) Input HIGH Current (I/O pins) Input LOW Current (Input pins) Input LOW Current (I/O pins) High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Short Circuit Current Input Hysteresis Quiescent Power Supply Current VCC = Max. VIN = GND or VCC VCC = Min., IIN = -18mA VCC = Max., VO = GND(3) -- VCC = Max. VO = 2.7V VO = 0.5V VI = GND Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VI = VCC Min. 2 -- -- -- -- -- -- -- -- -80 -- -- Typ.(2) -- -- -- -- -- -- -- -- -0.7 -140 100 5 Max. -- 0.8 1 1 1 1 1 1 -1.2 -250 -- 500 V mA mV A A Unit V V A
OUTPUT DRIVE CHARACTERISTICS
Symbol IO VOH Parameter Output Drive Current Output HIGH Voltage VCC = Max., VO = VCC = Min. VIN = VIH or VIL VCC = Min. VIN = VIH or VIL VCC = 0V, VIN or VO 4.5V Test Conditions(1) 2.5V(3) IOH = -3mA IOH = -15mA IOH = -32mA(4) IOL = 64mA Min. -50 2.5 2.4 2 -- -- Typ.(2) -- 3.5 3.5 3 0.2 -- Max. -180 -- -- -- 0.55 1 Unit mA V
VOH IOFF
Output LOW Voltage Input/Output Power Off Leakage
V A
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. Duration of the condition can not exceed one second.
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IDT74FCT16601AT/CT FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Test Conditions(1) VCC = Max. VIN = 3.4V(3) VCC = Max., Outputs Open OEAB = VCC, OEBA = GND One Input Toggling 50% Duty Cycle VCC = Max., Outputs Open fCP = 10MHz (CLKBA) 50% Duty Cycle OEAB = VCC OEBA = GND LEAB = GND CLKENBA = GND One Bit Toggling fi = 5MHz 50% Duty Cycle VCC = Max., Outputs Open fCP = 10MHz (CLKBA) 50% Duty Cycle OEAB = VCC OEBA = GND LEBA = GND CLKENBA = GND Eighteen Bits Toggling fi = 2.5MHz 50% Duty Cycle Min. -- -- Typ.(2) 0.5 75 Max. 1.5 120 Unit mA A/ MHz
VIN = VCC VIN = GND
IC
Total Power Supply Current(6)
VIN = VCC VIN = GND
--
0.8
1.7
mA
VIN = 3.4V VIN = GND
--
1.3
3.2
VIN = VCC VIN = GND
--
3.8
6.5(5)
VIN = 3.4V VIN = GND
--
8.5
20.8(5)
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi
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IDT74FCT16601AT/CT FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16601AT Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tSU tH tSU tH tW tW tSK(o) Parameter CLKAB or CLKBA frequency(3) Propagation Delay Ax to Bx or Bx to Ax Propagation Delay LEBA to Ax, LEAB to Bx Propagation Delay CLKBA to Ax, CLKAB to Bx Output Enable Time OEBA to Ax, OEAB to Bx Output Disable Time OEBA to Ax, OEAB to Bx Set-up Time, HIGH or LOW Ax to CLKAB, Bx to CLKBA Hold Time, HIGH or LOW Ax after CLKAB, Bx after CLKBA Set-up Time, HIGH or LOW Ax to LEAB, Bx to LEBA Hold Time HIGH or LOW Ax after LEAB, Bx after LEBA Set-up Time, CLKEN to CLK Hold Time, CLKEN after CLK LEAB or LEBA Pulse Width HIGH(3) CLKAB or CLKBA Pulse Width HIGH or LOW(3) Output Skew(4) Condition(1) CL = 50pF RL = 500 Min.(2) -- 1.5 1.5 1.5 1.5 1.5 4 0 Clock LOW ClockHIGH 1 2.5 2 2.5 0 2.5 3 -- Max. 150 4.9 5.2 4.7 5.8 6.2 -- -- -- -- -- -- -- -- -- 0.5 FCT16601CT Min.(2) -- 1.5 1.5 1.5 1.5 1.5 2.4 0 1 1.5 0.5 2 0 2.5 3 -- Max. 150 4 4.2 4.2 4.8 5.2 -- -- -- -- -- -- -- -- -- 0.5 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This parameter is guaranteed but not tested. 4. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
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IDT74FCT16601AT/CT FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V CC 7.0V 500 V IN Pulse Generator D.U.T. 50pF RT 500 CL V OUT
SWITCH POSITION
Test Open Drain Disable Low Enable Low All Other Tests Switch Closed Open
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Circuits for All Outputs
DATA INPUT tSU TIM ING INPUT ASYNCHRONOUS CONTROL PRES ET CLEA R ETC. SYNCHRONOUS CONTROL PRES ET CLEA R CLOCK ENABLE ETC. tREM
tH
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
LOW -HIGH-LOW PULSE tW HIGH-LOW -HIGH PULSE
1.5V
1.5V
tSU
tH
Pulse Width
Set-up, Hold, and Release Times
ENABLE SAM E PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE P HASE INPUT TRANSITION tPHL tPHL 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V DISABLE 3V CONTROL INPUT tPZL OUTPUT NORM ALLY LOW SW ITCH CLOSED tPZH OUTPUT NORM ALLY HIGH SW ITCH OPEN 3.5V 1.5V 0.3V tPHZ 0.3V 1.5V 0V 0V VOH tPLZ 1.5V 0V 3.5V VOL
Propagation Delay
Enable and Disable Times
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns.
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IDT74FCT16601AT/CT FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT X FCT XX XXX Temperature Family Device Range Type XX Package
PV PA
Shrink Small Outline Package Thin Shrink Small Outline Package
601AT 601CT
18-Bit Universal Bus Transceiver
16
Double-Density, 5 Volt, High Drive
74
- 40C to +85C
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for Tech Support: logichelp@idt.com (408) 654-6459
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