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PD - 94393
l l l l l l
Advanced Process Technology Ultra Low On-Resistance Dynamic dv/dt Rating 175C Operating Temperature Fast Switching Fully Avalanche Rated
G
HEXFET(R) Power MOSFET
D
IRFR3411 IRFU3411
VDSS = 100V RDS(on) = 44m
Description
Advanced HEXFET(R) Power MOSFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The D-Pak is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead, I-Pak, version (IRFU series) is for throughhole mounting applications. Power dissipation levels up to 1.5 watts are possible in typical surface mount applications.
S
ID = 32A
D-Pak IRFR3411
I-Pak IRFU3411
Absolute Maximum Ratings
Parameter
ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS IAR EAR dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds
Max.
32 23 110 130 0.83 20 16 13 7.0 -55 to + 175 300 (1.6mm from case )
Units
A W W/C V A mJ V/ns C
Thermal Resistance
Parameter
RJC RJA RJA Junction-to-Case Junction-to-Ambient (PCB mount)* Junction-to-Ambient
Typ.
--- --- ---
Max.
1.2 50 110
Units
C/W
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1
02/18/02
IRFR3411/IRFU3411
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
V(BR)DSS
V(BR)DSS/TJ
RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss EAS
Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Single Pulse Avalanche Energy
Min. Typ. Max. Units Conditions 100 --- --- V VGS = 0V, ID = 250A --- 0.12 --- V/C Reference to 25C, I D = 1mA --- 36 44 m VGS = 10V, ID = 16A 2.0 --- 4.0 V VDS = VGS , ID = 250A 21 --- --- S VDS = 50V, ID = 16A --- --- 25 VDS = 100V, VGS = 0V A --- --- 250 VDS = 80V, VGS = 0V, TJ = 150C --- --- 100 VGS = 20V nA --- --- -100 VGS = -20V --- 48 71 ID = 16A --- 9.0 14 nC VDS = 80V --- 14 21 VGS = 10V, See Fig. 6 and 13 --- 11 --- VDD = 50V --- 35 --- ID = 16A ns --- 39 --- RG = 5.1 --- 35 --- VGS = 10V, See Fig. 10 Between lead, 4.5 --- --- 6mm (0.25in.) nH G from package --- 7.5 --- and center of die contact --- 1960 --- VGS = 0V --- 250 --- VDS = 25V --- 40 --- pF = 1.0MHz, See Fig. 5 --- 700 185 mJ IAS = 16A, L = 1.5mH
D
S
Source-Drain Ratings and Characteristics
IS
ISM
VSD trr Qrr ton Notes:
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time
Min. Typ. Max. Units
Conditions D MOSFET symbol 33 --- --- showing the A G integral reverse --- --- 110 S p-n junction diode. --- --- 1.2 V TJ = 25C, IS = 16A, VGS = 0V --- 115 170 ns TJ = 25C, IF = 16A --- 505 760 nC di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11) Starting TJ = 25C, L =1.5mH RG = 25, IAS = 16A. (See Figure 12) ISD 16A, di/dt 340A/s, VDD V(BR)DSS, TJ 175C. Pulse width 400s; duty cycle 2%.
This is a typical value at device destruction and represents
operation outside rated limits.
This is a calculated value limited to TJ = 175C .
* When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint dering techniques refer to application note #AN-994.
2
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IRFR3411/IRFU3411
1000
I D , Drain-to-Source Current (A)
100
I D , Drain-to-Source Current (A)
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
1000
100
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
4.5V
10
10
4.5V
1 0.1
20s PULSE WIDTH T = 25 C
J 1 10 100
1 0.1
20s PULSE WIDTH T = 175 C
J 1 10 100
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
3.5
ID = 33A
R DS(on) , Drain-to-Source On Resistance (Normalized)
I D , Drain-to-Source Current (A)
3.0
2.5
TJ = 25 C TJ = 175 C
2.0 1.5
100
1.0
10 4.0
V DS = 50V 20s PULSE WIDTH 7.0 8.0 5.0 6.0 9.0
0.5
0.0 -60 -40 -20
VGS = 10V
0 20 40 60 80 100 120 140 160 180
VGS , Gate-to-Source Voltage (V)
TJ , Junction Temperature ( C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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3
IRFR3411/IRFU3411
3000
2500
VGS , Gate-to-Source Voltage (V)
VGS = 0V, f = 1MHz Ciss = Cgs + Cgd , Cds SHORTED Crss = Cgd Coss = Cds + Cgd
20
ID = 16A
16
C, Capacitance (pF)
2000
Ciss
V DS = 80V V DS = 50V V DS = 20V
12
1500
8
1000
C oss
500
4
C rss
0 1 10 100 0 0 20
FOR TEST CIRCUIT SEE FIGURE 13
60 40 80
VDS , Drain-to-Source Voltage (V)
QG , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
1000
1000 OPERATION IN THIS AREA LIMITED BY R DS(on)
ISD , Reverse Drain Current (A)
100
TJ = 175 C
10
ID, Drain-to-Source Current (A)
100
10
100sec 1msec
TJ = 25 C
1
1
T A = 25C T J = 175C Single Pulse
10msec
0.1 0.2
V GS = 0 V
0.6 1.0 1.4 1.8
0.1 1 10 100 1000 VDS , Drain-toSource Voltage (V)
VSD ,Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRFR3411/IRFU3411
35
VDS
30
RD
VGS RG
D.U.T.
+
25
-VDD
ID , Drain Current (A)
20
VGS
Pulse Width 1 s Duty Factor 0.1 %
15
10
Fig 10a. Switching Time Test Circuit
VDS 90%
5
0 25 50 75 100 125 150 175
TC , Case Temperature
( C)
Fig 9. Maximum Drain Current Vs. Case Temperature
10% VGS
td(on) tr t d(off) tf
Fig 10b. Switching Time Waveforms
10
(Z thJC )
1 D = 0.50
Thermal Response
0.20 0.10 0.1 0.05 0.02 0.01
SINGLE PULSE (THERMAL RESPONSE)
0.01 0.00001
Notes: 1. Duty factor D = 2. Peak T t1/ t
2 J = P DM x Z thJC
P DM t1 t2 +T C 1
0.0001
0.001
0.01
0.1
t 1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFR3411/IRFU3411
400
1 5V
EAS , Single Pulse Avalanche Energy (mJ)
VD S
L
D R IV E R
300
ID 6.5A 11.3A BOTTOM 16A TOP
RG
20V
D .U .T
IA S tp 0 .01
+ - VD D
A
200
Fig 12a. Unclamped Inductive Test Circuit
V (B R )D SS tp
100
0 25 50 75 100 125 150 175
Starting TJ , Junction Temperature ( C)
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
IAS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator Same Type as D.U.T.
50K
QG
12V
.2F .3F
VGS
QGS VG QGD
VGS
3mA
D.U.T.
+ V - DS
IG
ID
Charge
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
6
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IRFR3411/IRFU3411
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T* Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
+
-
+
RG VGS * dv/dt controlled by RG * ISD controlled by Duty Factor "D" * D.U.T. - Device Under Test
+ VDD
*
Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive P.W. Period D=
P.W. Period
[VGS=10V ] ***
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
[VDD]
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
[ ISD ]
*** VGS = 5.0V for Logic Level and 3V Drive Devices Fig 14. For N-channel HEXFET(R) power MOSFETs
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7
IRFR3411/IRFU3411
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
6 .7 3 (.2 6 5 ) 6 .3 5 (.2 5 0 ) -A5 .4 6 (.2 1 5 ) 5 .2 1 (.2 0 5 ) 4 1 .2 7 (.0 5 0 ) 0 .8 8 (.0 3 5 )
2 .3 8 (.0 9 4 ) 2 .1 9 (.0 8 6 )
1 .1 4 (.0 4 5 ) 0 .8 9 (.0 3 5 ) 0 .5 8 (.0 2 3 ) 0 .4 6 (.0 1 8 )
6 .4 5 (.2 4 5 ) 5 .6 8 (.2 2 4 ) 6 .2 2 (.2 4 5 ) 5 .9 7 (.2 3 5 ) 1.0 2 (.0 4 0 ) 1.6 4 (.0 2 5 ) 1 2 3 0 .5 1 (.0 2 0 ) M IN . 1 0 .4 2 (.4 1 0 ) 9 .4 0 (.3 7 0 ) L E A D A S S IG N M E N T S 1 - GATE 2 - D R A IN 3 - S OU R CE 4 - D R A IN -B 1 .5 2 (.0 6 0 ) 1 .1 5 (.0 4 5 ) 3X 2X 1 .1 4 (.0 4 5 ) 0 .7 6 (.0 3 0 ) 2 .2 8 ( .0 9 0 ) 4 .5 7 ( .1 8 0 )
0 .8 9 (.0 3 5 ) 0 .6 4 (.0 2 5 ) 0 .2 5 ( .0 1 0 ) M AMB N O TE S :
0 .5 8 (.0 2 3 ) 0 .4 6 (.0 1 8 )
1 D IM E N S IO N IN G & T O L E R A N C IN G P E R A N S I Y 1 4 .5 M , 1 9 8 2 . 2 C O N T R O L L IN G D IM E N S IO N : IN C H . 3 C O N F O R M S T O J E D E C O U T L IN E T O -2 5 2 A A . 4 D IM E N S IO N S S H O W N A R E B E F O R E S O L D E R D IP , S O L D E R D IP M A X. + 0 .1 6 (.0 0 6 ) .
D-Pak (TO-252AA) Part Marking Information
EXAMPLE: T HIS IS AN IRFR120 WITH ASSEMBLY LOT CODE 1234 ASSEMBLED ON WW 16, 1999 IN T HE AS SEMBLY LINE "A" PART NUMBER INT ERNAT IONAL RECT IFIER LOGO
IRFU120 916A 12 34
ASSEMBLY LOT CODE
DAT E CODE YEAR 9 = 1999 WEEK 16 LINE A
8
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IRFR3411/IRFU3411
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
6 .7 3 (.26 5 ) 6 .3 5 (.25 0 ) -A 5 .4 6 (.2 1 5 ) 5 .2 1 (.2 0 5 ) 4 1 .2 7 ( .0 5 0 ) 0 .8 8 ( .0 3 5 )
2 .3 8 (.0 9 4 ) 2 .1 9 (.0 8 6 ) 0 .5 8 (.0 2 3 ) 0 .4 6 (.0 1 8 ) L E A D A S S IG N M E N T S 1 - GATE 2 - D R A IN 3 - SOURCE 4 - D R A IN
6 .4 5 (.2 4 5 ) 5 .6 8 (.2 2 4 ) 1 .5 2 (.0 6 0 ) 1 .1 5 (.0 4 5 ) 1 -B 2.2 8 (.0 9 0) 1.9 1 (.0 7 5) 9 .6 5 ( .3 8 0 ) 8 .8 9 ( .3 5 0 ) 2 3 6 .2 2 ( .2 4 5 ) 5 .9 7 ( .2 3 5 )
N O TE S : 1 D IM E N S IO N IN G & TO L E R A N C IN G P E R A N S I Y 1 4 .5M , 19 8 2 . 2 C O N T R O L L IN G D IM E N S IO N : IN C H . 3 C O N F O R MS TO J E D E C O U T L IN E TO -2 5 2 A A . 4 D IM E N S IO N S S H O W N A R E B E F O R E S O L D E R D IP , S O L D E R D IP M A X. + 0.1 6 (.0 0 6 ).
3X
1 .1 4 (.0 45 ) 0 .7 6 (.0 30 )
3X
0 .8 9 (.0 35 ) 0 .6 4 (.0 25 ) M AMB
1 .1 4 ( .0 4 5 ) 0 .8 9 ( .0 3 5 ) 0 .5 8 (.0 2 3 ) 0 .4 6 (.0 1 8 )
2 .28 (.0 9 0 ) 2X
0 .2 5 (.0 1 0 )
I-Pak (TO-251AA) Part Marking Information
EXAMPLE: T HIS IS AN IRFR120 WIT H ASSEMBLY LOT CODE 5678 ASSEMBLED ON WW 19, 1999 IN T HE ASSEMBLY LINE "A" PART NUMBER INT ERNAT IONAL RECT IFIER LOGO
IRFU120 919A 56 78
DAT E CODE YEAR 9 = 1999 WEEK 19 LINE A
ASSEMBLY LOT CODE
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IRFR3411/IRFU3411
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR TR R TR L
1 6.3 ( .64 1 ) 1 5.7 ( .61 9 )
16 .3 ( .6 4 1 ) 15 .7 ( .6 1 9 )
1 2.1 ( .4 7 6 ) 1 1.9 ( .4 6 9 )
F E E D D IR E C T IO N
8 .1 ( .3 18 ) 7 .9 ( .3 12 )
F E E D D IR E C T IO N
NOTES : 1. C O N T R O LL IN G D IM E N S IO N : M ILL IM ET E R . 2. A L L D IM EN S IO N S A R E S H O W N IN M ILL IM ET E R S ( IN C H E S ). 3. O U T L IN E C O N F O R M S T O E IA - 48 1 & E IA -54 1.
1 3 IN C H
16 m m NO TES : 1. O U T L IN E C O N F O R M S T O E IA -4 81 .
Data and specifications subject to change without notice. This product has been designed and qualified for the Automotive [Q101] market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.02/02
10
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