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MC74HC4051A, MC74HC4052A, MC74HC4053A Analog Multiplexers / Demultiplexers
High-Performance Silicon-Gate CMOS
The MC74HC4051A, MC74HC4052A and MC74HC4053A utilize silicon-gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog multiplexers/demultiplexers control analog voltages that may vary across the complete power supply range (from VCC to VEE). The HC4051A, HC4052A and HC4053A are identical in pinout to the metal-gate MC14051AB, MC14052AB and MC14053AB. The Channel-Select inputs determine which one of the Analog Inputs/Outputs is to be connected, by means of an analog switch, to the Common Output/Input. When the Enable pin is HIGH, all analog switches are turned off. The Channel-Select and Enable inputs are compatible with standard CMOS outputs; with pullup resistors they are compatible with LSTTL outputs. These devices have been designed so that the ON resistance (Ron) is more linear over input voltage than Ron of metal-gate CMOS analog switches. For a multiplexer/demultiplexer with injection current protection, see HC4851A and HC4852A. * Fast Switching and Propagation Speeds * Low Crosstalk Between Switches * Diode Protection on All Inputs/Outputs * Analog Power Supply Range (VCC - VEE) = 2.0 to 12.0 V * Digital (Control) Power Supply Range (VCC - GND) = 2.0 to 6.0 V * Improved Linearity and Lower ON Resistance Than Metal-Gate Counterparts * Low Noise * In Compliance With the Requirements of JEDEC Standard No. 7A * Chip Complexity: HC4051A -- 184 FETs or 46 Equivalent Gates HC4052A -- 168 FETs or 42 Equivalent Gates HC4053A -- 156 FETs or 39 Equivalent Gates
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16
16 1
PDIP-16 N SUFFIX CASE 648 1 16 SO-16 D SUFFIX CASE 751B
1
HC405xAN AWLYYWW
16
HC405xAD AWLYYWW 1 16
16 1
SO-16 WIDE DW SUFFIX CASE 751G 1
HC405xA AWLYWW
16 TSSOP-16 DT SUFFIX CASE 948F 1 16 SOEIAJ-16 F SUFFIX CASE 966
1
16 1
HC40 5xA ALYW
16
74HC405xA ALYW 1
A WL YY WW
= Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet.
(c) Semiconductor Components Industries, LLC, 1999
1
March, 2000 - Rev. 1
Publication Order Number: MC74HC4051A/D
MC74HC4051A, MC74HC4052A, MC74HC4053A
FUNCTION TABLE - MC74HC4051A LOGIC DIAGRAM MC74HC4051A Single-Pole, 8-Position Plus Common Off
X0 14 X1 15 X2 ANALOG 12 MULTIPLEXER/ INPUTS/ X3 DEMULTIPLEXER OUTPUTS X4 1 5 X5 2 X6 4 X7 11 A CHANNEL 10 B SELECT 9 INPUTS C 6 ENABLE PIN 16 = VCC PIN 7 = VEE PIN 8 = GND
13
Control Inputs Enable L L L L L L L L H C L L L L H H H H X Select B A L L H H L L H H X L H L H L H L H X ON Channels X0 X1 X2 X3 X4 X5 X6 X7 NONE X = Don't Care
3
X
COMMON OUTPUT/ INPUT
Pinout: MC74HC4051A (Top View)
VCC 16 X2 15 X1 14 X0 13 X3 12 A 11 B 10 C 9
1 X4
2 X6
3 X
4 X7
5 X5
6
7
Enable VEE
8 GND
FUNCTION TABLE - MC74HC4052A LOGIC DIAGRAM MC74HC4052A Double-Pole, 4-Position Plus Common Off
X0 14 X1 15 X2 11 X3 Y0 Y1 Y2 Y3 A B
1 5 2 4 10 9 6 12
Control Inputs Select Enable L L L L H X = Don't Care B L L H H X A L H L H X ON Channels Y0 Y1 Y2 Y3 NONE X0 X1 X2 X3
X SWITCH
13
X COMMON OUTPUTS/INPUTS
ANALOG INPUTS/OUTPUTS
Y SWITCH
3
Y
Pinout: MC74HC4052A (Top View)
PIN 16 = VCC PIN 7 = VEE PIN 8 = GND VCC 16 X2 15 X1 14 X 13 X0 12 X3 11 A 10 B 9
CHANNEL-SELECT INPUTS
ENABLE
1 Y0
2 Y2
3 Y
4 Y3
5 Y1
6
7
Enable VEE
8 GND
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MC74HC4051A, MC74HC4052A, MC74HC4053A
FUNCTION TABLE - MC74HC4053A LOGIC DIAGRAM MC74HC4053A Triple Single-Pole, Double-Position Plus Common Off
X0 13 X1 Y0 1 Y1 Z0 3 Z1 CHANNEL-SELECT INPUTS A 10 B 9 C 6 ENABLE
11 5 2 12 14
Control Inputs Enable L L L L L L L L H C L L L L H H H H X Select B A L L H H L L H H X L H L H L H L H X ON Channels Z0 Z0 Z0 Z0 Z1 Z1 Z1 Z1 Y0 Y0 Y1 Y1 Y0 Y0 Y1 Y1 NONE X0 X1 X0 X1 X0 X1 X0 X1
X SWITCH
X
ANALOG INPUTS/OUTPUTS
Y SWITCH
15
Y
COMMON OUTPUTS/INPUTS
Z SWITCH
4
Z
X = Don't Care
PIN 16 = VCC PIN 7 = VEE PIN 8 = GND
Pinout: MC74HC4053A (Top View)
VCC 16 Y 15 X 14 X1 13 X0 12 A 11 B 10 C 9
NOTE: This device allows independent control of each switch. Channel-Select Input A controls the X-Switch, Input B controls the Y-Switch and Input C controls the Z-Switch
1 Y1
2 Y0
3 Z1
4 Z
5 Z0
6
7
Enable VEE
8 GND
IIIIIIIIIIIIIIIIIIII II I IIII II I I I IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIII II I III I II II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I II II I I I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIII II I III I II II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII II II IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I
Symbol VCC VEE VIS Vin I Parameter Value Unit V V V V Positive DC Supply Voltage (Referenced to GND) (Referenced to VEE) - 0.5 to + 7.0 - 0.5 to + 14.0 - 7.0 to + 5.0 VEE - 0.5 to VCC + 0.5 25 750 500 450 Negative DC Supply Voltage (Referenced to GND) Analog Input Voltage Digital Input Voltage (Referenced to GND) DC Current, Into or Out of Any Pin Power Dissipation in Still Air, - 0.5 to VCC + 0.5 mA PD Plastic DIP EIAJ/SOIC Package TSSOP Package mW Tstg TL Storage Temperature Range - 65 to + 150 260
MAXIMUM RATINGS*
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
v
v
_C _C
Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP, SOIC or TSSOP Package
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C EIAJ/SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
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MC74HC4051A, MC74HC4052A, MC74HC4053A
RECOMMENDED OPERATING CONDITIONS
IIII I I I I IIIIIIIIIIIIIIIIIIIII I I II I II I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII I IIII I II I I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII III I II I II I I IIIIIIIIIIIIIIIIIIIIIII II I I II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I
Symbol VCC VEE VIS Vin Parameter Min 2.0 2.0 Max Unit V V V V V Positive DC Supply Voltage (Referenced to GND) (Referenced to VEE) 6.0 12.0 Negative DC Supply Voltage, Output (Referenced to GND) Analog Input Voltage - 6.0 VEE GND VCC VCC 1.2 Digital Input Voltage (Referenced to GND) Static or Dynamic Voltage Across Switch GND VIO* TA Operating Temperature Range, All Package Types Input Rise/Fall Time (Channel Select or Enable Inputs) - 55 0 0 0 0 + 125 1000 600 500 400
_C
ns
tr, tf
VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V
*For voltage drops across switch greater than 1.2V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
DC CHARACTERISTICS -- Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted
Symbol VIH Parameter Minimum High-Level Input Voltage, Channel-Select or Enable Inputs Maximum Low-Level Input Voltage, Channel-Select or Enable Inputs Maximum Input Leakage Current, Channel-Select or Enable Inputs Maximum Quiescent Supply Current (per Package) Condition Ron = Per Spec VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 6.0 Guaranteed Limit -55 to 25C 1.50 2.10 3.15 4.20 0.5 0.9 1.35 1.8 0.1 85C 1.50 2.10 3.15 4.20 0.5 0.9 1.35 1.8 1.0 125C 1.50 2.10 3.15 4.20 0.5 0.9 1.35 1.8 1.0 Unit V
VIL
Ron = Per Spec
V
Iin ICC
Vin = VCC or GND, VEE = - 6.0 V Channel Select, Enable and VIS = VCC or GND; VEE = GND VIO = 0 V VEE = - 6.0
A A
6.0 6.0
1 4
10 40
20 80
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
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MC74HC4051A, MC74HC4052A, MC74HC4053A
DC CHARACTERISTICS -- Analog Section
Guaranteed Limit Symbol Ron Parameter Maximum "ON" Resistance Condition Vin = VIL or VIH; VIS = VCC to VEE; IS 2.0 mA (Figures 1, 2) Vin = VIL or VIH; VIS = VCC or VEE (Endpoints); IS 2.0 mA (Figures 1, 2) Ron Maximum Difference in "ON" Resistance Between Any Two Channels in the Same Package Maximum Off-Channel Leakage Current, Any One Channel Vin = VIL or VIH; VIS = 1/2 (VCC - VEE); IS 2.0 mA Vin = VIL or VIH; VIO = VCC - VEE; Switch Off (Figure 3) VCC 4.5 4.5 6.0 4.5 4.5 6.0 4.5 4.5 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 VEE 0.0 - 4.5 - 6.0 0.0 - 4.5 - 6.0 0.0 - 4.5 - 6.0 - 6.0 - 6.0 - 6.0 - 6.0 - 6.0 - 6.0 - 6.0 -55 to 25C 190 120 100 150 100 80 30 12 10 0.1 0.2 0.1 0.1 0.2 0.1 0.1 85C 240 150 125 190 125 100 35 15 12 0.5 2.0 1.0 1.0 2.0 1.0 1.0 125C 280 170 140 230 140 115 40 18 14 1.0 4.0 2.0 2.0 4.0 2.0 2.0 A Unit
Ioff
A
Maximum Off-Channel HC4051A Vin = VIL or VIH; Leakage Current, HC4052A VIO = VCC - VEE; Common Channel HC4053A Switch Off (Figure 4) Ion Maximum On-Channel HC4051A Vin = VIL or VIH; Leakage Current, HC4052A Switch-to-Switch = Channel-to-Channel HC4053A VCC - VEE; (Figure 5)
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol tPLH, tPHL Parameter Maximum Propagation Delay, Channel-Select to Analog Output (Figure 9) VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 Guaranteed Limit -55 to 25C 270 90 59 45 40 25 12 10 160 70 48 39 245 115 49 39 10 35 130 80 50 1.0 85C 320 110 79 65 60 30 15 13 200 95 63 55 315 145 69 58 10 35 130 80 50 1.0 125C 350 125 85 75 70 32 18 15 220 110 76 63 345 155 83 67 10 35 130 80 50 1.0 Unit ns
tPLH, tPHL
Maximum Propagation Delay, Analog Input to Analog Output (Figure 10)
ns
tPLZ, tPHZ
Maximum Propagation Delay, Enable to Analog Output (Figure 11)
ns
tPZL, tPZH
Maximum Propagation Delay, Enable to Analog Output (Figure 11)
ns
Cin CI/O
Maximum Input Capacitance, Channel-Select or Enable Inputs Maximum Capacitance (All Switches Off) Analog I/O Common O/I: HC4051A HC4052A HC4053A Feedthrough
pF pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D) Typical @ 25C, VCC = 5.0 V, VEE = 0 V CPD Power Dissipation Capacitance (Figure 13)* HC4051A HC4052A HC4053A 45 80 45 pF
* Used to determine the no-load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
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MC74HC4051A, MC74HC4052A, MC74HC4053A
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
VCC V VEE V `51 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 -2.25 -4.50 -6.00 -2.25 -4.50 -6.00 -2.25 -4.50 -6.00 -2.25 -4.50 -6.00 -2.25 -4.50 -6.00 -2.25 -4.50 -6.00 -2.25 -4.50 -6.00 80 80 80 Limit* 25C `52 95 95 95 -50 -50 -50 -40 -40 -40 25 105 135 35 145 190 -50 -50 -50 -60 -60 -60 % 2.25 4.50 6.00 -2.25 -4.50 -6.00 0.10 0.08 0.05 dB mVPP `53 120 120 120 dB Unit MHz
Symbol BW
Parameter Maximum On-Channel Bandwidth or Mi i Minimum Frequency Response F R (Figure 6)
Condition fin = 1MHz Sine Wave; Adjust fin Voltage to Obtain 0dB Obt i 0dBm at VOS; Increase fin t I Frequency Until dB Meter Reads -3dB; RL = 50, CL = 10pF fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at VIS fin = 10kHz, RL = 600, CL = 50pF
--
Off-Channel Feedthrough Isolation (Figure 7)
fin = 1.0MHz, RL = 50, CL = 10pF -- Feedthrough Noise. Channel-Select Input to Common I/O (Figure 8) Vin 1MHz Square Wave (tr = tf = 6ns); Adjust RL at Setup so that IS = 0A; Enable = GND RL = 600, CL = 50pF
RL = 10k, CL = 10pF -- Crosstalk Between Any Two Switches (Figure 12) (Test does not apply to HC4051A) fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at VIS fin = 10kHz, RL = 600, CL = 50pF
fin = 1.0MHz, RL = 50, CL = 10pF THD Total Harmonic Distortion (Figure 14) fin = 1kHz, RL = 10k, CL = 50pF THD = THDmeasured - THDsource VIS = 4.0VPP sine wave VIS = 8.0VPP sine wave VIS = 11.0VPP sine wave
*Limits not tested. Determined by design and verified by qualification. 300 Ron , ON RESISTANCE (OHMS) Ron , ON RESISTANCE (OHMS) 250 200 125C 150 100 50 0 25C - 55C 180 160 140 120 100 80 60 40 20 0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25 0 0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25 2.5 2.75 3.0 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE - 55C 125C 25C
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
Figure 1a. Typical On Resistance, VCC - VEE = 2.0 V
Figure 1b. Typical On Resistance, VCC - VEE = 3.0 V
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MC74HC4051A, MC74HC4052A, MC74HC4053A
120 Ron , ON RESISTANCE (OHMS) Ron , ON RESISTANCE (OHMS) 100 80 60 25C 40 - 55C 20 0 105 90 75 60 25C 45 - 55C 30 15 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 125C
125C
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
Figure 1c. Typical On Resistance, VCC - VEE = 4.5 V
Figure 1d. Typical On Resistance, VCC - VEE = 6.0 V
80 Ron , ON RESISTANCE (OHMS) Ron , ON RESISTANCE (OHMS) 70 60 50 40 30 20 10 0 -4.5 -3.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 25C - 55C 125C
60 50 125C 40 25C 30 - 55C 20 10 0 -6.0 -5.0 -4.0 -3.0 -2.0 -1.0
0
1.0
2.0
3.0 4.0
5.0
6.0
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
Figure 1e. Typical On Resistance, VCC - VEE = 9.0 V
Figure 1f. Typical On Resistance, VCC - VEE = 12.0 V
PLOTTER
PROGRAMMABLE POWER SUPPLY - +
MINI COMPUTER
DC ANALYZER
VCC DEVICE UNDER TEST
ANALOG IN
COMMON OUT
GND
VEE
Figure 2. On Resistance Test Set-Up
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MC74HC4051A, MC74HC4052A, MC74HC4053A
VCC VCC
VEE OFF VCC A NC OFF
16
VCC
VEE VCC
16 ANALOG I/O OFF OFF
VCC
COMMON O/I
COMMON O/I
VIH
6 7 8
VIH
6 7 8
VEE
VEE
Figure 3. Maximum Off Channel Leakage Current, Any One Channel, Test Set-Up
Figure 4. Maximum Off Channel Leakage Current, Common Channel, Test Set-Up
VCC A ON VEE VCC ANALOG I/O VIL 6 7 8 OFF
16
VCC fin COMMON O/I N/C
0.1F ON
VCC 16
VOS dB METER CL* RL
6 7 8 VEE *Includes all probe and jig capacitance
VEE
Figure 5. Maximum On Channel Leakage Current, Channel to Channel, Test Set-Up
Figure 6. Maximum On Channel Bandwidth, Test Set-Up
VIS 0.1F fin RL OFF
VCC 16
VOS dB METER CL* RL RL ON/OFF ANALOG I/O OFF/ON RL
VCC 16 COMMON O/I RL CL* TEST POINT
6 7 8 VEE VIL or VIH CHANNEL SELECT *Includes all probe and jig capacitance
Vin 1 MHz tr = tf = 6 ns VEE VCC GND
6 7 8
VCC 11
CHANNEL SELECT *Includes all probe and jig capacitance
Figure 7. Off Channel Feedthrough Isolation, Test Set-Up
Figure 8. Feedthrough Noise, Channel Select to Common Out, Test Set-Up
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MC74HC4051A, MC74HC4052A, MC74HC4053A
VCC VCC CHANNEL SELECT tPLH ANALOG OUT 50% GND tPHL 6 7 8 CHANNEL SELECT *Includes all probe and jig capacitance ON/OFF ANALOG I/O OFF/ON CL* VCC 16 COMMON O/I TEST POINT
50%
Figure 9a. Propagation Delays, Channel Select to Analog Out
Figure 9b. Propagation Delay, Test Set-Up Channel Select to Analog Out
VCC 16 VCC 50% GND tPLH ANALOG OUT 50% tPHL 6 7 8 ANALOG I/O ON CL* COMMON O/I TEST POINT
ANALOG IN
*Includes all probe and jig capacitance
Figure 10a. Propagation Delays, Analog In to Analog Out
Figure 10b. Propagation Delay, Test Set-Up Analog In to Analog Out
tf ENABLE tPZL ANALOG OUT 50%
tr 90% 50% 10% tPLZ VCC GND HIGH IMPEDANCE 10% tPZH tPHZ VOL VCC 1 2 1 2
POSITION 1 WHEN TESTING tPHZ AND tPZH POSITION 2 WHEN TESTING tPLZ AND tPZL VCC 16 ANALOG I/O ON/OFF CL* ENABLE
1k TEST POINT
ANALOG OUT
90% 50%
VOH HIGH IMPEDANCE
6 7 8
Figure 11a. Propagation Delays, Enable to Analog Out
Figure 11b. Propagation Delay, Test Set-Up Enable to Analog Out
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MC74HC4051A, MC74HC4052A, MC74HC4053A
VCC VIS VCC RL fin 0.1F OFF VEE RL 6 7 8 *Includes all probe and jig capacitance RL CL* RL CL* VEE 6 7 8 VCC 11 ON 16 VOS ANALOG I/O OFF/ON ON/OFF 16 COMMON O/I NC A
CHANNEL SELECT
Figure 12. Crosstalk Between Any Two Switches, Test Set-Up
0 VCC 16 ON RL CL* VOS TO DISTORTION METER dB - 10 - 20 - 30 - 40 - 50 - 60 6 7 8 VEE *Includes all probe and jig capacitance - 70 - 80 - 90 - 100
Figure 13. Power Dissipation Capacitance, Test Set-Up
VIS 0.1F fin
FUNDAMENTAL FREQUENCY
DEVICE SOURCE
1.0
2.0 FREQUENCY (kHz)
3.125
Figure 14a. Total Harmonic Distortion, Test Set-Up
Figure 14b. Plot, Harmonic Distortion
APPLICATIONS INFORMATION The Channel Select and Enable control pins should be at VCC or GND logic levels. VCC being recognized as a logic high and GND being recognized as a logic low. In this example: VCC = +5V = logic high GND = 0V = logic low The maximum analog voltage swings are determined by the supply voltages VCC and VEE. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below VEE. In this example, the difference between VCC and VEE is ten volts. Therefore, using the configuration of Figure 15, a maximum analog signal of ten volts peak-to-peak can be controlled. Unused analog inputs/outputs may be left floating (i.e., not connected). However, tying unused analog inputs and outputs to VCC or GND through a low value resistor helps minimize crosstalk and feedthrough noise that may be picked up by an unused switch. Although used here, balanced supplies are not a requirement. The only constraints on the power supplies are that: VCC - GND = 2 to 6 volts VEE - GND = 0 to -6 volts VCC - VEE = 2 to 12 volts and VEE GND When voltage transients above VCC and/or below VEE are anticipated on the analog channels, external Germanium or Schottky diodes (Dx) are recommended as shown in Figure 16. These diodes should be able to absorb the maximum anticipated current surges during clipping.
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MC74HC4051A, MC74HC4052A, MC74HC4053A
+5V +5V -5V 16 ANALOG SIGNAL ON ANALOG SIGNAL +5V -5V VCC Dx Dx VEE 6 7 8 -5V 11 10 9 TO EXTERNAL CMOS CIRCUITRY 0 to 5V DIGITAL SIGNALS VEE VCC 16 ON/OFF Dx VEE VCC Dx
7 8
Figure 15. Application Example
Figure 16. External Germanium or Schottky Clipping Diodes
+5V +5V VEE +5V VEE 16 ANALOG SIGNAL ON/OFF ANALOG SIGNAL +5V VEE +5V LSTTL/NMOS CIRCUITRY VEE 6 7 8 11 10 9 HCT BUFFER LSTTL/NMOS CIRCUITRY
+5V +5V VEE 16 ANALOG SIGNAL ON/OFF ANALOG SIGNAL +5V * R R
R
6 7 8 VEE
11 10 9 * 2K R 10K
a. Using Pull-Up Resistors
b. Using HCT Interface
Figure 17. Interfacing LSTTL/NMOS to CMOS Inputs
11 LEVEL SHIFTER 13
A
X0
14
X1
B
10
LEVEL SHIFTER
15
X2
12
X3
C
9
LEVEL SHIFTER
1
X4
5
X5
ENABLE
6
LEVEL SHIFTER
2
X6
4
X7
3
Figure 18. Function Diagram, HC4051A
X
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MC74HC4051A, MC74HC4052A, MC74HC4053A
A 10 LEVEL SHIFTER 12 X0
14
X1
B
9
LEVEL SHIFTER
15
X2
11 13 ENABLE 6 LEVEL SHIFTER 1
X3 X Y0
5
Y1
2
Y2
4
Y3
3
Y
Figure 19. Function Diagram, HC4052A
A
11
LEVEL SHIFTER
13
X1
12 14 B 10 LEVEL SHIFTER 1
X0 X Y1
2 15 C 9 LEVEL SHIFTER 3
Y0 Y Z1
5 4 ENABLE 6 LEVEL SHIFTER
Z0 Z
Figure 20. Function Diagram, HC4053A
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MC74HC4051A, MC74HC4052A, MC74HC4053A
ORDERING & SHIPPING INFORMATION
Device MC74HC4051AN MC74HC4051AD MC74HC4051ADR2 MC74HC4051ADT MC74HC4051ADTR2 MC74HC4051ADW MC74HC4051ADWR2 MC74HC4051AF MC74HC4051AFEL MC74HC4052AN MC74HC4052AD MC74HC4052ADR2 MC74HC4052ADT MC74HC4052ADTR2 MC74HC4052ADW MC74HC4052ADWR2 MC74HC4052AF MC74HC4052AFEL MC74HC4053AN MC74HC4053AD MC74HC4053ADR2 MC74HC4053ADT MC74HC4053ADTR2 MC74HC4053ADW MC74HC4053ADWR2 MC74HC4053AF MC74HC4053AFEL Package PDIP-16 SOIC-16 SOIC-16 TSSOP-16 TSSOP-16 SOIC WIDE SOIC WIDE SOEIAJ-16 SOEIAJ-16 PDIP-16 SOIC-16 SOIC-16 TSSOP-16 TSSOP-16 SOIC WIDE SOIC WIDE SOEIAJ-16 SOEIAJ-16 PDIP-16 SOIC-16 SOIC-16 TSSOP-16 TSSOP-16 SOIC WIDE SOIC WIDE SOEIAJ-16 SOEIAJ-16 Shipping 500 Units / Unit Pak 48 Units / Rail 2500 Units / Tape & Reel 96 Units / Rail 2500 Units / Tape & Reel 48 Units / Rail 1000 Units / Tape & Reel See Note 1. See Note 1. 500 Units / Unit Pak 48 Units / Rail 2500 Units / Tape & Reel 96 Units / Rail 2500 Units / Tape & Reel 48 Units / Rail 1000 Units / Tape & Reel See Note 1. See Note 1. 500 Units / Unit Pak 48 Units / Rail 2500 Units / Tape & Reel 96 Units / Rail 2500 Units / Tape & Reel 48 Units / Rail 1000 Units / Tape & Reel See Note 1. See Note 1.
1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.
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13
MC74HC4051A, MC74HC4052A, MC74HC4053A
PACKAGE DIMENSIONS
PDIP-16 N SUFFIX CASE 648-08 ISSUE R
-A -
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 0.250 0.270 6.85 6.35 0.145 0.175 4.44 3.69 0.015 0.021 0.53 0.39 0.040 0.070 1.77 1.02 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.008 0.015 0.38 0.21 0.110 0.130 3.30 2.80 0.295 0.305 7.74 7.50 10 0 10 0 0.020 0.040 1.01 0.51
B
1 8
F S
C
L
-T - H G D 16 PL 0.25 (0.010)
M
SEATING PLANE
K
J TA
M
M
SOIC-16 D SUFFIX CASE 751B-05 ISSUE J
-A -
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 6.20 5.80 0.50 0.25 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019
-B -
1 8
P 8 PL 0.25 (0.010)
M
B
M
G F
K C -T SEATING -
PLANE
R X 45
M D 16 PL 0.25 (0.010)
M
J
T
B
S
A
S
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MC74HC4051A, MC74HC4052A, MC74HC4053A
PACKAGE DIMENSIONS
SOIC-16 WIDE DW SUFFIX CASE 751G-03 ISSUE B
D
16 M 9
A
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 10.15 10.45 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
B
1
8
16X
B TA
S
B B
S
h X 45 _
M
8X
0.25
E
0.25
M
A1
14X
e
SEATING PLANE
DIM A A1 B C D E e H h L
A
L
T
C
q
TSSOP-16 DT SUFFIX CASE 948F-01 ISSUE O
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16
2X
L/2
9
J1 B -U-
L
PIN 1 IDENT. 1 8
SECTION N-N
J
N 0.25 (0.010) 0.15 (0.006) T U
S
A -V- N F DETAIL E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
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CCC EEE CCC EEE CCC
M
-W-
DIM A B C D F G H J J1 K K1 L M
MC74HC4051A, MC74HC4052A, MC74HC4053A
PACKAGE DIMENSIONS
SOEIAJ-16 F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 966-01 ISSUE O
16 9
LE Q1 E HE M_ L DETAIL P
1
8
Z D e A VIEW P
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.78 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.031
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local Sales Representative.
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16
MC74HC4051A/D

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