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INDEX PRELIMINARY
MX98742
FEBC 100 BASE FAST ETHERNET BRIDGE CONTROLLER
1.0 FEATURES
* * * * * * * * * * * * 2-port MAC bridge supports both Fast Ethernet and Ethernet/Fast Ethernet bridging Minimum 16K byte, maximum 256K byte buffer memory Selectable TX/FX/T4 symbol-level repeater, MII interfaces, and 10BASE serial port T4 symbol mode includes the implementation of all PCS layers functions (8B/6T encode/decode, DE Balance encode/decode, error detection, ....etc.) 512-bit hash filtering Broadcast and Multicast packet filtering and inverse filtering Optional fast forwarding modes minimizes latency Optional dynamic auto buffer sizing JAM-based flow control ensures lossless buffering External Destination and Source Address filtering support Display of buffer boundary and flow-control JAM packet counts LED indication of flow-control JAM events
2.0 GENERAL DESCRIPTION
The Fast Ethernet Bridge Controller (FEBC) is a low-cost solution to link fast Ethernet repeaters together so that the distance between nodes can be expanded far beyond the 200m collision domain limitation. Each network segment connected through the bridge is in a separate collision domain, and the FEBC's function is to exchange all the good packets between two collision domain segments. A 512-bit hash filter is implemented to further reduce the traffic between segments if it is desired. A 10/100 bridge function is also supported. The FEBC has two forwarding modes: (1) store-and forward : a complete packet is buffered before it is to be forwarded. Packets with CRC errors and other anomalies are discarded. (2) 64-byte forward : a packet is forwarded after the first 64 bytes are buffered. The number of bridges that can be put in one network is constrained largely by the buffer memory and performance consideration. Multiple FEBCs are totally invisible to the upper layer protocol. The FEBC supports direct TX PHY interface and 25MHz-MII on both side. Port A of the FEBC also supports TX and T4 repeater ports at the symbobl level and port B of the FEBC also supports the 7-wire serial 10 MHz interface. The FEBC supports buffer memory from minimum 16 Kbytes to 256 Kbytes. The memory is partitioned into two sections with section A as the receive buffer for port A and section B for port B. The size of each section is equal if both sides are operating at 100 Mbps speed; the minimum size of each section is 8 Kbytes. In the auto-sizing mode, the FEBC will change the buffer size according to traffic pattern in each segment.
P/N : PM0403
REV. 1.4, AUG. 5, 1997
1
INDEX
MX98742
3.0 SYSTEM DIAGRAM
3.1 REPEATER WITH A BUILT-IN BRIDGE
PC
SRAM 8K x 8
SRAM 8K x 8
TX TRANSCEIVER
TX Port 100m
100m TX Media PC
TX Port
MAX 100m
TX TRANSCEIVER
MII Port
FEBC MX98742 BRIDGE CONTROLLER
MII Port
XRC MX98741 REPEATER CONTROLLER
PC 100m TX Port TX Port
TX TRANSCEIVER
100BASE-TX REPEATER
T4 Port 100m
PC 100m TX Media
Figure 3-1. A Typical TX Connection
PC
SRAM 8K x 8
SRAM 8K x 8
TX TRANSCEIVER
100m TX Media PC
TX Port
MAX 100m
T4 TRANSCEIVER
MII Port
FEBC MX98742 BRIDGE CONTROLLER
MII Port
XRC MX98741 REPEATER CONTROLLER
PC 100m T4 Port TX Port
TX TRANSCEIVER
100BASE-TX REPEATER
PC 100m TX Media
Figure 3-2. A Typical T4 Connection
2
INDEX
MX98742
4.0 CONNECTION DIAGRAM
VSSP TDAT0_A TDAT1_A TDAT2_A TDAT3_A TDAT4_A TXEN_A VDD TXCLK_A CRS_A SIGDET_A RXCLK_A RXDV_A RXER_A RDAT0_A RDAT1_A RDAT2_A RDAT3_A RDAT4_A VSS OE_A RX2PR0 RX2PR1 RX3PR0 RX3PR1 RX4PR0 RX4PR1 VSSP TX1PR0 TX1PR1 TX3PR0 TX3PR1 TX4PR0 TX4PR1 MSIZE0 MSIZE1 AUTOSIZE FWDMODE0 FWDMODE1 BPDIS
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
T4SEL PKT0_A PKT1_A PKT2_A PKT3_A VSSP PKT4_A PKT5_A PKT6_A PKT7_A VSSP ABYTE0_A ABYTE1_A ABT_A PHY0_A PHY1_A JAMLED_A VSSP RESET JAMLED_B PHY1_B PHY0_B ABT_B ABYTE1_B ABYTE0_B VDDP PKT7_B PKT6_B PKT5_B PKT4_B VSSP PKT3_B PKT2_B PKT1_B PKT0_B VDDP TEST0 TEST1 VDDP VSSP
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
VSSP TDAT0_B TDAT1_B TDAT2_B TDAT3_B TDAT4_B TXEN_B VDD TXCLK_B CRS_B SIGDET_B RXCLK_B RXDV_B RXER_B RDAT0_B RDAT1_B RDAT2_B RDAT3_B RDAT4_B VSS CDAT7 CDAT6 CDAT5 CDAT4 CDAT3 CDAT2 CDAT1 CDAT0 VSSP REGSEL7 REGSEL6 REGSEL5 REGSEL4 REGSEL3 REGSEL2 REGSEL1 REGSEL0 RDY_ CS_ REGR_W
Figure 4-1. 160-pin PQFP Package
MX98742
G_ R_W SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 VSS SD0 SD1 SD2 SD3 VDDP SD4 SD5 SD6 SD7 VSSP SD8 SD9 SD10 SD11 VDDP SD12 SD13 SD14 SD15 VSSP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
3
INDEX
MX98742
5.0 PIN DESCRIPTIONS
Table 5-1. Port A TX Interface (Am79865 and Am79866 or MC68836 or Macronix Data Transceiver or TX repeater port, 13 pins) PIN# 126-122 PIN NAME TDAT4-0_A/TXD3-0_A TYPE O/Z, CMOS DESCRIPTION TX Mode : Transmit Data X Port A. These five outputs driven at the rising edge of TXCLK_A are 4B/5B encoded transmit data symbols. TDAT4 is the Most Significant Bit. MII Mode : Transmit Data MII A. For each TXCLK_A period in which TXEN is asserted, TXD3-0, synchronous to TXCLK_A's rising edge, are driven by the MAC. The value of TXD3-0 is ignored when TXEN is deaserted. TXD3 is the Most Significant Bit. TX Mode : Local Symbol Clock. 25 MHz clock input. TXCLK_A and RXCLK_A should be driven by the same timing reference if the MX98742 interfaces to TX repeater ports. MII Mode : Transmit Clock MII A. 25 MHz transmit clock. TX Mode : Received Data X Port A. These 5-bit parallel data symbols from transceiver are latched by the rising edge of RXCLK_A. RDAT4 is the Most Significant Bit. MII Mode : Receive Data X Port A. For each RXCLK_A period in which RXDV is asserted, RXD3-0, synchronous to RXCLK_A's rising edge, should be latched by the MAC. While RXDV is deasserted, RXD3-0 are the 5B/4B decoded nibbles from RDAT4-0. RXD3 is the Most Significant Bit. TX Mode : Recovered Symbol Clock Port A. This 25 MHz clock input is derived from the clock symchronization PLL circuit. RXCLK_A and TXCLK_A should be driven by the same timing reference if MX98742 interfaces to TX repeater ports. T4 Mode : Recovered Symbol Clock. MII Mode : Receive Clock MII A. 25 MHz continuous clock that provides the timing reference for the transfer of RXDV, RXD and RXER signals.
129
TXCLK_A
I, TTL
139-135
RDAT4-0_A/RXD3-0_A
I, TTL
132
RXCLK_A
I, TTL
4
INDEX
MX98742
131 SIGDET_A/LKGD/COL_A I, TTL TX Mode : Signal Detect Port A. This signal indicates that the received signal is above the detection threshold. If MX98742 interfaces to TX repeater ports, this pin should be pulled high. T4 : Link Good. The link state machine is in Link Pass state. MII Mode : Collision MII A. This signal is asserted if both the receiving media and TXEN are active.
Table 5-2. Port A T4 Symbol Level Interface (Broadcom/Cypress compatible, 17 pins) PIN# 143-142 145-144 147-146 150-149 152-151 154-153 120 132 130 134 131 PIN NAME RX2PR1-0 RX3PR1-0 RX4PR1-0 TX1PR1-0 TX3PR1-0 TX4PR1-0 T4SEL RXCLK_A PMACRS PMARXER LKGD TYPE I, TLL I, TLL I, TLL O/Z, CMOS O/Z, CMOS O/Z, CMOS I, TTL I, TTL I, TTL I, TTL I, TTL DESCRIPTION Receive Pair 2. 00:0V, 01:3.5V, 10:-3.5V. (Broadcom). 00:0V, 01:-3.5V, 10:3.5V. (Cypress) Receive Pair 3. 00:0V, 01:3.5V, 10:-3.5V. (Broadcom). 00:0V, 01:-3.5V, 10:3.5V. (Cypress) Receive Pair 4. 00:0V, 01:3.5V, 10:-3.5V. (Broadcom). 00:0V, 01:-3.5V, 10:3.5V. (Cypress) Transmit Pair 1. 00:0V, 01:3.5V, 10:-3.5V. (Broadcom). 00:0V, 01:-3.5V, 10:3.5V. (Cypress) Transmit Pair 3. 00:0V, 01:3.5V, 10:-3.5V. (Broadcom). 00:0V, 01:-3.5V, 10:3.5V. (Cypress) Transmit Pair 4. 00:0V, 01:3.5V, 10:-3.5V. (Broadcom). 00:0V, 01:-3.5V, 10:3.5V. (Cypress) Transceiver Select : 1 : Broadcom, 0:Crypress Receivered Symbol Clock. PMA Carrier Sense. Mux'd with MII mode pin CRS_A. PMA Receive Error. Mux'd with MII pin RXER_A. Link Good. Mux'd with TX pin SIGDET_A.
5
INDEX
MX98742
Table 5-3. Port A Meddia Independent Interface (15 pins) PIN# 129 127 PIN NAME TXCLK_A TXEN_A TYPE I, TTL O, CMOS DESCRIPTION Transmit Clock MII A. 25MHz transmit clock. Transmit Enable MII A. TXEN_A, synchronous to TXCLK_A's rising edge, is asserted by the MAC with first nibble of the preamble and remains asserted while all nibbles to be transmitted are presented. Transmit Data MII A. TDAT3-0_A. Mux'd with TX mode pins
125-122 133
TXD3-0_A RXDV_A
O, CMOS I,TTL
Receive Data Valid MII A. This signal, synchronous to RXCLK's rising edge, remains asserted through the whole frame, starting with start-of-frame delimiter and excluding any end-of-frame delimiter. MII Mode : Carrier Sense MII A. This pin is asserted when the receiving medium is not idle. T4 Mode : PMA Carrier Sense. This pin, synchronous to RXCLK_A, signals that activity is detected. MII Mode : Receive Error MII A. While RXDV is asserted, i.e. a frame is being received, this signal which is synchronous to RXCLK_A's rising edge is asserted if any coding error is detected. T4 Mode : PMA Receive Error. Misaligment is detected. Receive Clock MII A. Receive Data MII A. RDAT3-0_A. Mux'd with TX mode pins
130
CRS_A/PMACRS
I, TTL
134
RXER_A/PMARXER
I, TTL
132 138-135 131
RXCLK_A RXD3-0_A COL_A
I, TTL I, TTL I, TTL
Collision MII A. Mux'd with TX SIGDET_A.
Table 5-4. Port A Output Control Pin (1 pin) PIN# 141 PIN NAME OE_A TYPE I, TTL DESCRIPTION Output Enable Port A. The assertion of OE_A, active low, enables TDAT4-0 (TX) or TX1_PR1-0, TX3_PR10, TX4_PR1-0 (T4) or TXD3-0 (MII), or TXENA, and it tristates these output pins if held High.
6
INDEX
MX98742
Table 5-5. Port B TX Interface (Am79865 and Am79866 or MC68836 or Macronix Data Transceiver, 13 pins) PIN# 72 PIN NAME TXCLK_B TYPE I, TTL DESCRIPTION TX Mode : Logic Symbol Clock. 25MHz clock input. If the FEBC is used to connected between two TX medum, TXCLK_A and TXCLK_B should be driven by the same reference source. MII Mode : Transmit clock MII B. 25/2.5MHz transmit clock. 7_wire Mode : This is the 10MHz transmit clock which is used only when 7_wire interface is selected at Port B. TX Mode : Transmit Data X Port B. These five outputs driven at the rising edge of TXCLK_B are 4B/5B encoded transmit data symbols. TDAT4 is the Most Significant Bit. MII Mode : Transmit Data MII/B. For each TXCLK_B period in which TXEN is asserted, TXD3-0, synchronous to TXCLK_B's rising edge, are driven by the MAC. The value of TXD3-0 is ignored when TXEN is deasserted. TXD3 is the Most Significant Bit. If 7_wire mode is selected, only TXD0_B is active. TX Mode : Receive Data X Port B. These 5-bit parallel data symbols from transceiver are latched by the rising edge of RXCLK_B. RDAT4 is the Most Signaificant Bit. MII Mode : Receive Data MII/B. For each RXCLK_B period in which RXDV is asserted, RXD3-0, synchronous to RXCLK_B's rising edge, should be latched by the MAC. While RXDV is deasserted, RXD3-0 are the 5B/4B decoded nibbles from RDAT4-0. RXD3 is the Most Significant Bit. If 7_wire mode is selected, only RXD0_B is active. TX Mode : Recovered Symbol Clock Port B. This is a 25MHz clock which is derived from the clock synchronization PLL circuit. RXCLK_B and TXCLK_B should be driven by the same timing reference if MX98742 interfaces to TX repeater ports. MII Mode : Receive Clock MII/B. This is the 25/2.5 MHz continuous clock that provides the timing reference for the transfer of the RXDV, RXD and RXER signals. If 7-Wire mode is selected, this is the 10MHz recovered clock.
75-79
TDAT4-0_B/TXD3-0_B
O, CMOS
62-66
RDAT4-0_B/RXD3-0_B
I, TTL
69
RXCLK_B
I, TTL
7
INDEX
MX98742
70 SIGDET_B/COL_B I, TTL TX Mode : Signal Detect Port B. This signal indicates that the received signal is above the detection threshold. If MX98742 interfaces to TX repeater port, this pin should be pulled high. MII Mode : Collision MII/B. This signal is asserted if both the receiving media and TXEN are active. If 7_wire mode is selected, this pin is the collision signal.
Table 5-6. Port Media Independent Interface (15 pins) PIN# 72 PIN NAME TXCLK_B TYPE I, TTL DESCRIPTION Transmit clock MII/B. 25/2.5 MHz transmit clock. This is the 10MHz transmit clock which is used only when 7_wire mode interface is selected at Port B. Transmit Enable MII/B. TXEN_B, synchronous to the TXCLK_B's rising edge, is asserted by the MAC with the first nibble of the preamble and remains asserted while all nibbles to be transmitted are presented. If 7_wire mode is selected, this pin denotes transmit enable. Transmit Data MII/B. Mux'd with TX mode pins TDAT3-0_B. If 7_wire mode is selected, only TXD0_B is active. Receive Data Valid MII B. This signal, synchronous to RXCLK_B's rising edge, remains asserted through the whole frame, starting with start-of-frame delimiter and excluding any end-of-frame delimiter. Carrier Sense MII/B. This pin is asserted when the receiving medium is not idle. In 7_wire mode is selected, this pin is an asynchronous CRS. Receive Error MII. While RXDV_B is asserted in the case like a frame is received, this signal, synchronous to RXCLK_B's rising edge, is asserted when any coding errors are detected. Receive Clock MII/7_wire B. Receive Data MII/7_wire B. Mux'd with TX mode pins RDAT3-0_B. Collision MII/10 B. Mux'd with TX mode pin SIGDET_B.
74
TXEN_B
O, CMOS
76-79
TXD3-0_B
O, CMOS
68
RXDV_B
I, TTL
71
CRS_B
I, TTL
67
RXER_B
I, TTL
69 63-66 70
RXCLK_B RXD3-0_B COL_B
I, TTL I, TTL I, TTL
8
INDEX
MX98742
Table 5-7. Buffer SRAM Interface (35 pins) PIN# 19-3 PIN NAME SA16-0 TYPE O, CMOS DESCRIPTION SRAM Address 0-16. These 17 address inputs select one of the 16-bit-wide words in the 128K x 16 SRAM buffers. SRAM Data Input/Output Ports. These 16 bi-directional ports are used to read data from or write data into the SRAM.
39-36, 34-31, 29-26, 24-21 2 1
SD15-0
I/O, CMOS
R_W G_
O, CMOS O, CMOS
Write Enable. The write enable input is active low during write cycle to SRAM. Read Enable. The read enable input is active low during read cycle to SRAM.
Table 5-8. Buffer Memory Configuration Pin (5 pins) PIN# 156-155 PIN NAME MSIZE1-0 TYPE I, TTL DESCRIPTION Memory Size. These two pins select buffer memory size. [MSIZE1, MSIZE0]='00' : 16 Kbytes; '01' : 64 Kbytes; '10' : 256 Kbytes; '11' : 128 Kbytes (after rev E) Auto Sizing. When asserted high, this pin activates the Macronix Proprietary auto-sizing algorithm to adjust buffer area dynamically. Forward mode. [FWDMODE1, FWDMODE0]= '00' : full-packet-store-and-forward; '01' : 64-byte-store-and-forward; '10' : half-duplex-and-forward; '11' : full-duples-and-forward mode.
157
AUTOSIZE
I, TTL
159-158
FWDMODE1-0
I, TTL
9
INDEX
MX98742
Table 5-9. Address Field Access Pins (22 pins) PIN# 114-111 PIN NAME PKTD0-7_A TYPE O, CMOS DESCRIPTION Packet Data from Port A. These pins, synchronous to the MII clock RXCLK_A, display the Port A packet data on the aligned byte boundary every two RXCLK_A cycles for each byte. Address Byte from Port A. These two pins, synchronous to RXCLK_A, whose binary value indicates that DA, SA, or data is present on PKT0-7_A. [ABYTE1, ABYTE0]='00' : Idle; ='01' : Data; ='11' : Source Address; ='10' : Destination Address; Abort Packet from Port A. This pin is asserted to signal the FEBC to abort forwarding packet from Port A. In Fast Forward mode of FEBC, the assertion of this signal must be acknowledged by FEBC before the complete receipt of the 64 bytes of data; otherwise a fragment may be sent into the segment due to the late assertion. Packet Data from Port B. These pins, synchronous to the MII clock RXCLK_B, display the Port B packet data on the aligned byte boundary every two RXCLK_B cycles for each byte. Address Byte from Port B. These two pins, synchronous to RXCLK_B, whose binary value indicates that DA, SA, or Data is present on PKT0-7_B. [ABYTE1, ABYTE0]='00' : Idle; ='01' : Data; ='11' : Source Address; ='10' : Destination Address; Abort Packet from Port B. This pin is asserted to signal the FEBC to abort forwarding packet from Port B. In Fast Forward mode of FEBC, the assertion of this signal must be acknowledged by FEBC before the complete receipt of the 64 bytes of data; otherwise a fragment may be sent into the segment due to the late assertion.
108-109
ABYTE1-0_A
O, CMOS
107
ABT_A
I, TTL
86-89 91-94
PKTD0-7_B
O, CMOS
97-96
ABYTE0-1_B
O, CMOS
98
ABT_B
I, TTL
10
INDEX
MX98742
Table 5-10. LED Pins (2 pins) PIN# 104 PIN NAME JAMLED_A TYPE O, CMOS DESCRIPTION JAM LED Port A. Active Low. This pin which is capable of driving LEDs directly denotes that the Port A receive buffer is full. For better visibility, the ON and OFF time of the LEDs should be at least 80 and 20 ms respectively. JAM LED Port B. Active Low. This pin which is capable of driving LEDs directly denotes that the Port B receive buffer is full. For better visibility, the ON and OFF time of the LEDs should be at least 80 and 20 ms respectively.
101
JAMLED_B
O, CMOS
Table 5-11. PHY Configuration Pins (pins) PIN# 105-106 PIN NAME PHY1-0_A TYPE I, TTL DESCRIPTION PHY of Port A. [PHY1_A, PHY0_A] ='00' : 100BASE T4; ='01' : MII; ='10' : 100BASE-FX; ='11' : 100BASE-TX. PHY of Port AB [PHY1_A, PHY0_B] ='00' : 10Base(7_wire); ='01' : MII; ='10' : 100BASE-FX; ='11' : 100BASE-TX.
100-99
PHY1-0_B
I, TTL
Table 5-12. CPU Interface (19 pins) PIN# 60-53 51-44 43 42 41 PIN NAME CDAT[7:0] RegSel[7:0] RDY_ CS_ REGR_W TYPE I/O I, TTL O/Z I,TTL I, TTL DESCRIPTION CPU Data. 8-bit CPU data. CPU Address. This pin selects internal registers. Register Latch. This pin is asserted low by the FEBC to terminate a read or write cycle. Chip Select. This pin enables the read or write access to the registers Register Read Or Write. This pin indicates Read or Write on the registers
11
INDEX
MX98742
Table 5-13. Miscellaneous Pins (2 pins) PIN# 160 102 PIN NAME BPDIS RESET_ TYPE I, TTL I, TTL DESCRIPTION Back Pressure Disable:This pin, active high, disables the back pressure mechanism. Reset. Active low. This signal is an output from the system to reset all the logic on the chip.
Table 5-14. Test Pins/ Power/ Ground, 22 pins PIN# 83-4 PIN NAME TEST1-0 TYPE I, TTL DESCRIPTION Test pins. [TEST1, TEST0] ='00' : notmal operation, back pressure=2; '01', '10' : internal functions checking; '11' : normal operation, back pressure=; 5V Power Supply.
128, 95, 85, 82, 73, 35, 25 148, 140 121, 115, 110, 103, 90, 81, 80, 61, 52, 40, 30, 20
VCC
GND
Ground.
6.0 OPERATION DESCRIPTION
The MX98742 FEBC is equipped with user-configurable modes which provides media flexibility or 100BASE-TX, 100BASE-FX, T4, MII, and 10BASE-T by using pins PHY0-1_A and PHY0-1_B. Three types of operations for FEBC are illustrated below:
12
INDEX
MX98742
6.1 BUILD-IN BRIDGE APPLICATION
SRAM 8K x 8
SRAM 8K x 8
TX Media
TX TWISTED PAIR TRANSCEIVER
TX CLOCK RECOVERY CHIP
TX Port
FEBC MX98742 BRIDGE CONTROLLER
MII Port
XRC MX98741 REPEATER CONTROLLER
Figure 6-1. TX Connection With MX98741
SRAM 8K x 8
SRAM 8K x 8
T4 Media
T4 TRANSCEIVER
MII Port
FEBC MX98742 BRIDGE CONTROLLER
MII Port
XRC MX98741 REPEATER CONTROLLER
Figure 6-2. T4 Connection With MX98741
13
INDEX
MX98742
6.2 SPARE MII APPLICATION
XRC MX98741 REPEATER CONTROLLER TX Port TX CLOCK RECOVERY CHIP TX Port FEBC MX98742 BRIDGE CONTROLLER TX Port TX TWISTED-PAIR TRANSCEIVER TX CLOCK RECOVERY CHIP
TX Media TX TWISTED-PAIR TRANSCEIVER
TX Media
Figure 6-3. Alternative TX Connection With MX98741
NS83850 REPEATER CONTROLLER MII Port TX TWISTED-PAIR TRANSCEIVER MII Port
ML 6691
TX Media
FEBC MX98742 BRIDGE CONTROLLER MII Port TX CLOCK RECOVERY CHIP
TX TWISTED-PAIR TRANSCEIVER
TX Media
Figure 6-4. TX Connection With NS83850
14
INDEX
MX98742
6.3 STAND-ALONE BRIDGE APPLICATION
SRAM 8K x 8
SRAM 8K x 8
TX Media
TX TWISTED PAIR TRANSCEIVER
TX CLOCK RECOVERY CHIP
TX Port
FEBC MX98742 BRIDGE CONTROLLER
TX Port
TX CLOCK RECOVERY CHIP
FX FIBER TRANSCEIVER
FX Media
Figure 6-5. TX/FX Bridging
SRAM 8K x 8
SRAM 8K x 8
TX Media
TX TWISTED PAIR TRANSCEIVER
TX CLOCK RECOVERY CHIP
TX Port
FEBC MX98742 BRIDGE CONTROLLER
MII Port
T4 TRANSCEIVER
T4 Media
Figure 6-6. TX/T4 Bridging
SRAM 8K x 8
SRAM 8K x 8
TX Media
TX TWISTED PAIR TRANSCEIVER
TX CLOCK RECOVERY CHIP
TX Port
FEBC MX98742 BRIDGE CONTROLLER
MII Port
10-BASE TWISTED PAIR TRANSCEIVER
10-BASE Media
Figure 6-7. TX/10 BASE-T Bridging
15
INDEX
MX98742
6.4 CLOCK CONNECTION TO THE FEBC
TXCLK_A TX Mode
Port A 100BASE
FEBC MX98742 BRIDGE CONTROLLER
Port B 100 BASE
TXCLK_B TX Mode
25MHz
Figure 6-8. TX/TX Mode
TXCLK_A 25MHz MII Mode
Port A 100BASE
FEBC MX98742 BRIDGE CONTROLLER
25MHz Port B 100 BASE TXCLK_B MII Mode T4 Transceiver
Figure 6-9. MII/MII Mode
TXCLK_A 25MHz TX Mode
Port A 100BASE
FEBC MX98742 BRIDGE CONTROLLER
Port B 100 BASE
10MHz TXCLK_B Serial Mode
10 BASE Transceiver
Figure 6-10. TX/Serial Mode
16
INDEX
MX98742
6.5 ML6691-MX98742 INTERFACE
VCC
NS83850 MII Port
ML6691
SD TSM4-0 RSM4-0 RXC TXC
5 5
SIGDET RXD4-0 TXD4-0 RXC TXC
MX98742
25MHz
Figure 6-11. ML6691-MX98742 Interface
7.0 PHYSICAL INTERFACE AND SELECTION
The FEBC provides 4 physical interfaces on port A and B. The TX/FX interfaces can be connected to a repeater controller's TX port or a TX PHY chip. The T4 interface is connected to a repeater controller's T4 port only. The speed selection algorithm is described in the following table: PHY1 0 0 1 1 PHY0 0 1 0 1 PHY Selection Port A : T4; Port B : 10BASE (7_wire) MII FX TX
17
INDEX
MX98742
8.0 BUFFER MANAGERMENT
8.1 BUFFER CONFIGURATION
The FEBC requires a minumum of 16K-byte buffer which has to be implemented with high-speed (25 ns or faster) SRAMs. A 16K-byte buffer SRAM is configured initially as the following:
Port A Packet 1 Port A Packet 2 Port A Packet 3
0K 2K 4K 6K
12K Port A Packet 2 Port A Packet 1 14K 16K
The first 2 bytes of each buffer is for the status storage. The FEBC writes the packet length in the storage at the end of receiving. A 'bad' packet is rejected at the end and the buffer is reclaimed. If both sides are selected at 100Mps after reset, the buffer sizes for A and B are equal. However, if port B is operated at 7_wire mode, then the ratio of the two buffer sizes of the 100Mbps and 10Mbps is 7:1. In the Macronix Proprietary auto-sizing mode, the FEBC can dynamically adjust the buffer area size. For example, if buffer A is full and buffer B is still available; buffer A will grow into buffer B's area, and vice versa.
18
INDEX
MX98742
8.2 BUFFER ACCESS
Receive MAC
Buffer Management
Receive MAC
Transmit MAC Transmit MAC Hash Filter
Buffer B
Buffer A
Figure 8-1. Simplified Block Diagram The minimum size of a packet buffer is 2 Kbytes; therefore, a maximum-size packet, 1518 bytes can always be accommodated once a buffer is available. Combined with back-pressure flow control, a packet will never be lost due to buffer overflow. The A buffer starts with an address 0, and the port B buffer starts with the maximum address e.g. 16k. The accesses from both ports are interleaved to guarantee the bandwidth. The buffer memory access has 4 modes: (1) receiving from A, transmitting to B, (2) receiving from B, transmitting to A, (3) receiving from A, receiving from B, (4) transmitting to A, transmitting to B. If port A buffer is full and CRS_A is high, then a JAM packet which length is 1024 bytes will be sent out to generate collision in A segment. JAM packet will be sent continuously until a buffer space is available. The total number of JAM sequences that can be sent consecutively is programmable. Once the terminal count is reached, no more JAM sequences are sent, and the flow-control JAM mechnism is disabled. Consequently any new packets sent from the network are lost. The JAM mechanism of port A will be restored if the associated buffer is available again. If auto-sizing is enabled, the buffer boundary will be changed according to the need. For example, if A buffer is full and B buffer still has an unused space adjacent to A buffer, then A buffer will get one packet buffer (2KByte) from B buffer. The packet buffer B space that is assigned to A segment will remain unless B buffer segment has a need to reclaim it. The starting address of the last packet buffer in A segment can be read from a status register through register access pins.
19
INDEX
MX98742
9.0 FILTERING FUNCTIONS, FORWARDING MODES AND EXTERNAL FILTERING FUNCTIONS
9.1 FILTERING FUNCTIONS
FEBC provides a total of six filtering functions. Filters 1, 2, 3, and 4 can be implemented simultaneously, while Filters 4, 5, and 6 can be implemented simulneously: 1. Broadcast Packet Filter:Packets with all 1's in the 48-bit Destination Address will not be forwarded. 2. Multicast Packet Filter:Packets with '1' in the Group address bit will not be forwarded. This does not include Broadcast packets. 3. Self-Addressing Packet (DA=SA) Filter:Packets with same Destination Address and Source Address will not be forwarded. 4. 512-bit Hash Filter:The Destination Address of an incoming packet is fed through the standard Ethernet 32-bit CRC function. The 9 most significant bits of the decoded results are used to index a unique hash-filtering bit in the hash table. If the index bit is set, the packet is filtered (not forwarded). The packet is forwarded only when the index bit is cleared. 5. Inverse Broadcast Filter:Packets with 1's in the 48-bit Destination Address as well as hash filtered packets will be forwarded. 6. Inverse Multicast Packet Filter:Packets with '1' in the Group Address bit as well as hash filtered packets will be forwarded. This does not include Broadcast packets. All the possible combinations of the above mentioned filtering schemes are listed below: Table 9-1. B 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 0 0 0 0 0 1 1 1 1 M 0 0 0 0 1 1 1 1 0 0 0 0 S 0 0 1 1 0 0 1 1 0 0 1 1 H 0 1 0 1 0 1 0 1 0 1 0 1 IB 0 0 0 0 0 0 0 0 0 0 0 0 IM 0 0 0 0 0 0 0 0 0 0 0 0 DESCRIPTION All packets are accepted. Hash-filtering addressed packets are filtered. Self-addressing packets are filtered. Hash-filtering & self-addressing packets are filtered. Multicast addressed packets are filtered. Multicast & Hash-filtering addressed packets are filtered. Multicast & Self-addressing packets are filtered. Multicast, Self-addressing, & Hash-filtering packets are filtered. Broadcast addressed packets are filtered. Broadcast & Hash-filtering addressed packets are filtered. Broadcast, Self-filtering addressed packets are filtered. Broadcast, Self-addressing & Hash-filtering packets are filtered.
20
INDEX
MX98742
13 14 15 16 17 18 19 20 21 22 Note: 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 1 0 0 0 1 1 1 0 0 0 0 0 1 1 0 1 1 0 0 0 0 1 0 1 1 0 1 Broadcast, Multicast addressed packets are filtered. Broadcast, Multicast & Hash-filtering packets are filtered. Broadcast, Multicast & Self-addressing packets are filtered. Inverse Broadcast & Inverse Multicast addressed packets are accepted. Inverse Multicast addressed packets are filtered. Inverse Broadcast addressed packets are filtered. Inverse Multicast & Inverse Broadcast addressed packets are filtered. Hash-filtering & Inverse Multicast addressed packets are filtered. Hash-filtering & Inverse Broadcast addressed packets are filtered. Hash-filtering, Inverse Brocast & Inverse Multicast packets are filtered. S : Self-Addressing Packet Filter; IM : Inverse Multicast Packet Filter.
B : Broadcast Packet Filter; H : 512-bit Hash Filter;
M : Multicast Packet Filter; IB : Inverse Broadcast Filter;
9.2. FORWARDING MODES Two forwarding modes are implemented: 1. Full-Packet Store and Foward:In this mode, a packet is forwarded only after the complete packet is received. An ill-formed packet will be discarded and the buffer reclaimed. 2. 64-byte-store-and-Forward:In the 64-byte mode. the FEBC attempts to forward a packet once the first 64 bytes are received without collision. This method introduces lower latency but carrier the risk of forwarding an ill-formed packet into next segment. This mode is not valid if there are still packets inside the buffer need to be transmitted. 3. Half-duplex-and-Forward (Test Mode 1):In this mode, no buffer memory is required. The data from one port is transmitted to another port directly. Collision sensed on one port will cause JAM sequence to be generated for as long as it lasts. This mode is useful when the bridge is used as a timing device to connect different PHY devices. If 100 meter UTP cable is attached to the bridge, the other end must be a DTE. 4. Full-duplex-and-forward-mode (Test Mode 2):In this mode, no buffer memory is required. The bridge functions strictly as a relay. The data can flow toward both directions at the same time. Both PHY interfaces to port A and Port B must be TX or FX and the collision detection in PCS is disabled. No flow control mechansim is implemented.
21
INDEX
MX98742
9.3. EXTERNAL FILTERING FUNCTIONS The incoming packet is displayed on the PKTD7-0 starting at the data. The two pins ABYTE1 and ABYTE0 indicates the content of PKTD7-0. Destination Address and Source Address of a packet received can be easily extracted from PKT D7-0 according to hte following table: ABYTE1 1 1 0 0 ABYTE0 0 1 1 0 PKT7-0 Destination Address Source Address Data Idle
The forwarding action can be terminated by asserting ABT_A or ABT_B. The FEBC's response to the assertion of ABT depends on the timing. The ABT functions are independent of forwarding modes and filtering modes. Upon receipt of the asserted ABT signal, the FEBC will either (1) reclaim the buffer if transmitting has not started or (2) terminate transmission immediately and result in incomplete packet being forwarded.
10.0 MAC
The two MACs in the FEBC are IEEE 802.3 compliant except the following: (1) A JAM packet could be sent to a segment to suppress more traffic until at least one buffer is available. (2) The length of the JAM packet is 1024 bytes. The back pressure function can be disabled by pulling BP_DIS pin high. The MAC does not expect CRS to be looped back while transmitting; i.e. the MAC can work with RXEN doubling as CRS.
11.0 REGISTERS
There are 8-bit registers in FEBC, that can be selected through REGSEL[7:0] REGSEL[7:0] 0000, 0000 0000, 0001 0000, 0010 0000, 0011 0000, 0100 0000, 0101 0000, 0110 0000, 0111 0000, 1000 REGISTER DESCRIPTION Reset Register JAM Control Register Forward Mode Register Filtering Mode Register JAM Counter A - upper 8-bit JAM Counter A - lower 8-bit JAM Counter B - upper 8-bit JAM Counter B - lower 8-bit Buffer Status R/W R/W R/W R/W R/W R R R R R
22
INDEX
MX98742
0000, 1001 0000, 1010 0000, 1011 0000, 1100 0000, 1101 0000, 1110 0000, 1111 0001, 0000-0011, 1111 0100, 0000 0100, 0001-0111, 1110 0111, 1111 1000, 0000-1011, 1111 1100, 0000 1100, 0001-1111, 1110 1111, 1111 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Hash Filter byte 0_A Hash Filter byte 1-62_A Hash Filter byte 63_A Reserved Hash Filter byte 0_B Hash Filter byte 1-62_B Hash Filter byte 63_B R/W R/W R/W R/W R/W R/W R R R R R R/W R/W
11.1
RESET REGISTER (R/W)
RST Bit:7 Bit:6 Bit:5 Bit:4 Bit:3 Bit:2 Bit:1 Bit:0
Table 11-1 Reset Register R/W BIT(S) 0 SYMBOL RST DESCRIPTION Reset 1:Reset (disable)FEBC. 0:Not reset (disable)FEBC. After power-up reset, RST is cleared to "0". Don't care. R/W R/W
1-7
Reserved
23
INDEX
MX98742
11.2 JAM CONTROL REGISTER (R/W)
JAS1 Bit:7 JAS0 Bit:6 JADIS Bit:5 Bit:4 JBS1 Bit:3 JBS0 Bit:2 JBDIS Bit:1 Bit:0
JAS1 and JAS0 are the JAM selection bits for port A. These two bits determine the number of consecutive JAM packets sent to port A for flow-control. Each JAM packet is 1024 bytes which is less than Jabber timer. After the count is up, no more JAM will be sent to a busy segment, and the flow-control jamming mechanism is disabled. It will be enabled again once one packet buffer is available. JBS1 and JBS0 are the JAM selection bits for port B. These two bits determine the number of consecutive JAM packets sent to port B for flow-control. Each JAM packet is 1024 bytes which is less than Jabber timer. After the count is up, no more JAM will be sent to a busy segment, and the flow-control jamming mechanism is disabled. It will be enabled again once one packet buffer is available. Table 11-2 JAM Control Register R/W BIT(S) 7-6 SYMBOL JAS1-0 DESCRIPTION JAM Selection Port A JAS1 JAS0 Number of Consecutive JAM into port A 0 0 2 (default) 0 1 4 1 0 8 1 1 infinity JAM Port A is Disabled 1:JAM function on port A is disabled. 0:JAM function on port A is enabled. This bit is valid only if BPDIS pin is tied low; JADIS is cleared to '0' after power-up reset. R/W R/W
5
JADIS
R/W
4 3-2
Reserved JBS1-0 JAM Selection Port B JBS1 JBS0 Number of Consecutive JAM into port A 0 0 2 (default) 0 1 4 1 0 8 1 1 infinity JAM Port B is Disabled 1:JAM function on port B is disabled. 0:JAM function on port B is enabled. This bit is valid only if BPDIS pin is tied low; JADIS is cleared to '0' after power-up reset. R/W
1
JBDIS
R/W
0
Reserved
24
INDEX
MX98742
11.3 FILTERING MODE REGISTER
BCSF Bit:7 MCSF Bit:6 SAF Bit:5 HF Bit:4 IBCSF Bit:3 IMCSF Bit:2 Bit:1 Bit:0
After power-up reset, no filtering is performed at all and all packets are forwarded. Table 11-3 Filtering Mode Register R/W BIT(S) 7 SYMBOL BCSF DESCRIPTION Broadcast Address Packet Filter 1:Enable broadcast address packet filter; broadcast packets will not be forwarded. 0:Not enable broadcast address packet filter. BCSF is cleared to '0' after power-up reset. Multicast Address Packet Filter 1:Enable multicast address packet filter; multicast packets will not be forwarded. 0:Not enable Multicast address packet filter. MCSF is cleared to '0' after power-up reset. Self Address Packet Filter 1:Enable self-address packet filter; self-addressed packets will not be forwarded. 0:Not enable self-address packet filter. SAF is cleared to '0' after power-up reset. Hash Filter 1:Enable hash filter packet filter; selected packets will not be forwarded. 0:Not enable hash filter packet filter. HF is cleared to '0' after power-up reset. Inverse Broadcast Address Packet Filter 1:Enable inverse broadcast address packet filter; only broadcast packets and packets which pass hash-filter (if HF='1') will not be forwarded. 0:Not enable inverse broadcast address packet filter. IBCSF is cleared to '0' after power-up reset. R/W R/W
6
MCSF
R/W
5
SAF
R/W
4
HF
R/W
3
IBCSF
R/W
25
INDEX
MX98742
2 IMCSF Inverse Multicast Address Packet Filter 1:Enable inverse multicast address packet filter; only multicast packets and packets which pass hash-filter (if HF='1') will not be forwarded. 0:Not enable inverse multicast address packet filter. IMCSF is cleared to '0' after power-up reset. R/W
1-0
Reserved
11.4
FORWARD MODE REGISTER
OVRD Bit:7 Bit:6 Bit:5 Bit:4 Bit:3 Bit:2 FMS1 Bit:1 FMS0 Bit:0
Table 11-4 Forward Mode Register R/W BIT(S) 7 SYMBOL OVRD DESCRIPTION Over-ride 1:Over-ride the forwarding mode selected by FWDMODE(1:0). 0:Not over-ride the forwarding mode. OVRD is cleared to '0' after power-up reset. R/W R/W
6-2 1-0
Reserved FMS1-0 Forward Mode Selection FMS1 FMS0 Forward Mode Slection 0 0 Full-Packet-Store-and-Forward 0 1 64-Byte-Store-and-Forward 1 0 Half-Duplex-and-Forward 1 1 Full-Duplex-and-Forward R/W
11.5
JAM COUNTER REGISTER (R/W)
MSB Bit:7 Bit:6 Bit:5 Bit:4 Bit:3 Bit:2 Bit:1 LSB Bit:0
There are two 16-bit counters inside FEBC counting the number of JAM events on each port. The value of these counters are displayed through 4 8-bit JAM Counter Register. After reset, all the counter values are cleared to 0.
26
INDEX
MX98742
11.6 BUFFER STATUS REGISTER (R/W)
MSB Bit:7 Bit:6 Bit:5 Bit:4 Bit:3 Bit:2 Bit:1 LSB Bit:0
These 8 bits display the starting address of the last packet buffer in Buffer A. For example: A:B 1:1 1:1 1:1 7:1 7:1 7:1 MEMORY SIZE 16K bytes 64K bytes 256K bytes 16K bytes 64K bytes 256K bytes STAT[7:0] 0000, 0011 (3) 0000, 1111 (15) 0011, 1111 (63) 0000, 0110 (6) 0001, 1011 (27) 0110, 1111 (111) LAST A BUFFER ADDR RANGE 6K-8K 30K-32K 126K-128K 12K-14K 54K-56K 222K-224K
11.7
HASH FILTER REGISTER
MSB Bit:7 Bit:6 Bit:5 Bit:4 Bit:3 Bit:2 Bit:1 LSB Bit:0
The 512-bit hash table are implemented by 64 8-byte hash filter register. CRC [23:31] are indexed to these register. CRC [23:31] 0_0000_0000 0_0000_0001 0_0000_0010 0_0000_1000 0_0000_1001 0_0000_1010 1_1111_1101 1_1111_1110 1_1111_1111 HASH REGISTER BYTE 0 0 0 1 1 1 63 63 63 HASH REGISTER BIT 0 1 2 0 1 2 5 6 7
After reset, all the hash-filtering bits are zeros and all packets are forwarded. The addresses to be blocked are transformed by the CRC hash algorithm. The hash-filtering bits that correspond to the Destination Addresses to be rejected are then set to ones.
27
INDEX
MX98742
12.0 ABSOLUTE MAXIMUM RATINGS
Table 12-1 Absolute Maximum Rating RATING Supply Voltage (VCC) DC Input Voltage (Vin) DC Output Voltage (Vout) Storage Temperature Range (TSTG) Power Dissipation (PD) ESD Rating (Rzap = 1.5 K, Czap = 100 pF) Ambient Operating Temp VAULE 4.75 V to 5.25 V -0.5 V to VCC + 0.5 V -0.5 V to VCC + 0.5 V -55 C to 150 C 375 mW 2000 V 0 C to 70 C
Note: 1. Stress greater than those listed under Absolute Maximum Ratings may cause pemanent damage to the device. This is stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Preliminary, subject to change.
13.0 DC CHARACTERISTICS
Table13-1 Supply Current SYMBOL PARAMETER ICC IDD Average Active (TXing/ RXing) Supply Current Static IDD Current CONDITIONS CLOCK=25MHz CLOCK=Undriven MIN --MAX 75 1 UNIT mA mA
Table13-2 DC Characteristics of Inputs, Output, Tri-states SYMBOL PARAMETER Vil Vih Maximum Low Level Input Voltage Minumum High Level Input Voltage (except SD15-0, CDAT7-0) Input Current Maximum Low Level Input Voltage for RESET_ Minumum High Level Input Voltage for RESET_ VI=VCC/GND Schmitt Schmitt CONDITIONS MIN -2.2 MAX 0.8 -UNIT V V
lin Vil Vih
-1.0 -2.7
1.0 0.6 --
uA V V
28
INDEX
MX98742
SYMBOL PARAMETER Voh Minimum High Level Output Voltage for PKT7-0_A, PKT7-0_B, ABYTE1-0_A, ABYTE1-0_B Maximum Low Level Output Voltage for PKT7-0_A, PKT7-0_B, ABYTE1-0_A, ABYTE1-0_B Minimum High Level Output Voltage for TDAT4-0, TDAT4-0_B, TXEN_A, TXEN_B, TX1PR1-0, TX3PR1-0, TX4PR1-0; OE_A, BPDIS, CS_, REGR_W, SA16-0, SD15-0, R_W, G_ Maximum Low Level Output Voltage for TDAT4-0, TDAT4-0_B, TXEN_A, TXEN_B, TX1PR1-0, TX3PR1-0, TX4PR1-0; OE_A, BPDIS, CS_, REGR_W, SA16-0, SD15-0, R_W, G_ Minimum High Level Output Voltage for RDY_ Maximum Low Level Output Voltage for RDY_ Minimum High Level Output Voltage for CDAT7-0 Maximum Low Level Output Voltage for CDAT7-0 Minimum High Level Output Voltage for JAMLED_A JAMLED_B CONDITIONS lol=-2mA MIN 2.4 MAX -UNIT V
Vol
lol=-2mA
--
0.4
V
Voh
lol=4mA
2.4
--
V
Vol
lol=4mA
0.4
V
Voh Vol Voh Vol Voh
loh=-8mA lol=8mA loh=-12mA lol=12mA loh=-16mA
2.4 -2.4 -2.4
-0.4 -0.4 --
V V V V V
Vol
Maximum High Level Output Voltage for JAMLED_A loh=16mA JAMLED_B Maximum Tri-State Output Leakage Current VOUT=VCC/GND -10.0
0.4
V
loz
10.0
uA
29
INDEX
MX98742
14.0 AC CHARACTERISTICS AND WAVEFOEMS
AC Test Conditions Input Pulse Level : VIH/VIL=2.4V/0.4V Input Rise and Fall Time : tr/tf=2ns/2ns Timing Reference Level : 1.5V
T11
RESET_
SYMBOL T11
DESCRIPTION Assertion time for RESET_
MIN. 2400
MAX.
UNIT ns
CS_
T11
T12
REFSEL[7:0]
T21
REGR_W
T31 T32
RDY_
T41
T42
CDAT[7:0]
Figure 14-1.Register Read
TA=0C-70C, VCC=4.75V-5.25V SYMBOL T11 T12 T21 T31 T32 T41 T42 DESCRIPTION CS_low to REGSEL[7:0] valid REGSEL[7:0] hold from CS_high CS_low to REGR_W high CS_low to RDY_low CS_high to RDY_high impedance CS_low to CDAT[7:0] valid CDAT[7:0] hold from CS_high
30
MIN.
MAX. 40
UNIT ns ns
0 35 120 40 160 80 150 0
ns ns ns ns
INDEX
MX98742
CS_
T11
T12
REFSEL[7:0]
T21
REGR_W
T31 T32 T33
RDY_
T43 T41 T42
CDAT[7:0]
Figure 14-2.Register Write
TA=0C-70C, VCC=4.75V-5.25V SYMBOL T11 T12 T21 T31 T32 T33 T41 T42 T43 DESCRIPTION CS_low to REGSEL[7:0] valid REGSEL[7:0] hold from CS_high CS_low to REGR_W high CS_low to RDY_low RDY_low to CSzx_high CS_high to RDY_high impedance CS_low to CDAT[7:0] valid CDAT[7:0] valid to CS_high CDAT[7:0] hold from CS_high 15 5 ns 80 10 40 80 75 5 35 120 MIN. MAX. 40 UNIT ns ns ns ns ns ns ns
31
INDEX
MX98742
T11
SA[16:0]
T22 T21 T31 T32 T23
R_W
SD[15:0]
Figure 14-3 Memory Write
TA=0C-70C, VCC=4.75V-5.25V SYMBOL T11 T21 T22 T23 T31 T32 DESCRIPTION Write cycle time Address setup time Write pulse width R_W high to address change Data setup time Data hold time MIN. 78 13 39 20 33 1 MAX. 82 19 41 25 38 7 UNIT ns ns ns ns ns ns
32
INDEX
MX98742
T11
SA[16:0]
T21 T22 T23
GB
T32 T31
SD[15:0]
Figure 14-4 Memory Read TA=0C-70C, VCC=4.75V-5.25V SYMBOL T11 T21 T22 T23 T31 T32 DESCRIPTION Read cycle time Address setup time Pulse width of GB Read recoverty time Output enable to SD[15:0] valid Output disable to SD[15:0] high impedance MIN. 78 13 39 21 0 0 MAX. 82 19 41 26 25 20 UNIT ns ns ns ns ns ns
33
INDEX
MX98742
RXCLK T11 PKTD[7:0] SFD T21 ABYTE[1:0] 00 10 DA T21 11 01 Detection Range T31 ABT T32 Valid 00 T11 SA DATA IDLE
Figure 14-5 CAM Interface Timing For 100BASE, RXCLK=25MHz or 2.5 MHz
TA=0C-70C, VCC=4.75V-5.25V SYMBOL T11 T21 T31 DESCRIPTION RXCLK rising edge to PKTD[7:0] valid RXCLK rising edge to ABYE[1:0] valid RXCLK rising edge to ABT high 230 (Note 2) 2300 (Note 3) 80 (Note 2) 800 (Note 3) MIN. MAX. 12 12 UNIT ns ns ns
T32
ABT pulse width
ns
Note 1: Any ABT pulse sampled by RXCLK's rising edge during detection range will purge current receiving packet. Note 2: For RXCLK=25MHz Note 3: For RXCLK =2.5 MHz
34
INDEX
MX98742
T1 T2-7 T8 T1
....
T8 T1 T2-7 T8 T1 T2-7 T8 T1
....
T8 T1 T2-7 T8 T1 T2 T3
.... Tn-1 Tn T1
T2 T3
RXCLK
T11
T11 SA0 SA1 SA4 DATA
PKTD[7:0]
SFD
DA0
DA1 DA4
DA5
SA5
IDLE
T21
T11
ABYTE[1:0]
00
10
11
01
00
Detection Range T31 T32
ABT
Figure 14-6 CAM Interface Timing For 10BASE, RXCLK=10MHz (10 Base)
TA=0C-70C, VCC=4.75V-5.25V SYMBOL T11 T21 T31 T32 DESCRIPTION RXCLK rising edge to PKTD[7:0] valid RXCLK rising edge to ABYTE[1:0] valid RXCLK rising edge to ABT high ABT pulse width 2300 800 MIN. MAX. 12 12 UNIT ns ns ns ns
Note 1: Any ABT pulse sampled by RXCLK's rising edge during detection range will purge current receiving packet.
35
INDEX
MX98742
T11 T12 TXCLK T21 SYM/MII TDAT[4:0]/TXD[3:0] TXEN
Figure 14-7 Transmit Signals Timing
TA=0C-70C, VCC=4.75V-5.25V SYMBOL T11* T12* T21* DESCRIPTION TXCLK high for 25MHz (100BASE-TX) TXCLK low for 25MHz (100BASE-TX) TXD, TXEN to TXCLK rising edge MIN. 14 14 10 MAX. 26 26 23 UNIT ns ns ns
T11 T12 RXCLK T22 SYM/MII RDAT[4:0]/RXD[3:0] RXDV RXER T21
Figure 14-8 Receive Signals Timing TA=0C-70C, VCC=4.75V-5.25V SYMBOL T11 T12 T21 T22 DESCRIPTION RXCLK high for 25MHz (100BASE-TX) RXCLK low for 25MHz (100BASE-TX) RXD, RXDV & PXER setup time to RXCLK's rising edge RXD, RXDV & RXER holg time to RXCLK'S rising edge MIN. 14 14 10 5 MAX. 26 26 UNIT ns ns ns ns
*Note 1: The suty cycle of TXCLK should be between 35% and 65% inclusively. 2: The transmit timing T21 measured with 30 pf loading.
36
INDEX
MX98742
T11 TXC T21 TXE T31 TXD 1 0 T22
T12
T23
T32 1 0
T33
T41 COL
T42
Figure 14-9 Serial Transmission With A Collision Detect Heartbeat
TA=0C-70C, VCC=4.75V-5.25V SYMBOL T11 T12 T21 T22 T23 T31 T32 T33 T41 T42 DESCRIPTION Transmit clock low time Transmit clock high time Transmit clock high to transmit enable high Transmit clock cycle time Transmit lock to TXE low Transmit clock high to serial data valid Serial data hold time from transmit clock high Transmit clock to data low TXE low to the start of the collision detect heartbeat Collision detect width 0 2*T22 6 55 64*T22 90 MIN. 36 36 45 110 55 65 ns ns ns ns ns MAX. UNIT ns ns ns ns
37
INDEX
MX98742
T11 T12 RXC T21 T22 T23 T24 T34 sync
CRS
T31 1
T32 T33 0 1
RXD
Figure 14-10 Serial Receive Timing TA=0C-70C, VCC=4.75V-5.25V SYMBOL T11 T12 T21 T22 T23 T24 T31 T32 T33 T34 DESCRIPTION Receive clock low time Receive clock high time Receive clock cycle time Receive clock to carrier sense low Minimum number of receive clocks after CRS low Receive recovery time Receive data setup time to receive clock high First preamble bit to synchronize Receive data hold time from receive clock high Maximum of allowed dribble bits/ clocks 20 8*T21 15 5*T21 MIN. 36 36 90 0 3*T21 40*T21 ns ns ns ns 110 1*T21 MAX. UNIT ns ns ns ns ns
38
INDEX
MX98742
T11 TXCLK T21 TX1PR SOSA T21 TX3PR
T12
SOSA
SOSB
SOSA T21
SOSA
TX4PR
SOSA
SOSB
Figure 14-11 T4 Transmit Timing TA=0C-70C, VCC=4.75V-5.25V SYMBOL T11 T12 T21 DESCRIPTION TXCLK high for 25MHz TXCLK low for 25MHz TX pairs valid to TXCLK's risig edge MIN. 14 14 -MAX. 26 26 25 UNIT ns ns ns
39
INDEX
MX98742
T11 RXCLK T21 RX1PR SOSA T21 RX3PR
T12
SOSA
SOSB
SOSA T21
SOSA
RX4PR
SOSA
SOSB
Figure 14-12 T4 Receive Timing TA=0C-70C, VCC=4.75V-5.25V SYMBOL T11 T12 T21 DESCRIPTION RXCLK high for 25MHz RXCLK low for 25MHz RX pairs should be valid after RXCLK's falling edge MIN. 14 14 -MAX. 26 26 15 UNIT ns ns ns
Note:The duty cycle of the RXCLK and TXCLK should be between 35% to 65% inclusively.
40
INDEX
MX98742
14.0 PACKAGE INFORMATION
160-Pin Plastic Quad Flat Pack
A
ITEM A B C D E F G H I J K L M N O P
MILLIMETERS 31.20 .30 28.00 .10 28.00 .10 31.20 .30 25.35 1.33 [REF] 1.33 [REF] .30 [Typ.] .65 [Typ.] 1.60 [REF.] .80 .20 .15 [Typ.] .10 max. 3.35 max. .10 min. 3.68 max.
INCHES 1.228 .012 1.102 .004 1.102 .004 1.228 .012 .999 .052 [REF] .052 [REF] .012 [Typ.] .026 [Typ.] .063 [REF.] .031 .008 .006 [Typ.] .004 max. .132 max. .004 min. .132 max.
F 160 1 120 121
B
81 80
E
C
D
NOTE: Each lead centerline is located within .25mm[.01 inch] of its true position [TP] at a maximum material condition.
41 40
G
H
I J
N L M K
P
O
41
INDEX
MX98742
MACRONIX INTERNATIONAL CO., LTD
HEADQUARTERS :
TEL : +886-3-578-8888 FAX : +886-3-578-8887
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http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
42

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