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| PNX8510/11 Analog Companion Chip Rev. 02 -- 8 October 2001 Product data 1. Introduction The PNX8510/11 is intended to serve as an analog back end "companion" for digital ICs dealing with video and audio signal processing. The primary difference between the PNX8510 and the PNX8511 is as follows: * * PNX8510 includes the Macrovisiona pay-per-view copy protection system. PNX8511 does not include the Macrovisiona pay-per-view copy protection system. The PNX8510/11 provides two video encoders through two standardized D1 interfaces. The encoders can be bypassed to get direct access to the video DACs for higher resolution displays, such as some of the ATSC formats. The PNX8510/11 also contains a sophisticated sync raster engine which can be utilized to generate various synchronization patterns for interlaced and non-interlaced image formats. The sync raster engine together with an up-sampling filter and a sync insertion unit compose a complete HDTV-capable data path including tri-level sync generation. The PNX8510/11 also provides two independent pairs of stereo audio DACs with two corresponding I2S interfaces. Figure 1 shows the PNX8510/11 with a typical source decoder IC. DV1_OUT DV2_OUT Source Decoder IC Chip A1 out A2 out I2C HSYNC VSYNC Blank 10 10 I2S I2S I2C PNX8510/11 2 2 5 1 1 3 1 RGB or Y/C CVBS Y C (CVBS) A1 R/L A2 R/L GPIO HSYNC VSYNC Figure 1: System Level Diagram 1.1 Features The features of the PNX8510/11 are as follows: PNX8510 * * Six 10-bit video DACs running at up to 135 MHz 1LSB DNL Four audio DACs arranged as two stereo pairs PNX8510/11 Analog Companion Chip Philips Semiconductors * * * * * * * * * * * * * * * * Two built-in digital video encoders PAL B/G, NTSC-M, SECAM encoding Two 10-bit D1 inputs with embedded VBI data Two I2S independent audio input ports I2C programmable (slave interface) Support for high resolution video out up to 81 MHz interface clock rate Support for various input modes (2xD1, RGB, 1x 2D1 muxed, 24/30-bit RGB, DD1...) Programmable generation of embedded analog and external digital sync signals compliant to VESA and SMPTE 274 standards VBI encoding for standard definition video out Teletext insertion for PAL-WST, NTSC-WST, NABTS VPS video programming service encoding Closed caption encoding CGMS copy generation management system according to CPR-1204 Internal color bar generator for standard definition video out JTAG-controlled test signals on video and audio converters Macrovisiona pay-per-view copy protection system, rev. 7.1 (SCART support with Macrovision copy protection on the RGB lines) PNX8511 Features are identical to the PNX8510 except that Macrovisiona is not available. 2. Video Pipeline 2.1 Overview The video pipeline contains two independent video channels. The primary channel is used to display graphic or video content on a standard television, CRT monitor or an HDTV system. The secondary video channel may connect to a VCR or a second standard TV for recording or secondary display purposes. No high definition or RGB output is available through the second video channel. R/C-DAC CCIR656DeMux VBI-extract De-Interleave Primary DENC RGB Bypass G/Y-DAC B-DAC CVBS-DAC Secondary DENC Y/CVBS-DAC C-DAC VOUT2 VOUT3 VOUT4 VOUT1 VOUT5 VOUT6 Figure 2: Video Path Block Diagram (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 2 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip The two video pipelines are driven by two standard D1 interfaces, which can operate in various modes in 8 or 10-bit precision. The following tables summarize the different modes of operation for the video interface of the PNX8510/11. The video interfaces and the sync raster engines are designed in a generic way. The only limiting factor is the data rate of the received video streams. All formats with a total interface speed requirement below 81 MHz can be displayed by the PNX8510/11. Table 1: Primary Video Channel Standard Interface Modes Interface Modes 4:4:4 RGB or YUV or YCrCb or YPrPb 4:2:2 YUV or YCrCb or YPrPb Mode 4:4:4 Muxed Components 10/8-bit 4:2:2 Muxed components 10/8-bit Interface Speed up to 81 MHz up to 81 MHz Table 2: Primary Video Channel Standard Display Modes Display Modes Mode Interface Speed 27 MHz Used Data Path SD-CVBSdata path PAL/NTSC/SECAM 4:2:2 YUV 4:2:2 Muxed components i.e. PAL: 10/8-bit 864 pixel/line x 312.5 lines/field x 50Hz = 13.5 MHz/Y samples 7.5 MHz/U samples 7.5 MHz/V samples PAL/NTSC/SECAM RGB/YUV 4:2:2 Muxed components i.e. PAL: 10/8-bit 864 pixel/line x 312.5 lines/field x 50Hz = 13.5 MHz/Y samples 7.5 MHz/U samples 7.5 MHz/V samples 2FH PAL/NTSC/SECAM 4:4:4 RGB/YUV/YCrCb/YPrPb i.e. PAL: 864 pixel/line x 312.5 lines/field x 50 Hz x2 = 27 MHz/component 480P PAL/NTSC/SECAM 4:4:4 RGB/YUV/YCrCb/YPrPb i.e. PAL: 864 pixel/line x 625 lines/field x 50 Hz = 27 MHz/component generic D1 mode; the interface clock can run up to 81MHz, the components can have either 4:2:2 or 4:4:4 color resolution, but must be in the correct color space. 4:4:4 Muxed Components 10/8-bit 27 MHz SD-CVB and RGB/ YUV data paths HD-data path 81 MHz 4:4:4 Muxed Components 10/8-bit 4:4:4 Muxed components/ 4:2:2 Muxed components (use of both D1 interfaces required) 10/8-bit 81 MHz HD-data path HD-data path up to 81 MHz Table 3: Secondary Video Channel Standard Interface Modes Interface Modes 4:2:2 YUV or YCrCb or YPrPb Mode 4:2:2 Muxed components 10/8-bit Interface Speed 27 MHz Table 4: Secondary Video Channel Standard Display Modes Display Modes PAL/NTSC/SECAM 4:2:2 YUV i.e. PAL: 864 pixel/line x 312.5 lines/field x 50Hz = 13.5MHz/Y samples 7.5 MHz/U samples 7.5 MHz/V samples Mode 4:2:2 Muxed components 10/8-bit Interface Speed 27 MHz Used Data Path SD-CVBSdata path 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 3 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors Table 5: Special Interface/Display Modes Display/Interface Modes 24-bit RGB/YUV Both D1 interfaces and the secondary audio channel are combined to provide high-speed direct access to video DACs . Pin Assignment 24-Bit Mode red[7] - I2S_IN2_SCK red[6] - I2S_AOS2_CLK red[7] - I2S_IN2_SD red[5] - DV_IN1[9] red[6] - I2S_IN2_WS red[4] - DV_IN1[8] red[3] - DV_IN1[7] red[5] - I2S_IN2_SCK red[2] - DV_IN1[6] red[4] - I2S_AOS2_CLK red[1] - GPIO[5] red[3] - DV_IN1[9] red[0] - GPIO[4] red[2] - DV_IN1[8] red[1] - DV_IN1[7] green[9] - DV_IN1[5] red[0] - DV_IN1[6] green[8] - DV_IN1[4] green[7] - DV_IN1[3] green[7] - DV_IN1[5] green[6] - DV_IN1[2] green[6] - DV_IN1[4] green[5] - DV_IN1[1] green[5] - DV_IN1[3] green[4] - DV_IN1[0] green[4] - DV_IN1[2] green[3] - DV_IN2[9] green[3] - DV_IN1[1] green[2] - DV_IN2[8] green[2] - DV_IN1[0] green[1] - GPIO[3] green[1] - DV_IN2[9] green[0] - GPIO[2] green[0] - DV_IN2[8] blue[7] - DV_IN2[7] blue[6] - DV_IN2[6] blue[5] - DV_IN2[5] blue[4] - DV_IN2[4] blue[3] - DV_IN2[3] blue[2] - DV_IN2[2] blue[1] - DV_IN2[1] blue[0] - DV_IN2[0 Pin Assignment 30-Bit Mode red[9] - I2S_IN2_SD red[8] - I2S_IN2_WS Note: In case of the 24/30-bit full parallel input, no secondary audio channel is available. Mode 24-bit direct RGB/YUV 8/10-bit Interface Speed up to 81 MHz blue[9] - DV_IN2[7] blue[8] - DV_IN2[6] blue[7] - DV_IN2[5] blue[6] - DV_IN2[4] blue[5] - DV_IN2[3] blue[4] - DV_IN2[2] blue[3] - DV_IN2[1] blue[2] - DV_IN2[0] blue[1] - GPIO[1] blue[0] - DV_CLK2 Single interface mode 2 (D1) Accommodates 2 synchronous multiplexed D1 streams for low cost applications (both streams are extracted) Interleaved interface mode Same formats as in single interface mode 1 and 2 but only one of the two interleaved video streams is extracted per interface. Selection of the extracted slice is possible by software, Usage of two PNX8510/11 chips possible to support up to 4 display/record devices 2x muxed 4:2:2 single D1 8/10-bit 2x muxed 4:2:2 single D1 or 2x muxed 4:4:4 RGB/YUV 8/10-bit 2 combined D1 8/10-bit 54 MHz 54 MHz or 81 MHz or pos-neg edge 27 MHz (SAA7128 compliant) Combined double D1 mode: the two D1 interfaces are combined to carry a single HDTV stream in 4:2:2 YUV or 4:2:2 YPrPb format primary D1: Y channel secondary D1: muxed UV or PrPb channel i.e.: 1920x1080 60 Hz interlaced 2200 pixel/line x 562.5 lines/field x 60 Hz = 74.25 MHz/Y samples 37.125 MHz/Cr/Pr samples 37.125 MHz/Cb/Pb samples Note: In case of the combined double D1 mode, no secondary display channel is available. (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. up to 75 MHz per D1 9397 750 08865 4 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip The PNX8510/11 supports color space conversion only in the primary RGB standard definition data path. For the high definition part of the primary video data path and for the secondary video data path no color space conversion is available. Hence the video data has to be provided in the display destination color space. Aside from built-in video encoders, which generate all necessary timing and filtering for an appropriate sync raster for PAL, NTSC and SECAM, the PNX8510/11 contains a separate raster-generation engine which also supports but is not limited to the HD-formats, such as the SMPTE 274M. Furthermore the PNX8510/11 contains an up-sampling filter to convert 4:2:2 formats (other than standard definition formats) to 4:4:4. Note: In the case of combined double D1 mode, no secondary display channel is available. If the interface is operated in D1 mode, the data stream presented to the interface has to be D1 compliant i.e., the maximum and minimum codes (8-bit 0x00 0xFF, 10-bit 0x000 0x3FF) must not occur during active video. A detailed description of video input data formats can be found in Section 2.2 Video Input Modes. The video modes mentioned in Section 2.2 correspond to the settings of the DEMUX_MODE bits in the register 0x95 VMUXCTL. If the video interface clock frequency is not equivalent to the processing and the video DAC operation frequency the appropriate divider registers in the audio/clock register section have to be programmed. As a general rule the following settings should be used: 422 YUV SD Single Interface Mode 27MHz interface clock 27MHz processing clock 27MHz DAC clock 444RGB 2FH Single Interface Mode 81MHz interface clock 27MHz processing clock 27MHz DAC clock 422 YUV 1080i Double Interface Mode 74.25MHz interface clock 74.25MHz processing clock 74.25MHz DAC clock 2.2 Video Input Modes The PNX8510/11 video interface supports a wide variety of video formats. The video interface is designed in a generic fashion. It is de-coupled from the actual video data paths in the system and imposes only a few restrictions on the video data streams provided to the chip. This section explains the possible video stream formats and provides details on synchronizing the PNX8510/11 with respect to a particular video data format. The PNX8510/11 accepts the following video formats on a single interface with up to 81 MHz interface clock: 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 5 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors 2.2.1 YUV 4:2:2 FF 00 00 EAV 80 10 80 10 .. . FF 00 00 SAV U1 Y1 V1 Y2 U3 Y3 .. . Figure 3: YUV 4:2:2 This is the CCIR-656 compliant format and will mainly be used at an interface speed of 27 MHz to feed the video encoder modules in the chip. This is the standard interface format for the secondary video encoder pipeline unless the chip is used in High Definition (HD) mode. The YUV 4:2:2 format can also be used to feed the HD data path as long as the pixel clock rate stays below 81 MHz. To operate the HD data path with 4:2:2 source material the 4:2:2 to 4:4:4 filter should be enabled to achieve the best video quality. 2.2.2 RGB 4:4:4 FF 00 00 EAV 80 10 80 10 .. . FF 00 00 SAV R1 G1 B1 R2 G2 B2 .. . Figure 4: RGB 4:4:4 This mode is only useful if the HD data path in the PNX8510/11 is in operation. The RGB 4:4:4 interface mode is not applicable to the standard definition RGB path operation due to the implicit clocking requirements. The data rate for standard definition RGB 4:4:4 data would be 13.5 MHz per component resulting in an interface speed of 40.5 MHz. Because the chip does not contain any PLLs, it is not possible to extract 27 MHz out of the interface clock. 2.2.3 YUV 4:4:4 FF 00 00 EAV 80 10 80 10 .. . FF 00 00 SAV Y1 U1 V1 Y2 U2 V2 .. . Figure 5: YUV 4:4:4 This mode is useful only if the HD data path in the PNX8510/11 is in operation. 2.2.4 YUV 4:2:2 Interleaved FF FF 00 00 00 00 EAV EAV 80 80 10 10 .. . FF FF 00 00 00 00 SAV SAV U1 a U1 b Y1 a Y1 b V1 a V1 b Y2 a Y2 b Figure 6: YUV 4:2:2 Interleaved This mode supports two video data streams through one physical video interface. It can be used to utilize both video encoder channels in the chip with one interface only or to hook up two PNX8510/11 devices to one source providing an interleaved data stream. Each chip extracts one slice from the interleaved stream. This video format is useful for the encoder standard definition data path only. (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 6 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip 2.2.5 RGB 4:4:4 Interleaved FF FF 00 00 00 00 EAV EAV 80 80 10 10 .. . FF FF 00 00 00 00 SAV SAV R1 a R1 G1 G1 B1 b a b a B1 R2 R2 b a b Figure 7: RGB 4:4:4 Interleaved This mode supports two video data streams through one physical video interface. It can be used to utilize both video encoder channels in the chip with one interface only or to hook up two PNX8510/11 devices to one source providing an interleaved data stream. Each chip extracts one slice from the interleaved stream. This video format is useful for the standard definition RGB data path as well as for the HD data path. 2.2.6 YUV 4:4:4 Interleaved FF FF 00 00 00 00 EAV EAV 80 80 10 10 .. . FF FF 00 00 00 00 SAV SAV Y1 a Y1 b U1 U1 V1 a b a V1 b Y2 a Y2 b Figure 8: YUV 4:4:4 Interleaved This mode supports two video data streams through one physical video interface. It can be used to utilize both video encoder channels with one interface only or to hook up two PNX8510/11 devices to one source providing an interleaved data stream. Each chip extracts one slice from the interleaved stream. This video format is useful for the HD data path only. There are two modes defined for interleaved data streams. One is to run the interface at twice the speed and provide a qualifier on the HSYNC input to qualify a certain slice. The qualifier is essentially the interface clock divided by two. The other interleaved interface format works on both clock edges of the interface clock, so one slice is latched at the positive edge and the other slice is latched at the negative edge of the interface clock. 2.2.7 YUV 4:2:2 HD Two Channel Format FF 00 00 EAV 80 10 80 10 .. . FF 00 00 EAV 80 10 80 10 .. . FF 00 00 SAV U1 V2 U3 V3 U5 V5 FF 00 00 SAV Y1 Y2 Y3 Y4 U5 Y6 .. . .. . Figure 9: YUV 4:2:2 HD Two Channel Format This format is used only for high definition video modes that exceed interface clock requirements of 81 MHz. For this video interface mode, both physical interfaces of the chip are utilized. The primary interface gets a D1-like data stream, which only contains the luminance information, while the secondary D1 interface carries the chrominance information. 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 7 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors 2.3 Video Input Module The video input module is responsible for accommodating all supported video data formats. It delivers a de-multiplexed and de-sliced data stream to the video processing modules. As depicted in Figure 10, the IC has two video input ports which can accommodate 8 or 10-bit wide video data streams. The normal mode of operation is that the DV1 interface is routed to the primary video data paths and the DV2 interface is routed to the secondary video data paths. The IC however accepts also so called sliced data formats. A sliced data format contains two single video data streams multiplexed together on a component basis. A more detailed description of the arrangement of the components can be found in Section 2.2 Video Input Modes. To enable sliced data formats the SLICE_MODE bit has to be set. The De-Slice module essentially takes the two data streams apart by simply two to one demultiplexing. The routing of the resulting two video data streams is determined by setting the SEL register bits in the primary and secondary video data path apertures appropriately. Sliced data formats come in two different flavors: double edge and qualified. The double edge slice format has data changes on the positive and the negative clock edge where as the qualified mode qualifies one data stream of the two multiplexed ones with an active high on the HSYNC signal. To use this mode the USE_QUALIFIER bit must be set. The order of the slice qualification can be changed by setting the INV_QUALIFIER bit. Since each of the video input interfaces can accept sliced data formats a total of four video data streams could be routed into the IC and two of them can be selected to be forwarded to the primary and the secondary video display pipeline. Note: If the two video pipelines are sourced by only one video input interface operating in sliced mode, both video pipelines must receive the same input clock originating from the sliced data source. (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 8 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip The structure of the video input module is shown in the block diagram below. RST SYNC Primary RST SYNC Secondary Register Array Primary Register Array Secondary VBI Data Slicer TTX Data Port DEMUX_MODE 8/10-bit Mode R/Y/Y D1-IN Primary SAV-EAV Detection DE-SLICE OUT-SEL B/V Output Formatter G/U/U-V SLICE_MODE O_E 8/10-bit Mode SLICE_DIR SEL1 DEMUX_MODE Y D1-IN Secondary SAV-EAV Detection Output Formatter U-V DE-SLICE OUT-SEL O_E SLICE_MODE SLICE_DIR SEL2 VBI Data Slicer TTX Data Port Figure 10: Block Diagram of the Video Input Module 2.4 Video DAC Control The PNX8510/11 contains 6 video DACs. Four of them are dedicated to the primary video pipeline and the remaining 2 are assigned to the secondary video processing path. The first DAC of the primary video channel (VOUT1) is always assigned to the primary standard definition data path. The output of the DAC can be changed from CVBS to Y by resetting the DAC control bit CVBSEN to zero. The second DAC of the primary video channel (VOUT2) is either assigned to the standard definition data path and carries the chrominance (Y/C operation) if the CEN bit in the DAC control register is set or the Red/V channel (RGB/Component mode operation) if the DAC control register bit CEN is reset. In HD mode (SD_HD bit set to zero) this DAC carries either the Red channel or the Y channel depending on whether the HD path is operated in YUV or RGB mode. Note that the CEN bit must be reset for HD operation. 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 9 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors The third DAC of the primary video channel (VOUT3) carries the luminance channel if the VBSEN bit is set in standard definition mode (SD_HD=1'b1). This DAC streams out the Green/Y channel if the VBSEN bit is reset (RGB/Component mode operation). If the high definition data path is operational (SD_HD=1'b0) this DAC carries the Green or U channel depending on whether the HD path is operated in YUV or RGB mode. The configuration of the fourth DAC in the primary video data path (VOUT4) can not be changed with a programming register. This DAC carries the Blue or U channel in standard definition mode and the Blue or V channel if the high definition data path is active. The configuration of the DACs for the secondary video data path is limited to the CVBS/Y DAC (VOUT5). If the CVBSEN bit in the DAC control register is set this DAC carries the CVBS signal. Resetting the bit results in the Y signal being assigned to this DAC. The second DAC of the secondary video pipeline (VDAC6) always carries the chrominance signal. 2.5 VBI Data VBI data extraction from a D1 data stream is only supported for standard definition formats. The extraction follows the concept of Philips video decoders, such as the SAA7114. Both video interfaces can carry VBI data information. The content of the VBI data is entirely determined by the source decoder chip software driver. The PNX8510/11 supports two VBI data streams. The limitation to two VBI data streams implies certain limitations when using multiple PNX8510/11 chips in a system. In this case one PNX8510/11 gets either one or two (all) VBI data streams. The other PNX8510/11 IC would get one or none. Only the ANC/SAV-EAV header style VBI data encoding mode is supported in the PNX8510/11. According to these standards VBI data is always inserted in the horizontal blanking interval of a line. The data is preceded by an ANC header which is programmable. An internal header following the ANC contains a programmable sliced data identifier with the number of data bytes transmitted and two internal identification tokens containing data type, field type and line number. Figure 11 illustrates how the data is encoded in the horizontal blanking interval. Note: In standard definition mode, only 8 of the 10 available signal lines of the D1 interface are used. The two LSB lines are fixed to zero. *See the following tables for code descriptions. FF 00 00 EAV FF FF 00 DID SDID BC IDI1 IDI2 D1 D2 Ddc-1 Ddc FF 00 00 SAV Timing Reference Code End Active Video ANC Header Internal Header Sliced Data Timing Reference Code Start Active Video Horizontal Line Blanking Interval Figure 11: ANC VBI Data Insertion in D1 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 10 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip Table 6: VBI Header/Data Codes Name SAV DID SDID BC IDI1 IDI2 D1-Ddc EAV start of active video data identifier: ignored, has to be set to 0x11h sliced data identification: ignored, has to be set to 0x11h byte count describes the number of succeeding decoded data bytes internal data identification 1: OP, FID, LineNumber[8:3] internal data identification 2: OP, LineNumber[2:0], DataType data bytes end of active video Function Table 7: VBI Data Header Format Code SDID DID BC IDI1 1 1 - D9 1 1 - D8 1 1 D7 1 1 D6 1 1 D5 1 1 D4 1 1 D3 1 1 D2 BC5 LN8 BC4 LN7 BC3 LN6 BC2 LN5 BC1 LN4 BC0 LN3 field ID 0=field 1 1=field 2 LN2 IDI2 - LN1 LN0 DT3 DT2 DT1 DT0 LN = line number; BC = byte count; DT = data type Table 8: SAV/EAV Codes NTSC Line Number 1-3 4-19 20-263 264-265 266-282 283-525 F 1 0 0 0 1 1 V 1 1 0 1 1 0 H (EAV) 1 1 1 1 1 1 H (SAV) 0 0 0 0 0 0 Table 9: SAV/EAV Codes PAL Line Number 1-22 23-310 311-312 313-335 336-623 624-625 F 0 0 0 1 1 1 V 1 0 1 1 0 1 H (EAV) 1 1 1 1 1 1 H (SAV) 0 0 0 0 0 0 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 11 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors Table 10: SAV/EAV-Sequence D9 preamble 1 0 0 status word 1 D8 1 0 0 F D7 1 0 0 V D6 1 0 0 H D5 1 0 0 P3 D4 1 0 0 P2 D3 1 0 0 P1 D2 1 0 0 P0 D1 1 0 0 0 D0 1 0 0 0 P0 to P3 are protection bits and calculated in the following way: P3=V^H; P2=F^H; P1=F^V; P0=F^V^H Table 11: Supported Data Types Data Type 0000 0010 0011 0100 1100 1111 Teletext EuroWST VPS video programming service WSS wide screen signalling closed caption US NABTS Programming (SubAddr1-Data1-SubAddr2-Data2 ...) Standard Figure 12 illustrates the different modes of operation for the primary video channel. Video Encoder Input Interface CVBS/Y-DAC Y-Processing UV-Processing Mixer 10 10 10 D1 10/8 Sync Macrovision* RGB-Mode Delay Comp Sync Extract 24 Blanking Macrovision* Insertion Color Space Matrix R/C-DAC 24 16 8 G/Cr/Y-DAC B/Cb-DAC RGB-Pipe System CLK CLKin CLK-Divider * Macrovision is not available in the PNX8511. Figure 12: Primary Display Pipe (Standard Definition Operation Mode) (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 12 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip The secondary display consists of the Y and UV processing data path of a video encoder only. The synchronization information will be extracted from the incoming D1 data stream. The structure of the secondary display pipe is shown in the figure below. Video Encoder Input Interface 10/8 Sync Macrovision* Y-Processing UV-Processing CVBS/Y-DAC C-DAC D1 Mixer 10 10 * Macrovision is not available in the PNX8511. Figure 13: Secondary Display Pipe (Standard Definition Operation Mode) secondary D1 optional for special mode: combined D1 D1-Interface Sync Extract DeMUX Y/R-DAC Primary D1 D1-Interface Sync Extract Bypass up-sample Bypass Gain control Sync-insert Level-shift Sync-shaper U/Cb/Pb/G-DAC V/Cr/Pr/B-DAC Secondary D1 V/O_E Sync-raster generator CBlank V/O_E H H V Figure 14: Primary Display Pipe (HD Operation Mode) 2.6 PAL/NTSC/SECAM Encoder 2.6.1 General The PAL/NTSC/SECAM encoder accepts the YUV data and encodes it into an NTSC, PAL or SECAM video signal. From Y, U and V data, the encoder generates luminance, chrominance and subcarrier output signals, suitable for use as CVBS or separate Y and C signals. Luminance is modified in gain and in offset (offset is programmable to enable different black level setups). In order to enable easy analog post filtering, luminance is interpolated from a 13.5 MHz data rate to a 27 MHz data rate, providing luminance in 10-bit resolution. This filter is also used to define smoothed transients for synchronization pulses and the blanking period. 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 13 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors Chrominance is modified in gain (programmable separately for U and V). The standard dependent burst is inserted before baseband color signals are interpolated from a 6.75 MHz data rate to a 27 MHz data rate. One of the interpolation stages can be bypassed, thus providing a higher color bandwidth, which can be used for Y and C output. The FSC bits set the subcarrier frequency. To make sure the subcarrier is locked to the line frequency, as the standards require, the sync generator is able to reset the subcarrier generation periodically. This feature is controlled by the PHRES programming bits. These features are available to generate a standard interlaced signal; they will not work in non-interlaced mode. A crystal-stable master clock of 27 MHz, which is twice the CCIR line-locked pixel clock of 13.5 MHz, is received from the interface clock pins. The encoder synthesizes all necessary internal signals, color subcarrier frequency, and synchronization signals from that clock. For ease of analog post filtering, the signals are twice oversampled with respect to the pixel clock before digital-to-analog conversion. Programming flexibility includes NTSC-M, PAL-B, SECAM main standards as well as other variations. A number of possibilities are provided for setting different video parameters, such as: * * * Black and blanking level control Color subcarrier frequency Variable burst amplitude The sync generator generates all the signals required to control the signal processing, provide the composite sync signal, insert the color burst, etc. The encoder includes a cross-color reduction filter to reduce cross talk between the luminance and chrominance channels. In the CVBS signal, the signal amplitude is reduced by 15/16 to avoid overflow. 2.6.2 Luminance and Chrominance Processing The Y processing provides a high performance 5 MHz lowpass filter. It adjusts the level range according to the standard and inserts the sync and blanking pulses. The insertion stage generates the correct pulse shapes. No further processing is necessary of the D/A converters for this purpose. Chroma processing operates on the baseband signals as long as possible. At first, the signal amplitudes are adjusted and the burst is inserted. Afterwards the signals are passed through a 1.4 MHz lowpass filter. This filter can be switched to a higher cut-off frequency to allow more chroma bandwidth with S-Video. The quadrature modulator uses a DTO with 32-bits resolution for the subcarrier generation. Even with this high resolution, the DTO cannot generate the carrier locked to the line frequency as the standards require without further means. So the sync generator is able to reset the DTO periodically. This feature is controlled by the PHRES programming bits. These modes may only be switched on if the encoder is programmed to generate a standard signal; they will not work in non-interlaced mode. 2.6.3 Sync Generator The sync generator is the timing master of the encoder. It generates all the signals required to control the signal processing, provide the composite sync signal, insert the color burst, etc. Via the FISE control bit, the circuit can be set to generate 50 Hz patterns for e.g., PAL B or 60 Hz patterns (NTSC M). It is possible to modify the number of lines per field by 0.5 lines to generate a non-interlaced output signal. The sync generator also provides HS, VS and O_E signals to control the rest of the encoder. (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 14 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip 2.6.4 Macrovision PNX8510 The encoder supports Macrovisiona Anti-Taping for both NTSC and PAL. There is no Macrovision insertion for SECAM defined, however for AGC Pseudo Sync and BP pulses the same settings used for PAL could be used for SECAM. The different steps of this process can be programmed separately. The Macrovision control block provides all necessary timing and level information for inserting the correct pulses in the CVBS/Y/C/RGB/YUV data stream. Furthermore it provides the signals used to modify the subcarrier generator according to the Macrovision Burst Inversion requirements. The encoder uses a blanking level during the vertical blanking interval that is defined by the value of BLNVB, thus providing two different programmable blanking levels. Outside vertical blanking, value of BLNNL is effective, which should be reduced according to Macrovision requirements. The copy protection means can be activated independently by the respective control bits. The copy protection mechanism is optional and will be enabled by bonding a diepad to either VDD or VSS. PNX8511 Macrovision is not available in the PNX8511. 2.7 HD Data Path The high definition data path of the PNX8510/11 IC features an up-sampling filter, gain control and a universal sync insertion engine. Input formats supported by the high definition data path are: Double D1 mode:16/20 bit 422 (8/10 bit for Y and 8/10 bit for U/V); DEMUX_MODE set to 3'b011 Single interface HD 422 mode (UYVY 422 D1 format); DEMUX_MODE set to 3'b100 Single interface 444 (RGB/YUV 444 format); DEMUX_MODE set to 3'b001 Full 24/30 bit parallel input mode (YUV/RGB 444 formats); VMODE set to zero RGB and YUV data types are accepted. However, there is no color space conversion in the HD data path so the input data type has to match the display data type. The up-sampling filter can be applied to convert incoming 422 data formats to 444. The data path also provides individual gain control for RGB/YUV which allows a +/- 0.5x amplitude change (HD_GAIN_R/Y, HD_GAIN_U/G, HD_GAIN_V/B control registers). The HD sync insertion module following the filter and gain control circuits provides flexible insertion of synchronization signals into the Y, Y and V or R, G and B data paths. The insertion can be chosen on a component basis (Y/R_SYNC_INS_EN, U/G_SYNC_INS_EN, V/ B_SYNC_INS_EN control registers) and the sync generator provides individual tables for the components. A more detailed description of the sync generator can be found in the next paragraph. 2.8 HD-Sync Generator Module This section describes the operation and programming of the high definition (HD) video data path sync unit. The module's purpose is to provide the video data path that bypasses the digital video encoders with the appropriate synchronization pattern. The module design provides maximum flexibility in terms of raster generation for all interlaced and non-interlaced ATSC formats. The sync engine is 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 15 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors capable of providing a combination of event-value pairs which can be used to insert certain values at specified times in the outgoing data stream. It can also be used to generate digital signals associated with time events. They can be used as digital H- and V-synchronization signals. The sync raster generation is fully programmable to accommodate different requirements. The raster generation can be either progressive or interlaced. Digital sync signal generation (H, V, Blank) as well as analog embedded sync generation are supported. The picture position is adjustable through the programmable relation between the sync pulses and the video contents. The generation of embedded analog sync pulses is bound to a number of events which can be defined for a line. Several of these line-timing definitions can exist in parallel. For the final sync raster composition a certain sequence of lines with different sync event properties has to be defined. The sequence specifies a series of line types and the number of occurrences of this specific line type. After the sequence has completed, it restarts from the beginning. In this way, the sync raster generation is generic and can be adopted to different standards (different sync shapes, various H-timing, interlaced, progressive...). However, to generate a stable picture, it is important that the sequence fits precisely to the incoming data stream in terms of the total number of pixels per frame. (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 16 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip The sync engine's flexibility is achieved by using a sequence of linked lists carrying the properties for the image, the lines as well as fractions of lines. The list dependencies are illustrated in Figure 15. 4-bit line type index 10-bit line count Line_Count_Array 16 entries Line_Count_Ptr 3 3 3 3 3 Pattern_Ptr Line_Type_Array 15 entries 3 3 3 3 3 10-bit Duration 1-bit Select 3-bit Value Idx 10-bit Duration 1-bit Select 3-bit Value Idx 3 Line_Type_Ptr 3 3 3 3 3 10-bit Value R/Y-Value_Array Event_Type_Ptr 8 entries 10-bit Duration 1-bit Select 10-bit Duration 1-bit Select 3-bit Value Idx 10-bit Value G/U-Value_Array 3-bit Value Idx 8 entries Line_Pattern_Array 7 entries 10-bit Value B/V-Value_Array 8 entries Line_Pattern_Ptr Figure 15: Sync Engine List Dependencies The first table is called "Line_Count_Array" and serves as an array to hold the correct sequence of lines composing the synchronization raster. It can contain up to 16 entries. Each entry holds a 4-bit index (counted from 1 through 16)) and a 10-bit counter value. The 4-bit index is a pointer to a line in the next table called "Line_Type_Array." A 10-bit counter value specifies how often this particular line is repeated. If the necessary line count for a particular line exceeds the 10 bits, it has to use two table entries. This table has to be terminated with a dummy entry containing a `0' index and `0' line count. The second table, "Line_Type_Array" holds up to 15 entries (counted from 1 through 15). Each entry can contain up to eight index pointers. It is possible to have less than eight index pointers in any entry, in which case those index pointers should be filled with `0.' Each index pointer 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 17 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors points to a line with that index in the next table called "Line_Pattern_Array." These pointers represent parts of a line raster. A line may be split up into a sync, a blank and an active portion followed by another blank portion, which would require four index pointers in one entry of the table. The third table is called "Line_Pattern_Array" and it can contain a maximum of seven entries (counted from 1 though 7). The entries are used to define portions of a line representing a certain value for a certain number of clock cycles. Each of these seven entries can store up to four groups of "duration, select and value index." It is possible to have less than four groups in any entry, in which case those groups should be filled with `0.' "Duration" is a 10-bit value representing the number of clock cycles. "Select" indicates whether the value is actually inserted into the video data stream or not. "Value index" is a 3-bit index into another array called "value array." Certain bits of the "value index" can also be used to generate a digital sync raster provided at the H- and V-sync outputs of the PNX8510/11. "Value array" can hold up to 8 values (counted from 0 though 7) which are 10-bit signed. To ease the trigger setup for the sync generation module, a set of registers is provided to set up the screen raster defined as width and height. A trigger position can be specified as an x, y coordinate within the overall dimensions of the screen raster. If the x, y counter matches the specified coordinates, a trigger pulse is generated which pre-loads the tables with their initial values. The listing below outlines an example on how to set up the sync tables for a 1080i HD raster: // hd-sync config file for 1080i #line_count_array //index //line_count -----------------------------------------2 5 //5 lines vsync 4 1 //1 line sync-black-sync-black 6 14 //14 lines blank 1 537 //537 lines active video 6 5 //5 lines blank 5 1 //1 line sync-black-sync-blank 2 4 //4 lines sync 3 1 //1 line sync blank sync black 6 15 //15 lines blank 1 537 //537 lines active video 6 5 //5 lines blank 0 0 //dummy lines 0 0 //dummy lines 0 0 //dummy lines 0 0 //dummy lines 0 0 //dummy lines #line_type_array //p8 p7 p6 p5 p4 p3 p2 p1 ---------------------------------------------------------------------------------0 0 0 0 0 0 3 4 //sync-full active line 0 0 0 0 2 4 2 4 //sync-half blank-sync-half blank 0 0 0 0 1 4 2 4 //sync-half blank-sync-half black 0 0 0 0 1 4 1 4 //sync-half black-sync-half black 0 0 0 0 2 4 1 4 //sync-half black-sync-half blank 0 0 0 0 0 0 5 4 //sync-full line black 0 0 0 0 0 0 0 0 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 18 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 #line_pattern_array //d=dur s=sel v=value //d4 s4 v4 d3 s3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 v3 d2 s2 v2 d1 s1 v1 line black line blank active line pulse line black ----------------------------------------------------0 0 0 0 0 0 43 1 3 879 1 3 //half 0 0 0 0 0 0 43 1 3 879 1 0 //half 43 1 3 959 0 6 959 0 6 59 1 3 //full 0 0 0 87 1 3 43 1 2 43 1 1 //sync 43 1 3 959 1 3 959 1 3 59 1 3 //full 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 #value_array Y //signed values --------------------------------------512 //broad pulse level 0 -512 //lower sync tip 0 102 //upper sync tip 600 -204 //black/blank level org 204 0 0 0 0 #value_array U //signed values -------------------------------------0 //broad pulse level 0 -432 //lower sync tip 0 432 //upper sync tip 600 0 //black/blank level org 0 0 0 0 0 #value_array V //signed values -------------------------------------0 //broad pulse level 0 -432 //lower sync tip 0 432 //upper sync tip 600 0 //black/blank level org 250 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 19 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors 0 0 0 0 A complete example of register settings for 1080i is given in Section 11. Video Programming Examples. The listing below outlines an example on how to set up the sync tables for a 720p raster: // hd-syn config file for 720p #line_count_array //index line_count 2 5 3 20 1 360 1 360 3 5 0 0 0 0 0 0 0 0 0 0 #line_type_array //p8 p7 p6 p5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 //5 lines vsync //20 lines blank //360 lines active video //360 lines active video //5 lines blank //dummy lines //dummy lines //dummy lines //dummy lines p4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p2 3 2 5 0 0 0 0 0 0 0 0 0 0 0 p1 4 //sync-full line active 4 //sync-full line blank (vsync) 4 //sync-full line black (v-blanking) 0 0 0 0 0 0 0 0 0 0 0 #line_pattern_array //dur4 sel4 val4 dur3 0 0 0 0 0 0 0 69 69 1 3 639 0 0 0 69 69 1 3 639 0 0 0 0 0 0 0 0 sel3 0 1 0 1 1 0 0 val3 0 3 0 3 3 0 0 dur2 0 714 639 39 639 0 0 sel2 0 1 0 1 1 0 0 val2 dur1 0 0 0 714 0 149 2 39 3 149 0 0 0 0 sel1 0 1 1 1 1 0 0 val 1 0 //empty 0 //full line blank 3 //full line active 1 //sync pulse 3 //full line black 0 0 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 20 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip #value_array Y //signed values --------------------------------------512 //broad pulse level 0 -512 //lower sync tip 0 102 //upper sync tip 600 -204 //black/blank level org 204 0 0 0 0 #value_array U //signed values -------------------------------------0 //broad pulse level 0 -432 //lower sync tip 0 432 //upper sync tip 600 0 //black/blank level org 0 0 0 0 0 #value_array V //signed values -------------------------------------0 //broad pulse level 0 -432 //lower sync tip 0 432 //upper sync tip 600 0 //black/blank level org 250 0 0 0 0 2.9 Limitations of the Video Pipe In all HD modes, the video encoder will be switched off. Either a separate sync signal or the embedded syncs of the D1 input can be used to generate the sync raster driving the display device. 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 21 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors 3. Audio Pipeline The PNX8510/11 has two independent stereo channels, each connected to a separate audio interface. The primary audio channel is usually associated with the primary video channel and carries the accompanying sound information. The secondary audio channel usually carries the audio belonging to the record (secondary) video channel. Because they might originate from different sources, the two interfaces are operated by independent clocks. Mute on/off is programmable by a register setting. Table 12 describes the expected audio performance. Table 12: Audio Performance Parameter Dynamic Range S/(N+Disto.) QFP100 85dB >85dB The audio path has three general blocks: input, interpolation, and DAC. * * The input is, by default, a 24-bit I2S interface. However, it can be programmed to accept other formats. The interpolator scales, filters and oversamples the incoming data by 64 x its sampling frequency. The result goes to a Noise Shaper, which shifts in-band noise to frequencies well above the audio spectrum. This provides a very high signal-to-noise ratio. Finite Impulse Response DACs convert the 1-bit data stream to analog output voltage. * Primary I2S Interpolator Left/Right Noise Shaper FIR-DAC-L FIR-DAC-R Secondary I2S Interpolator Left/Right Noise Shaper FIR-DAC-L FIR-DAC-R Figure 16: Audio Path Block Diagram 3.1 Audio Interface Operation The audio interfaces can be operated in either slave or master mode: * * In slave mode, all required clocks (System CLK, SCK and WS) must be generated externally and must be synchronous with each other. In master mode, the PNX8510/11 only gets the System CLK and generates SCK and WS clocks synchronously to the applied System CLK. In this mode, System CLK is equal to 128 x Fs where Fs is the audio sampling frequency. (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 22 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip 3.1.1 Audio Input Timing The following timing diagrams illustrate the different modes of operation for the I2S interface used in the PNX8510/11. SCK SD 1) MSB first / MSB justified format (MSB): WS MSB LSB MSB LSB 2) MSB first / LSB justified format (Japanese I2S 16, 18, 20, 24 bit): WS MSB LSB MSB LSB : position fixed. : position may vary with wordsize. Figure 17: Input Formats. Justification bit is not delayed. SCK SD 1) MSB first / MSB justified format (Philips I2S): WS MSB LSB MSB LSB : position fixed. : position may vary with wordsize. Figure 18: Input Format. Justification bit is one bit clock delayed. Table 13: I2S Signals Port SCK SD WS Bit clock PCM data Word Select; left right clock is equal to the sample rate. Description 3.2 Mute Modes The audio modules of the PNX8510/11 have several mute functions. The mute operation is controlled via the programming registers quickmute, and mutemode. Quick Mute: This is an overriding quickmute on the master channel, which mutes the interpolator output signal in 32 samples using the cosine roll-off coefficients. This means whenever the quickmute register is set to one, independent of what the mute setting of the microcontroller is, the output is muted. 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 23 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors Mute Mode: this register sets the mute mode for the MASTER MUTE to either soft mute (setting is `0') or to quick mute (setting = `1'). For the master channel the quickmute function and the microcontroller mute function are OR'd. Table 14: Mute Mode Control Quick Mute 0 0 1 Microcontroller Mute 0 1 X No mute Function 1 microcontroller mute...mute mode depends on the `mutemode' setting. Overriding quick mute function Table 15: Mute Mode Function Mute Mode 0 1 Function Mute function via micro controller interface is set to "soft mute." Mute function via micro controller interface is set to "quick-mute." 4. Programming Interface The configuration of the various interface modes and the digital video encoder setup can be controlled via an I2C interface or a special VBI data packet sent during the horizontal blanking interval. With the VBI programming interface, a reliable real-time programming for the PNX8510/ 11 video blocks can be accomplished. For instance, this mode makes it very easy to carry the necessary programming data over to the digital encoder to encode a certain teletext packet in a specific scanline without extensive buffering. The format for programming registers in the PNX8510/11 via the VBI interface can be found in Section 2.5. Note that reprogramming clocks and audio registers are not possible via the VBI interface. The PNX8510/11 is an I2C slave device only. It uses four dedicated slave addresses to address the primary, secondary, audio and remaining control registers. The I2C address set can be configured during reset with a pullup or pulldown combination of GPIO pins. Figure 19 below illustrates an example of how the I2C device addresses are determined. VIDEO 1 IIC address selection example: GPIO5-2 are set to logic one and GPIO1 is set to zero during Anabel rest. VIDEO 2 AUDIO 1 / VIDEO 1 and AUDIO 1 clocks Address= GPIO5-GPIO4-XY-GPIO3-GPIO2-GPIO1-R/W Address= 1-1-XY-1-1-0-R/W VIDEO1= 1-1-0-0-1-1-0-R/W = 0xCC(write), 0xCD(read) VIDEO2= 1-1-0-1-1-1-0-R/W = 0xDC(write), 0xDD(read) AUDIO1= 1-1-1-0-1-1-0-R/W = 0xEC(write), 0xED(read) AUDIO2= 1-1-1-1-1-1-0-R/W = 0xFC(write), 0xFD(read) AUDIO 2/ VIDEO 2 and AUDIO 2 clocks Figure 19: I2C Address Determination A detailed description of all programming registers can be found in Section 8. on page 29. Note: Both video clocks have to be connected to the device for proper functioning of the I2C programming interface. (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 24 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip 5. GPIO Block Functional Description GPIOs are multi-purpose pins. They may be programmed as input/output and used to carry signals into the IC or to monitor the status of the IC. The selection of these I/O pins is controlled through programmable registers. The GPIO module can be programmed via subaddress 90-95 of the primary video pipe. 5.1 Overview The GPIO pins operate in two basic modes: Bootstrap mode and GPIO mode During chip reset the GPIOs are in bootstrap mode. The status of all GPIO pins is monitored and used to determine the set of I2C device addresses the IC responds to. After the chip reset is released, the GPIO pins may be used in GPIO mode. In output mode each GPIO pin can be set to logic one or zero by programming the appropriate register. In input mode the status of each GPIO can be monitored by reading the appropriate status register. In addition to the register-driven I/O mode, some of the GPIO pins are used to reflect the status of internal signals. Some GPIO pins are also used as additional inputs to functional units if operated in input mode. 5.2 Operation GPIO Set During Reset During reset the GPIO output is disabled. GPIO_in is stored as gpio_in_stored and retains its value until the next reset. This stored value determines the I2C device addresses. After reset, GPIO pins can be programmed for output with the OEN and OUT_SEL bits. The I2C subaddresses are derived from the GPIOs in the following way: Primary video pipe: {gpio5,gpio4,0,0,gpio3,gpio2,gpio1} Secondary video pipe: {gpio5,gpio4,0,1,gpio3,gpio2,gpio1} Primary audio pipe: {gpio5,gpio4,1,0,gpio3,gpio2,gpio1} Secondary audio pipe: {gpio5,gpio4,1,1,gpio3,gpio2,gpio1} Checking/Setting the GPIO Status Each GPIO pin is multiplexed four times to increase usability. The Figure 20 outlines the internal structure of one GPIO pin. In output mode the selection of the signal routed out to a GPIO pin is performed with the OUT_SEL register bits. The OEN bit is low active and enables the GPIO output mode. If OUT_SEL is set to 2'b11 and the OEN bit is set to zero, the GPIO pin can be set or reset by writing a one or zero into the STATUS location of the GPIO register. All other OUT_SEL settings are listed in 0x90--0x94 GPIO5-GPIO1 (0x90=GPIO1, ..., 0x94=GPIO5) Not present in secondary video channel. To read the external status of a GPIO pin, the OEN needs to be set to one to avoid conflicts with signals routed out of the chip. If GPIO_IN_EN4 is set to one, the status of the GPIO pin can be monitored by reading the STATUS bit of the appropriate GPIO register. The function of all relevant GPIO_IN/OUT signals are listed in Figure 20 and Table 16. 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 25 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors OUT_SEL gpio_out1 gpio_out2 gpio_out3 gpio_out4 GPIO_OUT OEN gpio_in1 GPIO_IN_EN1 gpio_in2 gpio_in3 gpio_in4 gpio_in_stored GPIO_IN_EN2 GPIO_IN_EN3 GPIO_IN_EN4 GPIO_IN GPIO Figure 20: Operation Modes for one GPIO in the PNX8510/11 Table 16: Specific GPIO Assignments Signal gpio5_out1 gpio5_out2 gpio5_in3 gpio4_out1 gpio4_out2 gpio4_in3 gpio3_out1 gpio3_out2 gpio3_in1 gpio3_in2 gpio3_in3 gpio2_out1 gpio2_out2 gpio2_in3 gpio1_out1 gpio_in3 Description Composite sync secondary encoder Vertical sync primary encoder 30-bit parallel video input mode: bit[1] = red channel Data request secondary encoder Composite sync primary encoder 30-bit parallel video input mode: bit[0] = red channel Enable y secondary encoder (1/2 of the encoder operation frequency) Odd/even signal primary encoder Real time control input primary encoder Real time control input secondary encoder 30-bit parallel video input mode: bit[1] = green channel Odd/even signal secondary encoder Data request primary encoder 30-bit parallel video input mode: bit[0] = green channel Vertical sync secondary encoder 30-bit parallel video input mode: bit[0] = blue channel All other settings are reserved for future use. (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 26 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip 6. Clock Module All of the PNX8510/11 modules receive their input clocks from the clocks module. The top level structure of the clocks module is shown below. I2C decoder module dv_clk1 clocks_video_sub_1 clk_dv1_if clk_dv1_proc dv_clk2 clocks_video_sub_2 clk_dv2_if clk_dv2_proc i2s_aos1_clk clocks_audio_sub_1 sclk_a1 ws_a1 i2s_aos2_clk clocks_audio_sub_2 sclk_a2 ws_a2 Figure 21: Clocks Module The PNX8510/11 in normal operation mode receives four external clocks. Two clocks dv_clk1 and dv_clk2 are the clocks used for the primary and secondary video data paths. The other two clocks assemble the audio over-sampling clocks for the primary and secondary audio channel. The PNX8510/11 video clocks are used to create two internal clocks: one for operating the video input interface (clk_dv1_if, clk_dv2_if), and one for operating the main video processing pipeline (clk_dv1_proc, clk_dv2_proc). The audio interface normally operates in slave mode (over-sampling clock, word select and bit clock are provided from the externally connected I2S master). However the PNX8510/11 can be operated in master mode. This mode only requires the over-sampling clock to be provided. The bit clock and the word select signals are subdivided from the over-sampling clock and provided to the chip pins. 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 27 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors 6.1 Clocks Video Submodule The generation of the various clock signals needed for video pipelines takes place in the clocks video module. Figure 22 shows a block diagram of this module. The configuration registers for the clocks module can be found in Section 10. Audio/Clock Address Space. dv_clk sel_v div by 1, 2, 3 or 4 clocks_sel clock divider & degilitcher dv_clk clk_dv_if_out test div by 1, 2, 3 or 4 clocks_sel clock divider & degilitcher dv_clk clk_dv_proc_out test Figure 22: Clocks Video Submodule 6.2 Clocks Audio Submodule The input clocks for the audio block are generated in the clocks audio submodule. Figure 23 shows a block diagram for this submodule. i2s_aos_clk clk_a 4-bit divider sel_a sck_in test_a 9-bit divider ws_in test_a ws_a sclk_a Figure 23: Clocks Audio Submodule 7. Test Mode This section describes how the analog test modes are implemented in the PNX8510/11. Note that these test modes are intended for production test only. The chip needs to be brought into analog test mode via the JTAG boundary scan controller. Once the chip is in analog test mode the different test modes can be enabled via the GPIO pins. The data input for the video DAC's is provided via the DV1 interface for DACs 1 through 4 and via the DV2 interface for DACs 5 and 6 respectively. The "main switch" for the test mode is controlled by the JTAG boundary scan controller. Once the chip is in analog test mode, the GPIO pins can be used to select certain combinations outlined in the tables. (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 28 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip Table 17: Video DAC Test Modes GPIO2 0 0 1 1 GPIO3 0 1 0 1 Test VDAC1 and VDAC5 active VDAC2 and VDAC6 active VDAC3 and VDAC5 active VDAC4 and VDAC6 active For the video DACs 1 to 4, the primary 10-bit D1 interface (DV1_IN[9:0]) provides the 10-bit input. Video DACs 5 and 6 are stimulated through the secondary D1 interface (DV2_IN[9:0]). Table 18: Audio DAC Test Modes GPIO4 0 0 1 1 GPIO5 0 1 0 1 Test ADAC1/2 and ADAC3/4 stereo pair first and second channel off ADAC1/2 stereo pair first channel active ADAC3/4 stereo pair second channel active ADAC1/2 and ADAC3/4 stereo pair first and second channel active The serial audio data streams for the first stereo pair are provided through the I2S_IN1_SD and the I2S_IN1_WS pins. The audio DAC pair 3 and 4 get their serial data through pins I2S_IN2_SD and I2S_IN2_WS. VDAC1 VDAC2 VDAC3 VDAC4 GPIO3 TEST DECODER VIDEO DV2_IN[9:0] VDAC5 VDAC6 GPIO4 TEST DECODER AUDIO I2S_IN1_SD I2S_IN1_WS ADAC1 ADAC2 GPIO2 DV1_IN[9:0] GPIO5 I2S_IN2_SD I2S_IN2_WS ADAC3 ADAC4 Figure 24: Audio and Video DAC Test Modes 8. Register Descriptions The PNX8510/11 register space is divided into four different spaces. Each of them is addressed by a different I2C device address. The first address space is dedicated to the primary video channel, the second space belongs to the secondary video channel. The third I2C address space accommodates the registers that control the first audio channel. The fourth I2C space is used to address the secondary audio channel. 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 29 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors The video channel registers are only listed once. Because the secondary video channel does not support high definition or RGB output, its registers have some minor differences, which are noted in the following tables as "Not present in secondary video channel." The slave addresses are selectable during boot. The registers for the primary and secondary audio and video modules are identical, except as noted in the register definitions. The following tables provide the offset--the base address is dependent on the module. The actual address spaces are determined at boot time according to the GPIO settings. For more information, refer to Section 4. on page 24. Table 19: PNX8510/11 Register Summary Address Name Video Address Space 0x00 0x1A 0x1B 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x38 0x39 0x3A 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x61 0x62 0x63--66 0x67 0x68 STATUS MSMT MSMS WSS1 WSS2 BCTL BCTL2 CGD1 CGD2 CGD DACCTL GAIN_Y GAIN_UV INPCTL VPS1 VPS2 VPS3 VPS4 VPS5 VPS6 CHPS GAINU GAINV BLCKL BLNNL BLNVB/CCR STDCTL BSTA FSC0-FSC3 L21O0 L21O1 Status register Monitor sense mode threshold Monitor sense mode status Wide screen signaling data Wide screen signaling enable Burst control Burst control Copy guard Copy guard Copy guard enable DAC control * Gain adjust for Y component (SD RGB/YUV data path) * Gain adjust for UV component (SD RGB/YUV data path) * Input control register * Video programming system Video programming system Video programming system Video programming system Video programming system Video programming system Color subcarrier phase Gain adjust for U component Gain adjust for V component Black level adjust Blank level adjust Cross color reduction / blank level (during vertical blank) Video standard control Burst amplitude control Color subcarrier frequency control Closed captioning odd field Closed captioning odd field 9397 750 08865 Description (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 30 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip Table 19: PNX8510/11 Register Summary (Cont'd.) Address 0x69 0x6A 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7E 0x7F 0x80 0x81 0x82 0x83--0x85 0x86 0x87--0x8D 0x8E 0x90--0x94 0x95 0x96--0x97 0x98 0x99--0x9A 0x9B--0x9C 0x9D 0x9E 0x9F 0xA0 L21E0 L21E1 TRGCTL1 TRGCTL2 MULTICTL TTXCTL ADWHS ADWHE ADWHS/E TTXHS TTXHL/TTXHD CSYNCA TTXOVS TTXOVE TTXEVS TTXEVE FAL LAL TTXCTRL DTTXL DTTXL2 LCNT_ARRAY_LINE LCNT_ARRAY_LINE LCNT_ARRAY_ADR LTYPE_ARRAY_LINE LTYPE_ARRAY_ADR LPATT_ARRAY_LINE LPATT_ARRAY_ADR GPIO5-GPIO1 VMUXCTL VALUE_ARRAY_LINE VALUE_ARRAY_ADR/ EVENT_TYPE_PTR TRIGGER_LINE TRIGGER_DURATION TRIGGER_PTR BLANK_Y BLANK_UV RGB_CTRL Name Description Closed captioning even field Closed captioning even field SD trigger control SD trigger control Sync and blank control VBI insertion control Active display window start Active display window end Active display window - MSB TTX control TTX control Composite sync control TTX insertion control odd field TTX insertion control odd field TTX insertion control even field TTX insertion control even field First active line Last active line TTX format control TTX mask TTX mask HD sync generator control * HD sync generator control * HD sync generator control * HD sync generator control * HD sync generator control * HD sync generator control * HD sync generator control * GPIO control * Video input mode control * HD sync generator control * HD sync generator control * HD sync generator control * HD sync generator control * HD sync generator control * Programmable blank level for Y (SD RGB/YUV data path) * Programmable blank level for UV (SD RGB/YUV data path) * Color space matrix bypass enable * 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 31 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors Table 19: PNX8510/11 Register Summary (Cont'd.) Address 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBC 0xBE 0xBF 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 Name BORDER_Y BORDER_U BORDER_V MISCCTRL HDCTRL SYNC_DELAY BLANK_R/Y BLANK_G/U BLANK_B/V SYNC_HEIGHT1 SYNC_HEIGHT2 SYNC_WIDTH1 SYNC_WIDTH2 SYNC_TRIGPOS_Y1 SYNC_TRIGPOS_Y2 SYNC_TRIGPOS_X1 SYNC_TRIGPOS_X2 SIG1 SIG2 SIG3 SIG4 SIGCTRL BLANK_MSBs R/Y Value Array Line B/U Value Array Line G/V Value Array Line Value Array Line MSBs DAC1 ADJ DAC2 ADJ DAC3 ADJ DAC4 ADJ DACC ADJ HD_Gain R/Y HD_Gain G/U HD_Gain B/V Border color Border color Border color Description DAC and trigger control * HD video path control * Sync and VBI programming control Blank offset control HD video path * Blank offset control HD video path * Blank offset control HD video path * HD sync generator screen height * HD sync generator screen height * HD sync generator screen width * HD sync generator screen width * HD sync generator vertical position control1 * HD sync generator vertical position control2 * HD sync generator horizontal position control1 * HD sync generator horizontal position control2 * Video signature * Video signature * Video signature * Video signature * Video signature analyzer control * Blank offset control * R/Y value aray data * B/U value aray data * G/V value aray data * Value aray data MSBs * Coarse current control DAC1 * Coarse current control DAC2 * Coarse current control DAC3 * Coarse current control DAC4 * Common current fine adjust for DACs 1-4 * Gain adjust HD path * Gain adjust HD path * Gain adjust HD path * Audio/Clock Address Space 0x0000 0x0001 CLK_AUDIO CLK_IF Audio clock control Video interface clock control (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 32 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip Table 19: PNX8510/11 Register Summary (Cont'd.) Address 0x0002 0x0003 0x00F4 0x00F5--00FB 0x00FC 0x00FD 0x00FE Name CLK_PROC_DIV CLK_DAC_DIV I2S_SET_REG FEATURE_REG INTERPOLATOR_REG1 INTERPOLATOR_REG2 Audio DAC power on register Description Video processing clock control Video DAC clock control Audio interface control Audio feature control Audio feature control Audio feature control Audio DAC control Note: Register entries indicated with an asterisk (*) have a different meaning or are not present in the secondary video address space. For more details, refer to the register description. 9. Video Address Space Read/ Write R R R R R Bits 7 6 5 4 3 2 1 Reset Value 0 0 1 - Name (Field or Function) STATUS VER2 VER1 VER0 CCRDO CCRDE Unused FSEQ Version ID bit 2 Version ID bit 1 Version ID bit 0 Description Offset 0x00 Closed caption encoding done for odd field Closed caption encoding done for even field R - Field Sequence 1 = During first field of a sequence 0 = Not the first field of a sequence Status of the ODD/EVEN flag in the encoder 0 R - O_E Registers 0x01 through 0x10 must be initialized to zero. Bits 7:0 7 Read/ Write R/W R/W Reset Value 0 Name (Field or Function) MSMT MSMT Description Monitor sense mode threshold for DAC's comparator Monitor sense mode 0 = Off 1 = On Offset 0x1A Offset 0x1B MSMS MSM 6:4 3 R/W - Unused MSMS4 Monitor sense status DAC4 0 = Comparator is inactive. 1 = Comparator is active. *Not present in secondary video channel. Monitor sense status DAC3 0 = Comparator is inactive. 1 = Comparator is active. *Not present in secondary video channel. 2 R/W - MSMS3 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 33 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors Bits 1 Read/ Write R/W Reset Value - Name (Field or Function) MSMS2 Description Monitor sense status DAC2 0 = Comparator is inactive. 1 = Comparator is active. Monitor sense status DAC1 0 = Comparator is inactive. 1 = Comparator is active. 0 R/W - MSMS1 Registers 0x1C through 0x25 must be initialized to zero. Bits 7:0 Read/ Write R/W Reset Value - Name (Field or Function) WSS1 WSSD[7:0] Description Wide screen signalling data bits 3:0 = Aspect ratio encoding bits 7:4 = Enhanced services Wide screen signalling enable 0 = wss switched off 1 = wss switched on Offset 0x26 Offset 0x27 7 R/W 0 WSS2 WSSON 6 5:0 R/W - Unused WSSD[13:8] Wide screen signalling data bits 13:11 = Reserved bits 10:8 = Subtitles Field sequence detection via RTC 0 = Field sequence as FISE in address 61 1 = Field sequence detection via RTC interface Color detection via RTC interface 0 = Color detection via RTC disabled 1 = Color detection via RTC enabled Note: The RTCE bit must be set to 1 to enable this feature. Starting point of color burst in clk cycles PAL=0x21 NTSC=0x25 Offset 0x28 7 R/W 0 RTC1/BCTL1 DECFIS 6 R/W 0 DECCOL 5:0 R/W 0x21 BS Offset 0x29 7:6 5:0 R/W 0x1d BCTL2 Unused BE Color burst end point in clk cycles PAL = 0x1D NTSC = 0x1D Copy guard information bits 7:0 Note: The 14 LSBs of the byte carry the information encoded after the run-in. The 6 MSBs have to carry the CRCC bits in accordance with the definition of the CGMS encoding format. Copy guard information bits 15:8 Note: The 14 LSBs of the byte carry the information encoded after the run-in. The 6 MSBs have to carry the CRCC bits in accordance with the definition of the CGMS encoding format. Copy guard enable 0 = Disabled 1 = Enabled Offset 0x2A 7:0 R/W - CGD1 CG Offset 0x2B 7:0 R/W - CGD2 CG Offset 0x2C 7 R/W 0 CGD CGEN (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 34 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip Bits 6:4 3:0 Read/ Write R/W Reset Value CG Name (Field or Function) Unused Description Copy guard information bits 19:16 Note: The 14 LSBs of the byte carry the information encoded after the run-in. The 6 MSBs have to carry the CRCC bits in accordance with the definition of the CGMS encoding format. DAC3 control 0 = Video dac 3 carries the green channel.. 1 = Video dac 3 carries the luminance channel *Not present in secondary video channel. DAC1 control 0 = Video dac 1carries the luminance channel. 1 = Video dac 1 carries the CVBS channel. DAC2 control 0 = Video dac 2 carries the red channel. 1 = Video dac 2 carries the chroma channel. *Not present in secondary video channel. Offset 0x2D 7 R/W 1 DACCTL Video data path VBSEN 6 R/W 1 CVBSEN 5 R/W 1 CEN 4:0 - Unused Registers 0x2E--0x37 must be initialized to zero. Bits 7:5 4:0 R/W Read/ Write Reset Value 0x1A Name (Field or Function) GAIN_Y - Not present in secondary video channel. Unused GAIN_Y Description Offset 0x38 Gain adjust for Y component in SD-RGB/YUV data path, two's complement number to adjust the gain from -50% to +50% Yout=Yin x (1+ GAIN_Y/32) *Not present in secondary video channel. Offset 0x39 7:5 4:0 R/W 0x1A GAIN_UV - Not present in secondary video channel. Unused GAIN_UV Gain adjust for U/V components in SD-RGB/YUV data path, two's complement number to adjust the gain from -50% to +50% UVout=UVin x (1+ GAIN_UV/32) *Not present in secondary video channel. Bits 7 Read/ Write R/W Reset Value 0 Name (Field or Function) INPCTL CBENB Description Color bar generator 0 = Color bar generation switched off 1 = Color bar generation enabled (SD-CVBS/YC modes only) 0 = Leave the pixel qualifier untouched. 1 = Invert the incoming pixel qualifier. *Not present in secondary video channel. Use qualifier enable 0 = No qualifier is used, QUALINVERT should be set. 1 = The HSYNC input is used as slice qualifier in interleaved mode. *Not present in secondary video channel. Offset 0x3A 6 R/W 1 QUALINVERT 5 R/W 0 USE_QUAL 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 35 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors Bits 4 Read/ Write R/W Reset Value 0 Name (Field or Function) DEDGE Description Double edge mode 0 = Double edge mode off; either the interface is running at 2x speed to get interleaved data in or only non-interleaved data streams are accepted. 1 = Input data is latched at positive and negative edge. The SLICE_DIR register determines which data slice goes in which channel. Video mode switch 0 = HD data path in operation; encoder runs idle. 1 = SD data path in operation; encoder is in CVBS/YC or RGB mode *Not present in secondary video channel. 0 = Y/R data channel coming from the D1 interface left unchanged 1 = Y/R MSB of data coming from the D1 interface is inverted. 0 = U/G data channel coming from the D1 interface left unchanged 1 = U/G MSB of data coming from the D1 interface is inverted. 0 = V/B data channel coming from the D1 interface left unchanged 1 = V/B MSB of data coming from the D1 interface is inverted. *Not present in secondary video channel. 3 R/W 1 SD_HD 2 1 0 R/W R/W R/W 1 1 1 U2C M2C L2C Registers 0x3B through 0x53 must be initialized to zero. Bits 7 6:0 Read/ Write R/W Reset Value 0 - Name (Field or Function) VPS1 VPSEN Unused Description 0 = Video programming system data insertion disabled 1 = Video programming system data insertion enabled Offset 0x54 Offset 0x55 7:0 7:0 7:0 7:0 7:0 7:0 R/W R/W R/W R/W R/W R/W 0x0 VPS2 VPSB5 Fifth byte of video programming system data 11th byte of video programming system data 12th byte of video programming system data 13th byte of video programming system data 14th byte of video programming system data Phase of encoded color subcarrier (including burst) relative to horizontal sync. Can be adjusted in steps of 360/256 degrees. Offset 0x56 Offset 0x57 Offset 0x58 Offset 0x59 Offset 0x5A VPS3 VPSB11 VPS4 VPSB12 VPS5 VPSB13 VPS6 VPSB14 CHPS CHPS (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 36 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip Bits 7:0 Read/ Write R/W Reset Value 0x7d Name (Field or Function) GAINU Description Variable gain for Cb signal; input representation is in accordance with CCIR656. White to black = 92.5 IRE GAINU can be adjusted in a range from -2.17 x nominal to 2.16 x nominal GAINU=0 (output subcarrier contribution of U = 0) GAINU=0x76 (output subcarrier contribution of U = nominal) White to black = 100 IRE GAINU can be adjusted in a range from -2.05 x nominal to 2.04 x nominal GAINU=0 (output subcarrier contribution of U = 0) GAINU=0x7D (output subcarrier contribution of U = nominal) GAINU=0x6A (nominal Gain for Secam encoding) Variable gain for Cr signal; input representation is in accordance with CCIR656. White to black = 92.5 IRE GAINV can be adjusted in a range from -1.55 x nominal to 1.55 x nominal GAINV=0 (output subcarrier contribution of V = 0) GAINV=0xA5 (output subcarrier contribution of V = nominal) White to black = 100 IRE GAINV can be adjusted in a range from -1.46 x nominal to 1.46 x nominal GAINV=0 (output subcarrier contribution of V = 0) GAINV=0xAF (output subcarrier contribution of V = nominal) GAINV=0x7F (nominal Gain for Secam encoding) Bit 8 of register 0x5B Odd/even field control via RTC interface 0 = Disabled 1 = Enabled Variable black level; input representation is in accordance with CCIR656. White to sync = 140 IRE recommended BLCKL=0x3A BLCKL=0 (output black level = 29 IRE) BLCKL=0x3F (output black level = 49 IRE) output black level/IRE=BLCKL x 2/6.29+28.9 White to sync = 143 IRE recommended BLCKL=0x33 BLCKL=0 (output black level = 27 IRE) BLCKL=0x3F (output black level = 47 IRE) output black level/IRE=BLCKL x 2/6.18+26.5 Bit 8 of register 0x5C Subcarrier phase reset control via RTC interface 0 = Disabled 1 = Enabled Offset 0x5B, 0x5D(MSB) GAINU Offset 0x5C, 0x5E(MSB) GAINV 7:0 R/W 0xaf GAINV Offset 0x5D 7 6 R/W R/W 0 0 BLCKL GAINU DECOE 5:0 R/W 0x33 BLCKL Offset 0x5E 7 6 R/W R/W 0 0 BLNNL GAINV DECPH 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 37 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors Bits 5:0 Read/ Write R/W Reset Value 0x35 Name (Field or Function) BLNNL Description Variable blanking level White to sync = 140 IRE recommended BLCKL=0x2E BLNNL=0 (output black level = 26 IRE) BLNNL=0x3F (output black level = 46 IRE) output black level/IRE=BLCKL x 2/6.29+25.4 White to sync = 143 IRE recommended BLCKL=0x35 BLNNL=0 (output black level = 26 IRE) BLNNL=0x3F (output black level = 46 IRE) output black level/IRE=BLCKL x 2/6.18+25.9 Cross-color reduction filter settings for luminance path 00 = Cross color reduction filter off 01 = Filter is active; transfer characteristic 1 10 = Filter is active; transfer characteristic 2 11 = Filter is active; transfer characteristic 3 Variable blanking level during vertical blanking interval is typically identical to the value of BLNNL. Offset 0x5F 7:6 R/W 0x0 BLNVB/CCR CCRS 5:0 R/W 0x35 BLNVB Offset 0x60 Offset 0x61 7:6 5 R/W 0 must be initialized to zero. STDCTL Unused INPI 0 = PAL switch phase is nominal. 1 = PAL switch phase is inverted compared to nominal if RTC is enabled. 0 = Luminance gain for white - black 100 IRE 1 = Luminance gain for white - black 92.5 IRE including 7.5 IRE set-up of black SECAM enable 0 = Secam encoding switched off 1 = Secam encoding switched on (PAL has to be 0) 0 = Enlarged bandwidth for chrominance encoding 1 = Standard bandwidth for chrominance encoding 0 = NTSC encoding (non alternating V component) 1 = PAL encoding (alternating V component) 0 = 864 total pixel per line 1 = 858 total pixel per line 0 = No real time control of generated subcarrier frequency 1 = Real time control of generated subcarrier frequency Amplitude of color burst; input representation is in accordance with CCIR 601 White to black = 92.5 IRE, burst = 40 IRE, NTSC encoding BSTA 0 to 2.02 x nominal recommended value BSTA = 0x3F White to black = 92.5 IRE, burst = 40 IRE, PAL encoding BSTA 0 to 2.82 x nominal recommended value BSTA = 0x2D White to black = 100 IRE, burst = 40 IRE, NTSC encoding BSTA 0 to 1.90 x nominal recommended value BSTA = 0x43 White to black = 92.5 IRE, burst = 40 IRE, PAL encoding BSTA 0 to 3.02 x nominal recommended value BSTA = 0x2F fixed burst amplitude for SECAM encoding 9397 750 08865 4 R/W 0 YGS 3 R/W 0 SECAM 2 1 0 R/W R/W R/W 1 1 0 SCBW PAL FISE Offset 0x62 7 6:0 R/W R/W 0 0x2f RTCCTL/BSTA RTCE BSTA (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 38 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip Bits 7:0 Read/ Write R/W Reset Value 0x2A09 8ACB Name (Field or Function) FSC0-FSC3 0x63=FSC0 0x64=FSC1 0x65=FSC2 0x66=FSC3 Description ffsc: subcarrier frequency (in multiples of line frequency) fllc: clock frequency (in multiples of line frequency) FSC = round ((ffsc/fllc)x2^32) FSC3 most significant byte FSC0 least significant byte NTSC-M: ffsc 227.5, fllc 1716 -> FSC = 21F07C1F PAL-B/G: ffsc 283.7516, fllc 1728 -> FSC = 2A098ACB SECAM: ffsc 274.304, fllc 1728 -> FSC = 28A33BB2 First byte of closed captioning data, odd field Second byte of closed captioning data, odd field First byte of closed captioning data, even field Second byte of closed captioning data, even field Offset 0x63--0x66 Offset 0x67 7:0 7:0 7:0 7:0 R/W R/W R/W R/W 0x0 0x0 0x0 0x0 L21O0 L21O0 Offset 0x68 Offset 0x69 Offset 0x6A Offset 0x6B Offset 0x6C 7:0 R/W 0x01 L21O1 L21O1 L21E0 L21E0 L21E1 L21E1 must be initialized to zero. TRGCTL1 - Not present in secondary video channel. HTRIG Sets horizontal trigger phase related to encoder input. Values above 1715 (FISE=1) or 1727 (FISE=0) are not allowed. Increasing HTRIG decreases delay as of all internally generated timing signals Reference mark: analog output horizontal sync (leading slope) coincides with active edge of RCV used for triggering at HTRIG=0x398. Sets horizontal trigger phase related to encoder input. Increasing VTRIG decreases delays of all internally generated timing signals measured in half lines. Variation range of VTRIG = 0 to 0x1F Offset 0x6D 7:5 4:0 R/W R/W 0x1 0x0 TRGCTL2 - Not present in secondary video channel. HTRIG VTRIG Offset 0x6E 7 6 5:4 R/W R/W 0 0x2 MULTICTL Unused BLCKON PHRES 0 = Encoder in normal operation mode 1 = Output signal is forced to blanking level. Selects the phase reset mode of the color subcarrier. 00 = No phase reset or reset via RTC 01 = Phase reset every two lines 10 = Reset every eight fields 11 = Reset every four fields Selects the luminance delay in reference to the chrominance 00 = No luma delay 01 = 1LLC luma delay 10 = 2LLC luma delay 11 = 3LLC luma delay Field length control 00 = Interlaced 312.5 lines/field at 50Hz, 262.5 lines/field at 60Hz 01 = Non interlaced 312 lines @50Hz, 262 lines @60Hz 10 = Non interlaced 313 lines @50Hz, 263 lines @60Hz 11 = Non interlaced 313 lines @50Hz, 263 lines @60Hz 3:2 R/W 0x0 LDEL 1:0 R/W 0x0 FLC 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 39 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors Bits 7:6 Read/ Write R/W Reset Value 0x00 Name (Field or Function) TTXCTL CCEN Description Closed caption enable 00 = Line 21 encoding off 01 = Enables encoding in field 1 (odd). 10 = Enables encoding in field 2 (even). 11 = Enables encoding in both fields. 0 = Disables teletext insertion. 1 = Enables teletext insertion. Selects the actual line where closed caption or extended data are encoded. line = (SCCLN + 4) for M-systems line = (SCCLN +1) for other systems Active Display Window Start bits 7 to 0 Defines the start of the active TV display portion after the border color. Values above 1715 (FISE=1) or 1727 (FISE=0) are not allowed. Active Display Window End bits 7 to 0 Defines the start of the active TV display portion after the border color. Values above 1715 (FISE=1) or 1727 (FISE=0) are not allowed. Offset 0x6F 5 4:0 R/W R/W 0 0x11 TTXEN SCCLN Offset 0x70 7:0 R/W 0x5a ADWHS ADWHS7:0 Offset 0x71 7:0 R/W 0x5a ADWHE ADWHE7:0 Offset 0x72 7 6:4 R/W 0x6 ADWHS/E Unused ADWHE10:8 Active Display Window End bits 10 to 8. Defines the start of the active TV display portion after the border color. Values above 1715 (FISE=1) or 1727 (FISE=0) are not allowed. 3 2:0 R/W 0x1 Unused ADWHS10:8 Active Display Window Start bits 10 to 8 Defines the start of the active TV display portion after the border color. Values above 1715 (FISE=1) or 1727 (FISE=0) are not allowed. Start of signal on TTXRQ Length of TTXRQ window; only active at old TTX protocol Note: bit TTXO = 1 Indicates the delay in clock cycles between rising edge of TTXRQ output and valid data at pin TTX. Advanced composite sync against RGB output, adjustable from 0 XTAL clocks to 31 XTAL clocks Offset 0x73 7:0 7:4 3:0 R/W R/W R/W 0x42 0x5 0x2 TTXHS TTXHS Offset 0x74 TTXHL/TTXHD TTXHL TTXHD Offset 0x75 7:3 2:0 R/W 0x0 R/W 0x5 CSYNCA CSYNCA Unused Offset 0x76 7:0 TTXOVS TTXOVS First line of occurrence of ttx data in odd field line = (TTXOVS + 4) for M-systems line = (TTXOVE +1) for other systems PAL: TTXOVS = 0x05 NTSC: TTXOVS = 0x06 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 40 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip Bits 7:0 Read/ Write R/W Reset Value 0x16 Name (Field or Function) TTXOVE TTXOVE Description Last line of occurrence of ttx data in odd field line = (TTXOVS + 3) for M-systems line = TTXOVE for other systems PAL: TTXOVS = 0x16 NTSC: TTXOVS = 0x10 First line of occurrence of ttx data in even field line = (TTXOVS + 4) for M-systems line = (TTXOVE + 1) for other systems PAL: TTXOVS = 0x04 NTSC: TTXOVS = 0x05 Last line of occurrence of ttx data in even field line = (TTXOVS + 3) for M-systems line = TTXOVE for other systems PAL: TTXOVS = 0x16 NTSC: TTXOVS = 0x10 First active line = FAL+4 for M-systems and = FAL+1 for other systems. Measured in lines, FAL = 0 coincides with the first field sync pulse. Last active line = LAL+3 for M-systems and = FAL for other systems. Measured in lines, LAL = 0 coincides with the first field sync pulse. 0 = Enables NABTS (FISE=1) or European TTX (FISE=0). 1 = Enables World Standard Teletext 60Hz (FISE=1). Bit 8 of LAL 0 =New TTX protocol selected. At each rising edge of TTXRQ a single TTX bit is requested. 1 = Old TTX protocol selected. The encoder provides a window of TTXRQ. The length of the window depends on the chosen TTX standard. Bit 8 of FAL Bit 8 of TTXEVE Bit 8 of TTXOVE Bit 8 of TTXEVS Bit 8 of TTXOVS Offset 0x77 Offset 0x78 7:0 R/W 0x4 TTXEVS TTXEVS Offset 0x79 7:0 R/W 0x16 TTXEVE TTXEVE Offset 0x7A 7:0 R/W 0x24 FAL FAL Offset 0x7B 7:0 R/W 0x29 LAL LAL Offset 0x7C 7 6 5 R/W R/W R/W 0 1 0 TTXCTRL TTX60 LAL8 TTXO 4 3 2 1 0 R/W R/W R/W R/W R/W 0 0 0 0 0 FAL8 TTXEVE8 TTXOVE8 TTXEVS8 TTXOVS8 Offset 0x7D Offset 0x7E 7:0 R/W 0x00 Must be initialized to zero. DTTXL DTTXL Individual lines in both fields (PAL counting) can be disabled for insertion of teletext by the respective bits. Disabled line =LINExx(50Hz field rate). Bit 7 = Line 12; Bit 0 = Line 5 The mask is only effective if the lines are enabled via TTXOVS/ TTXOVE and TTXEVS/TTXEVE. 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 41 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors Bits 7:0 Read/ Write R/W Reset Value 0x00 Name (Field or Function) DTTXL2 DTTXL Description Individual lines in both fields (PAL counting) can be disabled for insertion of teletext by the respective bits. Disabled line = LINExx(50Hz field rate) Bit 7 = Line 20; Bit 0 = Line 13 The mask is only effective if the lines are enabled via TTXOVS/ TTXOVE and TTXEVS/TTXEVE. Line count array programming data lower 8 bits Offset 0x7F Offset 0x80 7:0 7:6 5:0 7:4 3:0 R/W R/W R/W - LCNT_ARRAY_LINE - Not present in secondary video channel. LCNT_ARRAY_LINE Unused LCNT_ARRAY_LINE Unused LCNT_ARRAY_ADR Line count array programming address Writing to this address initiates the transfer of the data previously written into locations 80 and 81 into an internal register array. Line type array programming data 2:0 = first index ... 23:21 = last index Line count array programming data upper 6 bit Offset 0x81 LCNT_ARRAY_LINE - Not present in secondary video channel. Offset 0x82 LCNT_ARRAY_ADR - Not present in secondary video channel. Offset 0x83--0x85 7:0 R/W - LTYPE_ARRAY_LINE - Not present in secondary video channel. LTYPE_ARRAY_LINE 0x83 -> LSBs 0x85 -> MSBs Offset 0x86 7:4 3:0 R/W - LTYPE_ARRAY_ADR - Not present in secondary video channel. Unused LTYPE_ARRAY_ADR Line type array programming address Writing to this address initiates the transfer of the data previously written into locations 83 through 85 into an internal register array. Line pattern array programming data 13:4 = first duration 3:0 = first index ... 55:46 = last duration 45:42 last index Offset 0x87--0x8D 7:0 R/W - LPATT_ARRAY_LINE - Not present in secondary video channel. LPATT_ARRAY_LINE 0x87 -> LSBs 0x8D -> MSBs Offset 0x8E 7:3 2:0 R/W - LPATT_ARRAY_ADR - Not present in secondary video channel. Unused LTYPE_ARRAY_ADR Line pattern array programming address Writing to this address initiates the transfer of the data previously written into locations 87 through 8D into an internal register array. Offset 0x8F Offset 0x90--0x94 7 6 5 4 3 2 R/W R/W R/W R/W R/W R/W 0 0 0 0 1 0 must be initialized to zero. GPIO5-GPIO1 (0x90=GPIO1, ..., 0x94=GPIO5) Not present in secondary video channel. GPIO_IN_EN4 GPIO_IN_EN3 GPIO_IN_EN2 GPIO_IN_EN1 OEN STATUS GPIO input enable 4 GPIO input enable 3 GPIO input enable 2 GPIO input enable 1 Output enable Write to register sets the GPIO pin if output select is set to 2'b11. Read to register returns the status of the gpio pin if GPIO_IN_EN4 is set, otherwise it returns 0. (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 42 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip Bits 1:0 Read/ Write R/W Reset Value 0 Name (Field or Function) OUT_SEL Description Output selection bits 00 = Selects gpio_out1 01 = Selects gpio_out2 10 = Selects gpio_out3 11 = Read gpio status if GPIO_IN_EN4(bit7) is set. 0 = 8-bit mode 1 =10-bit mode 0 = Incoming data stream contains a single D1 stream. 1 = Incoming data stream is in sliced mode. De-slicer control determines where the extracted slice goes. 0: incoming slice 1 == outgoing slice 1 incoming slice 2 == outgoing slice 2 1: incoming slice 1 == outgoing slice 2 incoming slice 2 == outgoing slice 1 Data slice select mode Primary video channel: 00 = Slice 1 primary interface 01 = Slice 2 primary interface 10 = Slice 1 secondary interface 11 = Slice 2 secondary interface Secondary video channel: 00 = Slice 1 secondary interface 01 = Slice 2 secondary interface 10 = Slice 1 primary interface 11 = Slice 2 primary interface Output demultiplex mode 000 = yuv422 001 = yuv444 / RGB444 010 = yuvx / RGBx 011 = yuvhd (double interface mode) 100= yuv422hd (single interface mode) All other modes are reserved. Offset 0x95 7 6 5 R/W R/W R/W 1 1 0 VMUXCTL 8/10-BIT SLICE_MODE SLICE_DIR 4:3 R/W 0x0 SEL 2:0 R/W 0x0 DEMUX_MODE Offset 0x96--0x97 Offset 0x98 7 6:4 3 2:0 R/W - Must be initialized to zero. VALUE_ARRAY_ADR/EVENT_TYPE_PTR - Not present in secondary video channel. Unused EVENT_TYPE_PTR Unused VALUE_ARRAY_ADR Value array programming address Writing to this address initiates the transfer of the data previously written into locations 0xBE through 0xC1 into an internal register array. This value is used as a line count after trigger. register 0x99 bits 7:0 register 0x9A bits 9:8 This value is used as the duration for a certain value after trigger. register 0x9B bits 7:0 register 0x9C bits 9:8 This value is used as the line count pointer after trigger. HD SYNC generator event type pointer; trigger load value Offset 0x99--0x9A 7:0 R/W - TRIGGER_LINE - Not present in secondary video channel. TRIGGER_LINE Offset 0x9B--0x9C 7:0 R/W - TRIGGER_DURATION - Not present in secondary video channel. TRIGGER_DURATION Offset 0x9D 7:4 R/W - TRIGGER_PTR - Not present in secondary video channel. LCNT_PTR_TRIGGER 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 43 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors Bits 3:2 1:0 7:0 7:0 7:2 1 Read/ Write R/W R/W R/W Reset Value 0x90 0 - Name (Field or Function) Unused LPATT_PTR_TRIGGER BLANK_Y BLANK_UV Unused DEMOFF Description This value is used as the line pattern pointer after trigger. Programmable blank level for the R\Y SD-RGB/YUV channel Programmable blank level for the UV SD-RGB/YUV channel Offset 0x9e Offset 0x9f Offset 0xA0 R/W 0 BLANK_Y - Not present in secondary video channel. BLANK_UV - Not present in secondary video channel. RGB_CTRL - Not present in secondary video channel. YUV to RGB matrix bypass 0 = matrix enabled 1= matrix bypassed 0 - Reserved Register 0xA1 must be initialized to zero. Bits 7:0 7:0 7:0 7 6 W Read/ Write R/W R/W R/W Reset Value 0x80 0x80 0x80 0 Name (Field or Function) BORDER_Y BORDER_Y Description Border color Y component for encoder operation mode Border color U component for encoder operation mode Border color V component for encoder operation mode Offset 0xA2 Offset 0xA3 Offset 0xA4 Offset 0xA5 BORDER_U BORDER_U BORDER_V BORDER_V MISCCTRL Unused M24/30 Parallel video input mode select 0=30 bit parallel video input mode 1=24 bit parallel video input mode For details about which pins are used in 24 and 30-bit parallel modes, please refer to section 2 table 5. *Not present in secondary video channel. Always reads back `0'. External/embedded trigger selection 0 = External VSYNC/O_E signal triggers the HD-SYNC generator 1 = D1 embedded O_E signal used to trigger the HD-SYNC generator *Not present in secondary video channel. HD video data path enable 0 = Video demultiplexer bypassed for incoming 24/30-bit full parallel video streams (DEMUX_MODE settings ignored) 1 = Video demultiplexer enabled for HD signals (DEMUX_MODE settings apply) *Not present in secondary video channel. 5 R/W 1 TRIGGER_MODE 4 R/W 1 VMODE 3 2 R/W 0 Unused SLEEP Video DAC sleep mode powers off all analog circuitry but the band gap reference. primary video channel: DAC1-4 secondary video channel: DAC5-6 1 - Unused (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 44 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip Bits 0 Read/ Write R/W Reset Value 0 PD Name (Field or Function) Description Power down mode for DACs; powers all analog circuitry primary video channel: DAC1-4 secondary video channel: DAC5-6 Y Two's complement <-> binary offset conversion 0 = Data at the output of the HD-data path are left unchanged 1 = MSB of data output of the HD-data path is inverted U Two's complement <-> binary offset conversion 0 = Data at the output of the HD-data path are left unchanged. 1 = MSB of data output of the HD-data path is inverted. V Two's complement <-> binary offset conversion 0 = Data at the output of the HD-data path are left unchanged. 1 = MSB of data output of the HD-data path is inverted. Enables insertion of R/Y sync signals into the component signals. 0 = Embedded sync is disabled. 1 = Embedded sync is enabled. Enables insertion of G/U sync signals into the component signals. 0 = Embedded sync is disabled. 1 = Embedded sync is enabled. Enables insertion of B/V sync signals into the component signals. 0 = Embedded sync is disabled. 1 = Embedded sync is enabled. Sync signal insertion enable 0 = No insertion of HD sync module generated sync signals - the external signals are forwarded to the sync pouts. 1 = The insertion of HD sync module generated H-sync, V-sync and Blank signals is enabled. (Note: This disables external sync signals.) * H-sync is derived from sync value[0]. * V-sync is derived from sync value[1]. * C-blank is derived from sync value[2]. Enable 422 to 444 upsampling filter 0 = Filter switched into bypass mode 1 = Filter is active. Offset 0xA6 7 R/W 0 HDCTRL - Not present in secondary video channel. Y_TOCO 6 R/W 0 U_TOCO 5 R/W 0 V_TOCO 4 R/W 0 Y/R_SYNC_INS_EN 3 R/W 0 U/G_SYNC_INS_EN 2 R/W 0 V/B_SYNC_INS_EN 1 R/W 0 SYNC_SIG_EN 0 R/W 0 UPSAMPLE_EN Offset 0xA6 7:5 4:0 7:5 4:0 7:4 3:0 7 R/W R/W R/W 0 0 0 0 DAC6_ADJ - Not present in primary video channel. Unused DAC6_ADJ Unused DAC5_ADJ Unused DACC_ADJ DAC5 and 6 output level fine adjustment 0 = Programming via VBI disabled (use this mode for 24-bit parallel mode and any other mode containing non-656 compliant data). 1 = Programming via VBI enabled DAC5 output level coarse adjustment DAC6 output level coarse adjustment Offset 0xA7 DAC5_ADJ - Not present in primary video channel. Offset 0xA8 DACC_ADJ - Not present in primary video channel. Offset 0xA7 SYNC_DELAY VBIPROG 6:3 2:0 1 Unused SYNC_DELAY Determines the sync-data delay for the incoming data stream and the associated H/V sync and Blank signals. *Not present in secondary video channel. 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 45 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors Bits 7:0 Read/ Write Reset Value 0x0 0x0 0x0 - Name (Field or Function) BLANK_R/Y BLANK_G/U BLANK_B/V SYNC_HEIGHT1 SYNC_HEIGHT2 SYNC_WIDTH1 SYNC_WIDTH2 SYNC_TRIGPOS_Y1 SYNC_TRIGPOS_Y2 SYNC_TRIGPOS_X1 SYNC_TRIGPOS_X2 SIG1 SIG2 SIG3 SIG4 Description Blank offset for the R/Y LSBs Blank offset for the G/U LSBs Blank offset for the B/V LSBs Sync raster height bits 7:0 Sync raster height bits 15:8 Sync raster width bits 7:0 Sync raster width bits 15:8 y trigger position bits 7:0 y trigger position bits 15:8 x trigger position bits 7:0 x trigger position bits 15:8 Bit 7:0 primary video path signature Bit 15:8 primary video path signature Bit 7:0 secondary video path signature Bit 15:8 secondary video path signature Number of syncs needed to trigger signature analysis [-1] AND combination of signature done for primary and secondary channel Signature analyzer enable signal 0 = Signature analyzer disabled 1 = Signature analyzer enabled Video channel select for signature analysis 00 =Video dac 1 and video dac 5 01 =Video dac 2 and video dac 5 10 =Video dac 3 and video dac 6 11 = Video dac 4 and video dac 6 Offset 0xA8 Offset 0xA9 7:0 BLANK_R/Y - Not present in secondary video channel. BLANK_G/U - Not present in secondary video channel. BLANK_B/V - Not present in secondary video channel. SYNC_HEIGHT1 - Not present in secondary video channel. SYNC_HEIGHT2 - Not present in secondary video channel. - Offset 0xAA 7:0 Offset 0xAE 7:0 Offset 0xAF 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:4 3 2 R/W R/W R/W R/W R/W R/W R/W R R R R R/W R R/W 0x7 0 Offset 0xB0 Offset 0xB1 Offset 0xB2 Offset 0xB3 Offset 0xB4 Offset 0xB5 Offset 0xB6 Offset 0xB7 Offset 0xB8 Offset 0xB9 Offset 0xBA SYNC_WIDTH1 - Not present in secondary video channel. SYNC_WIDTH2 - Not present in secondary video channel. SYNC_TRIGPOS_Y1 - Not present in secondary video channel. SYNC_TRIGPOS_Y2 - Not present in secondary video channel. SYNC_TRIGPOS_X1 - Not present in secondary video channel. SYNC_TRIGPOS_X2 - Not present in secondary video channel. SIG1- Not present in secondary video channel. SIG2- Not present in secondary video channel. SIG3- Not present in secondary video channel. SIG4- Not present in secondary video channel. SIGCTRL- Not present in secondary video channel. SYNC_CTRL SIG_DONE SIG_ENABLE 1:0 R/W 0x0 SIG_SELECT Offset 0xBC 7:6 5:4 R/W - BLANK_MSBs- Not present in secondary video channel. Unused BLANK_R/Y Blank offset for the HD-R/Y channel MSBs (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 46 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip Bits 3:2 1:0 7:0 Read/ Write R/W R/W R/W Reset Value - Name (Field or Function) BLANK_G/U BLANK_B/V R/Y-VALUE_ARRAY_LINE Description Blank offset for the HD-G/U channel MSBs Blank offset for the HD-B/V channel MSBs R/Y Value array programming data register 0xBE bits 7:0 register 0xC1 bits 9:8 G/U Value array programming data register 0xBF bits 7:0 register 0xC1 bits 9:8 B/V Value array programming data register 0xC0 bits 7:0 register 0xC1 bits 9:8 Offset 0xBE R/Y VALUE_ARRAY_LINE - Not present in secondary video channel. Offset 0xBF 7:0 R/W - G/U VALUE_ARRAY_LINE - Not present in secondary video channel. G/U-VALUE_ARRAY_LINE Offset 0xC0 7:0 R/W - B/V VALUE_ARRAY_LINE - Not present in secondary video channel. B/V-VALUE_ARRAY_LINE Offset 0xC1 7:6 5:4 3:2 1:0 7:5 4:0 7:5 4:0 7:5 4:0 7:5 4:0 7:4 3:0 7:0 R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0x00 VALUE_ARRAY_LINE-MSBs - Not present in secondary video channel. Unused R/Y-VALUE_ARRAY_LINE G/U-VALUE_ARRAY_LINE B/V-VALUE_ARRAY_LINE Unused DAC1_ADJ Unused DAC2_ADJ Unused DAC3_ADJ Unused DAC4_ADJ Unused DACC_ADJ HD_GAIN_R/Y DAC1 to 4 output level fine adjustment Gain adjust for R/Y component in HD-RGB/YUV data path, two's complement number to adjust the gain from 1-0.5 to 1+-0.5 out=in x (1+ GAIN/256) Gain adjust for G/U component in HD-RGB/YUV data path, two's complement number to adjust the gain from 1-0.5 to 1+-0.5 out=in x (1+ GAIN/256) Gain adjust for B/Vcomponent in HD-RGB/YUV data path, two's complement number to adjust the gain from 1-0.5 to 1+-0.5 out=in x (1+ GAIN/256) DAC4 output level coarse adjustment DAC3 output level coarse adjustment DAC2 output level coarse adjustment DAC1 output level coarse adjustment R/Y Value array programming data MSBs G/U Value array programming data MSBs B/V Value array programming data MSBs Offset 0xC2 DAC1_ADJ - Not present in secondary video channel. Offset 0xC3 DAC2_ADJ - Not present in secondary video channel. Offset 0xC4 DAC3_ADJ - Not present in secondary video channel. Offset 0xC5 DAC4_ADJ - Not present in secondary video channel. Offset 0xC6 DACC_ADJ - Not present in secondary video channel. Offset 0xC7 HD_GAIN_RY - Not present in secondary video channel. Offset 0xC8 7:0 R/W 0x00 HD_GAIN_GU - Not present in secondary video channel. HD_GAIN_G/U Offset 0xC9 7:0 R/W 0x00 HD_GAIN_BV - Not present in secondary video channel. HD_GAIN_B/V 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 47 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors 10. Bits 7:1 0 Audio/Clock Address Space Read/ Write Reset Value R/W 0 Name (Field or Function) CLK_AUDIO Unused CLK_AUDIO 0= I2S is in slave mode. 1= I2S is in master mode. Description Offset 0000 Offset 0001 7:5 4 3 2:1 R/W R/W R/W 0 0 0x0 CLK_IF Video Interface Clock Unused CLK_IF_DIV8 CLK_IF_DIV6 CLK_IF_DIV 0 = default (divide by 4). 1 = divide by 8. 0 = default (divide by 3). 1 = divide by 6. 00= clk_if is input video clock divide by 1 (feed through). 01= clk_if is input video clock divide by 2. 10= clk_if is input video clock divide by 3/6. 11= clk_if is input video clock divide by 4/8. 0 = Normal functional mode 1 = Set the clock to zero. 0 R/W 0 CLK_IF_EN Offset 0002 7:5 4 3 2:1 R/W R/W R/W 0 0 0x0 CLK_PROC_DIV Video Processing Clock Unused CLK_PROC_DIV8 CLK_PROC_DIV6 CLK_PROC_DIV 0 = Divide by 4. 1 = Divide by 8. 0 = Default (div.ide by 3). 1 = Divide by 6 00 = clk_proc is input video clock divide by 1 (feed through). 01 = clk_proc is input video clock divide by 2. 10 = clk_proc is input video clock divide by 3/6. 11 = clk_proc is input video clock divide by 4/8. 0 = Normal functional mode 1 = Set the clock to zero. 0 R/W 0 CLK_PROC_EN Bits 7:4 3:0 Read/ Write Reset Value - Name (Field or Function) I2S_SET_REG Unused i2s_format 0000 0001 0010 0011 0100 1000 Description Offset 00F4 R/W 0 / Philips I2S / LSB justified 16 bits / LSB justified 18 bits / LSB justified 20 bits / MSB / LSB justified 24 bits All other combinations are reserved for future use. Offset 00F5(LSBs)--00FB(MSBs) FEATURE_REG 54:47 46:39 38:36 Unused Unused Unused (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 48 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip Bits 35:33 Read/ Write R/W Reset Value 0 Name (Field or Function) de-emph_1 Description De-emphasis Enable the digital de-emphasis filter for this channel. 000 = Other 001 = 32 kHz 010 = 44.1 kHz 011 = 48 kHz 100 = 96 kHz 32 31 R/W 0 Unused mt1 Mute 0 = Mute off 1 = Mute on Controls the mode of the sound processing filters of Bass Boost and Treble. 00 = Flat 01 = Min 10 = Min 11 = Max Master volume control for right channel. Two times this 8-bit value to control the volume attenuation. The range is 0 dB to - dB in steps of 0.25 dB. Bass-boost for right channel Result is dependent on the sound_feature setting [30:29]. 20:17 Flat Min Max 0000 0 dB 0 dB 0 dB 0001 0 dB 2 dB 2 dB 0010 0 dB 4 dB 4 dB 0011 0 dB 6 dB 6 dB 0100 0 dB 8 dB 8 dB 0101 0 dB 10 dB 10 dB 0110 0 dB 12 dB 12 dB 0111 0 dB 14 dB 14 dB 1000 0 dB 16 dB 16 dB 1001 0 dB 18 dB 18 dB 1010 0 dB 18 dB 20 dB 1011 0 dB 18 dB 22 dB 1100 0 dB 18 dB 24 dB 1101 0 dB 18 dB 24 dB 1110 0 dB 18 dB 24 dB 1111 0 dB 18 dB 24 dB Treble for right channel. Result is dependent on the sound_feature setting [30:29]. 16:15 Flat Min Max 00 0 dB 0 dB 0 dB 01 0 dB 2 dB 2 dB 10 0 dB 4 dB 4 dB 11 0 dB 6 dB 6 dB Master volume control for left channel. Two times this 8-bit value to control the volume attenuation. The range is 0 dB to - dB in steps of 0.25 dB. Bass-boost for left channel Result is dependent on the sound_feature setting [30:29]. (Refer to bboost_right [20:17] above.) Treble for left channel. Result is dependent on the sound_feature setting [30:29]. 16:15 Flat Min Max 00 0 dB 0 dB 0 dB 01 0 dB 2 dB 2 dB 10 0 dB 4 dB 4 dB 11 0 dB 6 dB 6 dB (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 30:29 R/W 0 sound_feature 28:21 R/W 0 master_vol_right 20:17 R/W 0 bboost_right 16:15 R/W 0 treble_right 14:7 R/W 0 master_vol_left 6:3 R/W 0 bboost_left 2:1 R/W 0 treble_left 9397 750 08865 Product data Rev. 02 -- 8 October 2001 49 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors Bits 0 Read/ Write R/W Reset Value 0 Name (Field or Function) mtm Mute 0 = Mute off 1 = Mute on Description Offset 00FC 7 R/W 0 INTERPLATOR_REG1 sdet_on Silence detect enable 0 = Silence detection circuit disabled 1 = Silence detection circuit enabled Silence override 0 = No override. Audio DAC silence switch setting depends on the silence detector circuit and or on the master_mute status. 1 = Override. The Audio DAC silence switch is activated. Switch between `flat' (for the Digital Amplifier) or `compensate' correction filter curve (for the Audio DAC). 0 = Curve for Audio DAC 1 = Curve for Digital Power Amp Select the polarity of the DATA to the Audio DAC = a means to control the output signal polarity. The DC and AC dither which must be added to the noise-shaper input will NOT be inverted when inverting the audio data. 0 = Non inverting data out 1 = Inverting data out The number of `zero' samples counted before the silence detector signals whether there has been digital silence: 00 = 3200 samples 01 = 4800 samples 10 = 9600 samples 11 = 19200 samples 6 R/W 0 silence_override 5 R/W 0 filter_comp 4 R/W 0 da_pol_inv 3:2 R/W 00 sd_value 1 0 R/W 0 Unused Unused Offset 00FD 7:6 5:4 3 INTERPOLATOR_REG2 Unused Unused quickmute This is an overriding quickmute on the master channel which mutes the interpolator output signal in 32 samples, using the cosine rolloff coefficients. 0 = Quick mute is off 1 = Quick mute on Mute function via micro controller interface: 0 = Soft mute mode 1 = Quick mute mode 2 R/W 0 mutemode 1 0 R/W 1 Unused Unused Offset 00FE 7:1 0 Audio DAC power on register Unused pon 1 = Power on for audio DAC 0 = Power off for audio DAC (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 50 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip 11. Video Programming Examples The following listings provide programming examples for setting up a video channel into PAL, NTSC and SECAM modes. [ANABEL_VIDEO] has to be substituted with the appropriate I2C base address for the primary or secondary video channel. [ANABEL_AUDIO] has to be substituted with the appropriate I2C base address for the primary or secondary audio channel. Note: The RGB and 1080i examples are only applicable to the primary video channel. Table 20: NTSC Mode (CVBS/YC 27 MHz YUV422 Interface Mode) [ANABEL_VIDEO] Offset bit 7 of 0x27 bit 7 of 0x54 bit 6 of 0x2D 0x3A bit 7 and 6 of 0x5F bit 7 of 0x62 bit 7 of 0x2C bit 7, 6, 5 of 0x6F 0x95 0x28 0x29 0x5A bit 7 of 0x5D & 0x5B bit 7 of 0x5E & 0x5C bits [5:0] of 0x5D bits [5:0] of 0x5E bits [5:0] of 0x5F 0x61 0x62 0x63-0x66 0x6E bit 4 of 0x7C & 0x7A bit 6 of 0x7C & 0x7B bits[2:0] of 0x72 & 0x70 bits [6:4] of 0x72 & 0x71 bits [7:5] of 0x6D & 0x6C bits [4:0] 0x6D Value 0x0 0x0 0xe0 0x48 0x0 0x0 0x0 0x0 0x80 0x25 0x1d 0x88 0x86 0xba 0x2a 0x2e 0x2e 0x11 0x45 0x21f07c1f 0x10 0x000 0x101 0x102 0x68c 0x0fa 0x0 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 51 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors Table 21: NTSC Mode (CVBS/YC 27 MHz YUV422 Interface Mode) [ANABEL_AUDIO] Offset 0x01 0x02 Value 0x0 0x0 Table 22: Pal Mode (CVBS/YC 27 MHz YUV422 Interface Mode) [ANABEL_VIDEO] Offset bit 7 of 0x27 bit 7 of 0x54 bit 6 of 0x2D 0x3A bit7and 6 of 0x5F bit 7 of 0x62 bit 7 of 0x2C bit 7, 6, 5 of 0x6F 0x95 0x28 0x29 0x5A bit 7 of 0x5D & 0x5B bit 7 of 0x5E & 0x5C bits [5:0] of 0x5D bits [5:0] of 0x5E bits [5:0] of 0x5F 0x61 0x62 0x63-0x66 0x6E bit 4 of 0x7C & 0x7A bit 6 of 0x7C & 0x7B bits[2:0] of 0x72 & 0x70 bits [6:4] of 0x72 & 0x71 bits [7:5] of 0x6D & 0x6C bits [4:0] 0x6D Value 0x0 0x0 0xe0 0x48 0x0 0x0 0x0 0x0 0x80 0x21 0x1d 0x0 0x7d 0xaf 0x23 0x35 0x35 0x02 0x2f 0x2a098acb 0x20 0x1b 0x130 0x160 0x65a 0x107 0x0 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 52 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip Table 23: Pal Mode (CVBS/YC 27 MHz YUV422 Interface Mode) [ANABEL_AUDIO] Offset 0x01 0x02 Value 0x0 0x0 Table 24: SECAM (CVBS/YC 27 MHz YUV422 Interface Mode) [ANABEL_VIDEO] Offset bit 7 of 0x27 bit 7 of 0x54 bit 6 of 0x2D 0x3A bit 7 and 6 of 0x5F bit 7 of 0x62 bit 7 of 0x2C bit 7, 6, 5 of 0x6F 0x95 0x28 0x29 0x5A bit 7 of 0x5D & 0x5B bit 7 of 0x5E & 0x5C bits [5:0] of 0x5D bits [5:0] of 0x5E bits [5:0] of 0x5F 0x61 0x62 0x63-0x66 0x6E bit 4 of 0x7C & 0x7A bit 6 of 0x7C & 0x7B bits[2:0] of 0x72 & 0x70 bits [6:4] of 0x72 & 0x71 bits [7:5] of 0x6D & 0x6C bits [4:0] 0x6D Value 0x0 0x0 0xe0 0x48 0x0 0x0 0x0 0x0 0x80 0x21 0x1d 0x0 0x6A 0x7f 0x23 0x35 0x35 0x0c 0x2f 0x28a33bb2 0x10 0x1b 0x130 0x160 0x65a 0x107 0x0 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 53 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors Table 25: SECAM (CVBS/YC 27 MHz YUV422 Interface Mode) [ANABEL_AUDIO] Offset 0x01 0x02 Value 0x0 0x0 Table 26: NTSC (RGB 27 MHz YUV422 Interface Mode) [ANABEL_VIDEO] Offset 0x27 0x54 0x2D 0x3A 0x2C 0x6F 0x95 0x28 0x29 0x5A bit 7 of 0x5D & 0x5B bit 7 of 0x5E & 0x5C bits [5:0] of 0x5D bits [5:0] of 0x5E bits [5:0] of 0x5F 0x61 0x62 0x63-0x66 0x6E bit 4 of 0x7C & 0x7A bit 6 of 0x7C & 0x7B bits[2:0] of 0x72 & 0x70 bits [6:4] of 0x72 & 0x71 bits [7:5] of 0x6D & 0x6C bits [4:0] 0x6D Value 0x0 0x0 0x00 0x49 0x0 0x0 0x80 0x1d 0x25 0x88 0x86 0xba 0x2a 0x2e 0x2e 0x11 0x45 0x21f07c1f 0x90 0x000 0x101 0x102 0x68c 0x0fa 0x0 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 54 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip Table 27: NTSC (RGB 27 MHz YUV422 Interface Mode) [ANABEL_AUDIO] Offset 0x01 0x02 Value 0x0 0x0 Table 28: PAL (RGB 27 MHz YUV422 Interface Mode) [ANABEL_VIDEO] Offset 0x27 0x54 0x2D 0x3A 0x2C 0x6F 0x95 0x28 0x29 0x5A bit 7 of 0x5D & 0x5B bit 7 of 0x5E & 0x5C bits [5:0] of 0x5D bits [5:0] of 0x5E bits [5:0] of 0x5F 0x61 0x62 0x63-0x66 0x6E bit 4 of 0x7C & 0x7A bit 6 of 0x7C & 0x7B bits[2:0] of 0x72 & 0x70 bits [6:4] of 0x72 & 0x71 bits [7:5] of 0x6D & 0x6C bits [4:0] 0x6D Value 0x0 0x0 0x00 0x49 0x0 0x0 0x80 0x1d 0x21 0x0 0x7d 0xaf 0x23 0x35 0x35 0x02 0x2f 0x2a098acb 0xa0 0x1b 0x130 0x160 0x65a 0x107 0x0 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 55 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors Table 29: PAL (RGB 27 MHz YUV422 Interface Mode) [ANABEL_AUDIO] Name 0x01 0x02 Value 0x0 0x0 Table 30: 1080i (74.25 MHz Two Interface 422YUV Mode) [ANABEL_VIDEO] Offset 0x80 0x81 0x82 0x82 0x80 0x81 0x82 0x82 0x80 0x81 0x82 0x82 0x80 0x81 0x82 0x82 0x80 0x81 0x82 0x82 0x80 0x81 0x82 0x82 0x80 0x81 0x82 0x82 0x80 0x81 Value 0x05 0x08 0x00 0x01 0x01 0x10 0x01 0x02 0x0e 0x18 0x02 0x03 0x19 0x06 0x03 0x04 0x05 0x18 0x04 0x05 0x01 0x14 0x05 0x06 0x04 0x08 0x06 0x07 0x01 0x0c (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 56 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip Table 30: 1080i (74.25 MHz Two Interface 422YUV Mode) (Cont'd.) [ANABEL_VIDEO] Offset 0x82 0x82 0x80 0x81 0x82 0x82 0x80 0x81 0x82 0x82 0x80 0x81 0x82 0x82 0x80 0x81 0x82 0x82 0x80 0x81 0x82 0x82 0x80 0x81 0x82 0x82 0x80 0x81 0x82 0x82 0x83 0x84 0x85 0x86 0x86 0x83 0x84 0x85 Value 0x07 0x08 0x0f 0x18 0x08 0x09 0x19 0x06 0x09 0x0a 0x05 0x18 0x0a 0x0b 0x00 0x00 0x0b 0x0c 0x00 0x00 0x0c 0x0d 0x00 0x00 0x0d 0x0e 0x00 0x00 0x0e 0x0f 0x1c 0x00 0x00 0x00 0x01 0x14 0x05 0x00 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 57 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors Table 30: 1080i (74.25 MHz Two Interface 422YUV Mode) (Cont'd.) [ANABEL_VIDEO] Offset 0x86 0x86 0x83 0x84 0x85 0x86 0x86 0x83 0x84 0x85 0x86 0x86 0x83 0x84 0x85 0x86 0x86 0x83 0x84 0x85 0x86 0x86 0x83 0x84 0x85 0x86 0x86 0x83 0x84 0x85 0x86 0x86 0x83 0x84 0x85 0x86 0x86 0x83 Value 0x01 0x02 0x14 0x03 0x00 0x02 0x03 0x0c 0x03 0x00 0x03 0x04 0x0c 0x05 0x00 0x04 0x05 0x2c 0x00 0x00 0x05 0x06 0x00 0x00 0x00 0x06 0x07 0x00 0x00 0x00 0x07 0x08 0x00 0x00 0x00 0x08 0x09 0x00 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 58 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip Table 30: 1080i (74.25 MHz Two Interface 422YUV Mode) (Cont'd.) [ANABEL_VIDEO] Offset 0x84 0x85 0x86 0x86 0x83 0x84 0x85 0x86 0x86 0x83 0x84 0x85 0x86 0x86 0x83 0x84 0x85 0x86 0x86 0x83 0x84 0x85 0x86 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8e 0x87 0x88 0x89 0x8a 0x8b Value 0x00 0x00 0x09 0x0a 0x00 0x00 0x00 0x0a 0x0b 0x00 0x00 0x00 0x0b 0x0c 0x00 0x00 0x00 0x0c 0x0d 0x00 0x00 0x00 0x0d 0x0e 0xfb 0xf6 0xae 0x00 0x00 0x00 0x00 0x00 0x01 0xf8 0xf6 0xae 0x00 0x00 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 59 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors Table 30: 1080i (74.25 MHz Two Interface 422YUV Mode) (Cont'd.) [ANABEL_VIDEO] Offset 0x8c 0x8d 0x8e 0x8e 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8e 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8e 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8e 0xbe 0xbf 0xc0 0xc1 0x98 0x98 0xbe Value 0x00 0x00 0x01 0x02 0xbb 0x83 0xfd 0x6e 0xbf 0xef 0x0a 0x02 0x03 0xb9 0x82 0xae 0xb0 0x57 0x00 0x00 0x03 0x04 0xbb 0xc3 0xfe 0xbe 0xbf 0xef 0x0a 0x04 0x05 0x00 0x9c 0x6a 0x2f 0x00 0x01 0x00 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 60 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip Table 30: 1080i (74.25 MHz Two Interface 422YUV Mode) (Cont'd.) [ANABEL_VIDEO] Offset 0xbf 0xc0 0xc1 0x98 0x98 0xbe 0xbf 0xc0 0xc1 0x98 0x98 0xbe 0xbf 0xc0 0xc1 0x98 0x98 0xbe 0xbf 0xc0 0xc1 0x98 0x98 0xbe 0xbf 0xc0 0xc1 0x98 0x98 0xbe 0xbf 0xc0 0xc1 0x98 0x98 0x99 0x9a 0x9c Value 0x9c 0x6a 0x2f 0x01 0x02 0x66 0x64 0x78 0x00 0x02 0x03 0x33 0xd4 0xc0 0x3a 0x03 0x04 0x00 0x00 0x00 0x00 0x04 0x05 0x00 0x00 0x00 0x00 0x05 0x06 0xf6 0x14 0x23 0x30 0x06 0x07 0x03 0x00 0x00 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 61 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors Table 30: 1080i (74.25 MHz Two Interface 422YUV Mode) (Cont'd.) [ANABEL_VIDEO] Offset 0x9b 0x9d 0xae 0xaf 0xb0 0xb1 0xb4 0xb5 0xb2 0xb3 Value 0x02 0x11 0x64 0x04 0x97 0x08 0x15 0x00 0x15 0x00 Table 31: 1080i (74.25 MHz Two Interface 422YUV Mode) [ANABEL_AUDIO] Offset 0x01 0x02 Value 0x0 0x0 Table 32: 720p (74.25 MHz Two Interface 422YUV Mode) [ANABEL_VIDEO] Offset 0x80 0x81 0x82 0x82 0x80 0x81 0x82 0x82 0x80 0x81 0x82 0x82 0x80 0x81 0x82 0x82 0x80 Value 0x05 0x08 0x00 0x01 0x14 0x0c 0x01 0x02 0x68 0x05 0x02 0x03 0x68 0x05 0x03 0x04 0x05 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 62 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip Table 32: 720p (74.25 MHz Two Interface 422YUV Mode) (Cont'd.) [ANABEL_VIDEO] Offset 0x81 0x82 0x82 0x80 0x81 0x82 0x82 0x80 0x81 0x82 0x82 0x80 0x81 0x82 0x82 0x80 0x81 0x82 0x82 0x80 0x81 0x82 0x82 0x83 0x84 0x85 0x86 0x86 0x83 0x84 0x85 0x86 0x86 0x83 0x84 0x85 0x86 0x86 Value 0x0c 0x04 0x05 0x00 0x00 0x05 0x06 0x00 0x00 0x06 0x07 0x00 0x00 0x07 0x08 0x00 0x00 0x08 0x09 0x00 0x00 0x09 0x0a 0x1c 0x00 0x00 0x00 0x01 0x14 0x00 0x00 0x01 0x02 0x2c 0x00 0x00 0x02 0x03 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 63 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors Table 32: 720p (74.25 MHz Two Interface 422YUV Mode) (Cont'd.) [ANABEL_VIDEO] Offset 0x83 0x84 0x85 0x86 0x86 0x83 0x84 0x85 0x86 0x86 0x83 0x84 0x85 0x86 0x86 0x83 0x84 0x85 0x86 0x86 0x83 0x84 0x85 0x86 0x86 0x83 0x84 0x85 0x86 0x86 0x83 0x84 0x85 0x86 0x86 0x83 0x84 0x85 Value 0x00 0x00 0x00 0x03 0x04 0x00 0x00 0x00 0x04 0x05 0x00 0x00 0x00 0x05 0x06 0x00 0x00 0x00 0x06 0x07 0x00 0x00 0x00 0x07 0x08 0x00 0x00 0x00 0x08 0x09 0x00 0x00 0x00 0x09 0x0a 0x00 0x00 0x00 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 64 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip Table 32: 720p (74.25 MHz Two Interface 422YUV Mode) (Cont'd.) [ANABEL_VIDEO] Offset 0x86 0x86 0x83 0x84 0x85 0x86 0x86 0x83 0x84 0x85 0x86 0x86 0x83 0x84 0x85 0x86 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8e 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8e 0x87 0x88 0x89 Value 0x0a 0x0b 0x00 0x00 0x00 0x0b 0x0c 0x00 0x00 0x00 0x0c 0x0d 0x00 0x00 0x00 0x0d 0x0e 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0xa8 0x2c 0x2a 0xbb 0x45 0x00 0x00 0x01 0x02 0x5b 0x09 0xfc 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 65 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors Table 32: 720p (74.25 MHz Two Interface 422YUV Mode) (Cont'd.) [ANABEL_VIDEO] Offset 0x8a 0x8b 0x8c 0x8d 0x8e 0x8e 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8e 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8e 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8e 0x87 0x88 0x89 0x8a 0x8b Value 0x09 0x7f 0x6e 0x11 0x02 0x03 0x79 0x82 0x9e 0xb0 0x45 0x00 0x00 0x03 0x04 0x5b 0xc9 0xfe 0xb9 0x7f 0x6e 0x11 0x04 0x05 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x05 0x06 0x00 0x00 0x00 0x00 0x00 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 66 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip Table 32: 720p (74.25 MHz Two Interface 422YUV Mode) (Cont'd.) [ANABEL_VIDEO] Offset 0x8c 0x8d 0x8e 0x8e 0xbe 0xbf 0xc0 0xc1 0x98 0x98 0xbe 0xbf 0xc0 0xc1 0x98 0x98 0xbe 0xbf 0xc0 0xc1 0x98 0x98 0xbe 0xbf 0xc0 0xc1 0x98 0x98 0xbe 0xbf 0xc0 0xc1 0x98 0x98 0xbe 0xbf 0xc0 0xc1 Value 0x00 0x00 0x06 0x07 0x00 0x00 0x00 0x20 0x00 0x01 0x00 0x00 0x00 0x20 0x01 0x02 0xff 0x00 0x00 0x10 0x02 0x03 0x56 0x00 0x00 0x30 0x03 0x04 0x00 0x00 0x00 0x00 0x04 0x05 0x00 0x00 0x00 0x00 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 67 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors Table 32: 720p (74.25 MHz Two Interface 422YUV Mode) (Cont'd.) [ANABEL_VIDEO] Offset 0x98 0x98 0xbe 0xbf 0xc0 0xc1 0x98 0x98 0x99 0x9a 0x9c 0x9b 0x9d 0xa8 0xa9 0xaa 0xae 0xaf 0xb0 0xb1 0xb4 0xb5 0xb 0xb3 Value 0x05 0x06 0x00 0x00 0x00 0x00 0x06 0x07 0x03 0x00 0x00 0x02 0x11 0x80 0x00 0x00 0xed 0x02 0x71 0x06 0x20 0x70 0x10 0x70 Table 33: 720p (74.25 MHz Two Interface 422YUV Mode) [ANABEL_AUDIO] Offset 0x01 0x02 Value 0x0 0x0 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 68 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip 12. Physical and Electrical Characteristics 12.1 PNX8510/11 Signal Descriptions Table 34: Signal Descriptions (by Pin No.) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Name AVDDA1 AVSS1 TRST RESETN SUB SUB AVDDD BONDDOWN TDI TDO TCK TMS VSS VDD I2S_IN2_SCK I2S_IN2_WS I2S_IN2_SD BONDDOWN I2S_AOS2_CLK I2S_IN1_SCK I2S_IN1_WS I2S_IN1_SD I2S_AOS1_CLK VSSI VDDI I2C_SDA I2C_SCL VSYNC_IN HSYNC_IN BLANK_IN VSSE1 VSYNC_OUT HSYNC_OUT VDDE VSS Audio DAC analog supply Audio DAC analog ground JTAG reset Chip reset in signal (low active) Audio digital ground Audio digital ground Audio DAC digital supply Digital ground JTAG controller test data input JTAG controller test data output JTAG controller test clock input Description JTAG controller test mode select input Digital ground Digital supply Bit clock IO for secondary audio channel Word select IO for secondary audio channel Serial data in for secondary audio channel Digital ground Oversampling clock input for secondary audio channel Bit clock IO for primary audio channel Word select IO for primary audio channel Serial data in for primary audio channel Oversampling clock input for primary audio channel Digital ground Digital supply I2C data line (bi-directional) I2C clock line (input) Vertical sync input for primary video interface Horizontal sync input for primary video interface Blanking input signal for primary video pipeline Digital ground Vertical sync output for primary video pipeline Horizontal sync output for primary video pipeline Digital supply Digital ground 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 69 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors Table 34: Signal Descriptions (by Pin No.) (Cont'd.) Pin No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 VDD VAVDD2_2 VOUT5 IDUMP2 VOUT6 RSET2 VAVSS2 VAVDD2_1 VOUT1 VAVDD1 VOUT4 VOUT3 IDUMP1 VOUT2 VAVDD1 RSET1 VREF1 VAVSS1 VSS VDD DV_CLK1 DV9_IN1 DV8_IN1 DV7_IN1 DV6_IN1 DV5_IN1 DV4_IN1 DV3_IN1 DV2_IN1 DV1_IN1 DV0_IN1 VSS VDD DV_CLK2 DV9_IN2 DV8_IN2 DV7_IN2 DV6_IN2 DV5_IN2 Name Digital supply Analog supply for video DACs Description Video output for secondary channel, Y/CVBS-DAC Current return path for C-DAC and CVBS/Y-DAC Video output for secondary channel, C-DAC Current setting resistor for secondary channel DACs Analog ground for video DACs Analog supply for video DACs Video output for primary video DAC 1 (CVBS/Y) Analog supply for video DACs Video output for primary video DAC 4 (Blue) Video output for primary video DAC 3 (Y/Green) Current return path for all primary channel DACs Video output for primary video DAC 2 (C/Red) Analog supply for video DACs Current setting resistor for primary channel DACs No connection (leave floating) Analog ground for video DACs Digital ground Digital supply Primary video interface clock Primary video D1 input Primary video D1 input Primary video D1 input Primary video D1 input Primary video D1 input Primary video D1 input Primary video D1 input Primary video D1 input Primary video D1 input Primary video D1 input Digital ground Digital supply Secondary video interface clock Secondary video D1 input Secondary video D1 input Secondary video D1 input Secondary video D1 input Secondary video D1 input (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 70 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip Table 34: Signal Descriptions (by Pin No.) (Cont'd.) Pin No. 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Name DV4_IN2 DV3_IN2 DV2_IN2 DV1_IN2 DV0_IN2 VSSI VDDI VSS VDD GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] AVSS2 AVDDA2 AOUT_R2 AVSSA2 AVREF2 AVDDO2 AOUT_L2 AOUT_R1 AVREF1 AVDDO1 AVSSA1 AOUT_L1 Secondary video D1 input Secondary video D1 input Secondary video D1 input Secondary video D1 input Secondary video D1 input Digital ground Digital supply Digital ground Digital supply General purpose input/output General purpose input/output General purpose input/output General purpose input/output General purpose input/output Audio DAC output buffer supply Audio DAC supply Description Audio output for right secondary audio channel Audio DAC ground Audio DAC reference Audio DAC output buffer supply Audio output for left secondary audio channel Audio output for right primary audio channel Audio DAC reference Audio DAC output buffer supply Audio DAC ground Audio output for left primary audio channel 12.2 Electrical Characteristics Range: VDD = 3.0 to 3.6 V; Tamb = 0 to +70C Note: For Table 35, VDD = 3.3; Tamb = 25C, unless otherwise stated. Table 35: Electrical Specifications Symbol Power Consumption SD1 Half HD1 Full HD1 Supply Parameter Conditions Min Typical Max Unit RGB/Y-C YPrPb YPrPb 1.02 1.09 1.58 1.15 1.26 1.97 W W W VAVDD Digital supply audio 3.0 3.3 3.6 V 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 71 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors Table 35: Electrical Specifications (Cont'd.) Symbol VDVDD AVDDD AVDDA Inputs Parameter Digital supply video Analog supply video Analog supply audio Conditions Min 3.0 3.15 3.15 Typical 3.3 3.3 3.3 Max 3.6 3.45 3.45 Unit V V V VIL VIH ILI Ci Low level input voltage High level input voltage Input leakage current Input capacitance clocks data I/Os at high impedance -0.5 2.0 - +0.8 VDD+0.3 1 10 8 8 V V uA pF pF pF Outputs VOL VOH I2S bus; SDA, SCL VIL VIH Ii VOL Io Input Timing Low level output voltage High level input voltage IOL=2mA IOH=2mA 2.4 0.4 - V V Low level output voltage High level input voltage Input current Low level output voltage (SDA) Output current Vi=low or high Iol=3mA during ACK -0.5 0.7 -10 3 +0.3 VDD+0.3 +10 0.4 - V V mA V mA tsu thd Input data setup time Input data hold time TBD TBD ns ns Data and Reference Signal Output Timing CL th td Audio DAC Outputs Output load cap. Output hold time Output delay TBD TBD TBD pf ns TBD ns Vout Vcom Rload Rout, Vref (THD+N)/S Full scale output voltage2 Common mode output voltage3 Load resistance Equivalent AC resistance seen at VREF terminal (THD+N)/S @ 0dB, 1 kHz (THD+N)/S @ -60dB, 1 kHz 4 1.0 1.65 Vrms V k 25 -90 -40 90 95 k dB dB(A) dB(A) dB(A) S/N SNR at digital silence SNR at digital silence (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 72 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip Table 35: Electrical Specifications (Cont'd.) Symbol DC Offset Characteristics Parameter Conditions Min Typical Max Unit Voffset Video DAC Outputs DC-offset compensation -43 mV INL DN Integral nonlinearity Static 0.6 0.5 2.3 2.3 200 lsb lsb ns ns MHz Output rise time Output fall time Clock frequency Iout Vref Output load Detection threshold (comparator) Operating to sleep delay Operating to power down delay Sleep to power down delay Sleep to operating Power delay Power down to operating delay Power down to sleep delay Output current programming Load 37.5 //15pF Load 37.5 //15pF See Section 12.3 for application information. 1.23 0.35 100 200 200 200 200 200 200 200 V V ns ns ns ns ns ns ns ns Notes: 1 Requires proper assembly of package to heat spreader. See Figure 29 Footprint for heat spreader requirements and Section 14.4 for soldering and footprint requirements. 2 Full scale output voltage is directly proportional to DC voltage at VREF pin (VDDA/2) and maximum digital signal level at low frequencies. Relation: Vout(rms) = * 1.645 * vref/1.41, = maximum digital input level at low frequencies. 3 Common mode output voltage equals VREF=VDDA/2/. 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 73 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors 12.3 Application Information p-dac vdda vref 1 :7 : 12 Rconv lout vout vref 12 Rconv vref 1.41 Rreg Rref 7: 12 vout(rms) = : max. dig. i/p level v6.0: Rconv = 247 vssa vss n-dac Rref = 18000 : -5.67dB = 0.521 => vout(rms) = 0.607 * vref Figure 25: Simplified Schematic of Audio DAC From the simplified schematic of the DAC in Figure 25 it can be seen that the output voltage swing depends upon: * * * * the maximum digital input level at low frequencies () the reference voltage vref (nominal VDDA/2) the current mirror gain (ideally 12) the ratio of the I/V conversion resistance (Rconv) and the reference resistance (Rref) Vout(rms) = 12 /2 Rconv/Rref Vref The reference resistor is dimensioned to be 18k. Since the reference voltage Vref is nominally half the supply voltage, the I/V conversion resistor must be dimensioned by: Rconv = Vout(rms)/Vref 2/(12 ) Rref For an rms output voltage of 1000mVrms, a reference voltage of 1.65V, a reference resistance of 18 k and a maximum digital input level of 0.521 (-5.67dB), the I/V conversion resistor should be 2470 . This relationship is: (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 74 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip Figure 26 shows the circuitry for the reconstruction filter of the video D/A converters. C40 120 PF L3 CVBS2 1 1 RV5 75 2 2.7 UH L4 2.7 UH 2 J6 RCA JACK 1 CV3 390 PF 2 2 1 CV4 560 PF C41 120 PF L5 LUMA1 1 2.7 UH 1 L6 2.7 UH LUMA1_OUT J7 S-Video 3 1 1 RV6 75 2 2 CV5 390 PF C42 120 PF 2 CV6 560 PF CHROMA1_OUT 4 2 L8 2.7 UH L7 VOUT6 1 1 RV7 75 2 2 2.7 UH 1 CV7 390 PF 2 CV8 560 PF Figure 26: DAC Reconstruction Filter Circuitry 12.3.1 Video DACs of Primary and Secondary Video Channels The video DACs used in both the primary and secondary video channels employ segmented current mode architecture. The programming feature of DACs is valid for both the primary and secondary video channels. The primary video channel has in its path four DACs: R, G, B and CVBS. The programming option "Fine Adjust" -- via the common four bits of I2C [3:0] -- can simultaneously adjust the central output level of all four DACs in a range of 7% in 1% increments. Please note the four bits are signed values. The following table shows the programming values. Table 36: Common I2C Bits for all DACs (Output Level: Fine Adjustment in 1% Increments) B03 0 0 0 0 9397 750 08865 B02 0 0 0 0 B01 0 0 1 1 B00 0 1 0 1 Vout 0% +1% +2% +3% (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 7 6 5 75 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors Table 36: Common I2C Bits for all DACs (Output Level: Fine Adjustment in 1% Increments) B03 0 0 0 0 1 1 1 1 1 1 1 1 B02 1 1 1 1 0 0 0 0 1 1 1 1 B01 0 0 1 1 0 0 1 1 0 0 1 1 B00 0 1 0 1 0 1 0 1 0 1 0 1 Vout +4% +5% +6% +7% 0% -1% -2% -3% -4% -5% -6% -7% The programming option "Coarse Adjust" uses five separate bits [14:10] of I2C to independently adjust the output level of each R, G, B and CVBS DAC between 0.58V and 1.23V (in increments of 21mV, assuming an effective load of 75 // 75 = 37.5 ). Note that these five bits are not signed. Table 37: Separate I2C Bits 31x21mV (Output Level: Coarse Adjustment for each DAC) Bit Values 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Vout 0% +3.6% +7.2% +10.7% +14.3% +17.9% +21.5% +25.0% +28.6% +32.2% +35.8% +39.4% +42.9% +46.5% +50.1% +53.7% +57.3% +60.8% +64.4% +68% +71.6% (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 76 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip Table 37: Separate I2C Bits 31x21mV (Output Level: Coarse Adjustment for each DAC) Bit Values 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 Vout +75.1% +78.7% +82.3% +85.9% +89.5% +93.0% +96.6% +100.2% +103.8% +107.4% +110.9% Programming Examples Assuming an effective load of 75 // 75 = 37.5 , Rset = 1k, the coarse bits are set to 0 0 0 0 and the fine adjust bits are set to 0 0 0 0 0. The output will be sitting at the minimum level of Vout = 0.579V. For example, if Vout is set to 1 V, then the fine adjust bits should be set to 0 0 0 0 0 and the coarse adjust bits set to 1 0 1 0 0. Sleep and Powerdown Modes * Sleep mode occurs when all current output switches are disabled asynchronously so that no current flows in either Iout or Idump pins i.e., IOUT = IDUMP = 0. Sleep mode allows a rapid recovery from a low power consumption state. Each DAC can be put into sleep mode asynchronously where IOUT = IDUMP = 0, yet still supply current flows to power the bandgap, opmap, and other analog DAC components, including the digital logic. Powerdown mode occurs when each DAC can be asynchronously put into zero state current so that all current output switches are disabled. This includes current to all analog and digital components of the DAC such as bandgap reference, opmaps, etc. In this mode IDDD = IDDA = 0. * 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 77 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors 10-bit current DAC with programmable output level adjustments of fine and coarse M = +/-7 fine 4-bit adjust N = 0..31 5-bit coarse adjust D = 0..1023 digital 10-bit inputs IOUT DAC 10 IDUMP IRef RSet VSSA central fine adjust for both DACs IOUT = separate output level coarse adjust for each DAC RDUMP = 0.1 or 2 ohm RL = RO/2 RO = 2x75 Ohm VSSA 6 ICOMP1 pcomp pcomp COMP VSSA VBG = 1.22V RSetnom = 1 kOhm for RL = 37.5 Ohm (double termination) RSetmax = 2 kOhm for RL = 75 Ohm ICOMPn = reference currents for up to 6 DACs IOUT + IDUMP = 1023I1 = constant IDUMP = (1023 - D) I1 VDUMP = IOUT x RL M 28 + N ae VBG x 16.4 o x 1 + ae 100 + M o --------- x ------------------ x D ------------ ----------------------------e RS e 100 o 100 100 o 23 x 16 i i i i i i i i i i i i i i i i i i i i i i i i i I1 = LSB current IOUT = I1 x D VOUT = IOUT x RL VOUTmin = 15.57 mA x 37.5 Ohm = 0.584 V (full-scale, fine adjust = 0%) VOUTmax = 32.80 mA x 37.5 Ohm = 1230 V (full-scale, fine adjust = 0%) Figure 27: Video Channel DAC Programming Figure 27 provides an example for calculating the RSet for the video DACs from given output voltage and termination. (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 78 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip 13. Package Description Figure 28 illustrates the 100-pin HTQFP package showing the dimensions in millimeters HTQFP100: plastic, heatsink thin quad flat package; 100 leads; body 14 x 14 x 1.0 mm SOT638-1 c y heatsink side X Dh 75 76 51 50 Z E A e E HE wM b pin 1 index detail X p Lp L Eh A A 2A 1 (A 3) 100 1 b wM p D H D ZD 25 26 e vM A B vM B 0 scale DIMENSIONS (mm are the original dimensions) A UNIT max. mm 1.2 A1 0.15 0.05 A2 1.05 0.95 A3 0.25 bp 0.27 0.17 c 0.20 0.09 (1) D 14.1 13.9 Dh 7.1 6.1 E (1) 14.1 13.9 Eh 7.1 6.1 e 0.5 HD 10 mm HE L 1.0 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 Z D(1) Z E(1) 1.15 0.85 1.15 0.85 7 0 16.15 16.15 15.85 15.85 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT638-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 01-03-30 Figure 28: Package Diagram 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 79 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors 14. Soldering 14.1 Introduction to Soldering Surface-Mount Packages The following information provides a very brief insight into a complex technology. A more indepth account of soldering ICs can be found in the Philips' Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface-mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. For the PNX8510/11 only reflow soldering is suitable. 14.2 Reflow Soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferably be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. 14.3 Manual Soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 14.4 Footprint For good thermal behavior of the PNX8510/11 in the application, the exposed pad needs to be soldered to the motherboard. Figure 29 shows the recommended footprint and solderpaste placement. A matrix of solderpaste dots has to be placed on a copper square. For optimal heat dissipation through the motherboard, the recommendation is to connect the copper square with vias to the inner-ground plane of the application board. (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 80 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip Figure 29: Footprint 9397 750 08865 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 81 of 84 PNX8510/11 Analog Companion Chip Philips Semiconductors 15. Ordering Information Package Type Number 12NC 9352 695 80557 9352 695 76557 Name HTQFP100 HTQFP100 Version SOT638-1 SOT638-1 PNX8510HW/B1 PNX8511HW/B1 16. Rev 02 Revision History Date 20010924 Table 38: Revision History CPCN 853-2300 27221 Description Upgraded to product data. Supersedes initial version of 27 August 2001 (9397 750 08495). Modifications: * The format of this document has been redesigned to comply with Philips Semiconductors' new presentation and information standard. Preliminary release posted on BHS (DVI) Intranet web site 01 20010827 17. Data Sheet Status Product Status2 Development Data Sheet Status1 Objective data Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNWSQ-650A. Preliminary data Qualification Product data Production 1. 2. Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 18. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. 9397 750 08865 82 of 84 Rev. 02 -- 8 October 2001 Product data Philips Semiconductors PNX8510/11 Analog Companion Chip device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 19. Disclaimers Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 20. Licenses Purchase of Philips I2C components Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. Contact Information For additional information, please visit http://www.semiconductors.philips.com For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com. 9397 750 08865 Fax: +31 40 27 24825 (c) Koninklijke Philips Electronics N.V. Copyright 2001. All rights reserved. Product data Rev. 02 -- 8 October 2001 83 of 84 Philips Semiconductors PNX8510/11 Analog Companion Chip Contents 1. 1.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 12. 12.1 12.2 12.3 12.3.1 Physical and Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 1-69 2. 2.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.2.7 Video Pipeline . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Video Input Modes . . . . . . . . . . . . . . . . . . . . . 1-6 YUV 4:2:2 . . . . . . . . . . . . . . . . . . . . . . . . . . . RGB 4:4:4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . YUV 4:4:4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . YUV 4:2:2 Interleaved . . . . . . . . . . . . . . . . . . RGB 4:4:4 Interleaved . . . . . . . . . . . . . . . . . . YUV 4:4:4 Interleaved . . . . . . . . . . . . . . . . . . YUV 4:2:2 HD Two Channel Format. . . . . . . . Video Input Module . . . . . . . . . . . . . . . . . . . . 1-6 1-6 1-6 1-7 1-7 1-7 1-8 1-8 PNX8810/11 Signal Descriptions . . . . . . . 1-69 Electrical Characteristics. . . . . . . . . . . . . . . 1-71 Application Information . . . . . . . . . . . . . . . . 1-74 Video DACs of Primary and Secondary Video Channels . . . . . . . . . . . . . . . . . . . . . . 1-75 13. 14. 14.1 14.2 14.3 14.4 Package Description . . . . . . . . . . . . . . . . 1-79 1-80 1-80 1-80 1-80 1-80 1-82 1-82 1-82 1-82 1-83 1-83 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to Soldering Surface-Mount Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reflow Soldering . . . . . . . . . . . . . . . . . . . . . Manual Soldering . . . . . . . . . . . . . . . . . . . . . Footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 2.4 2.5 2.6 2.6.1 2.6.2 2.6.3 2.6.4 Video DAC Control . . . . . . . . . . . . . . . . . . . . . 1-9 VBI Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 PAL/NTSC/SECAM Encoder . . . . . . . . . . . 1-13 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Luminance and Chrominance Processing . . Sync Generator . . . . . . . . . . . . . . . . . . . . . . Macrovision . . . . . . . . . . . . . . . . . . . . . . . . . HD Data Path . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1-14 1-14 1-15 1-15 15. 16. 17. 18. 19. 20. Ordering Information . . . . . . . . . . . . . . . . Revision History. . . . . . . . . . . . . . . . . . . . . Data Sheet Status. . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 2.8 2.9 HD-Sync Generator Module . . . . . . . . . . . . 1-15 Limitations of the Video Pipe . . . . . . . . . . . 1-21 3. 3.1 3.1.1 Audio Pipeline . . . . . . . . . . . . . . . . . . . . . . . 1-22 Audio Interface Operation . . . . . . . . . . . . . . 1-22 Audio Input Timing . . . . . . . . . . . . . . . . . . . . 1-23 3.2 Mute Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 4. 5. 5.1 5.2 Programming Interface . . . . . . . . . . . . . . 1-24 GPIO Block Functional Description . 1-25 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 6. 6.1 6.2 Clock Module . . . . . . . . . . . . . . . . . . . . . . . . 1-27 Clocks Video Submodule . . . . . . . . . . . . . . 1-28 Clocks Audio Submodule . . . . . . . . . . . . . . 1-28 7. 8. 9. 10. 11. Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Descriptions Video Address Space . . . . . . . . . . . . . . . . Audio/Clock Address Space . . . . . . . . . Video Programming Examples 1-28 . . . . . . . . . . . . . . . 1-29 1-33 1-48 . . . . . . 1-51 (c) Koninklijke Philips Electronics N.V. 2001. Printed in the U.S.A All rights are reserved. Reproduction in whole omr in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: Rev. 02 -- 8 October 2001 Document order number: 9397 750 08865 |
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