View UT6264_278058.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

UTRON
Rev. 1.4
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
REVISION HISTORY
REVISION Preliminary Rev. 0.1 Rev. 1.0 Rev. 1.1 DESCRIPTION Original. Revised - The timeing waveforms add CE2 control pin Revised - Package outline dimension - Waveform. Revised - Improve IDR from 20A to 10A (LL-version , max.) - 28-pin PDIP package outline dimension 1. Add Extended temperature : -20J ~85J 2. Revised Operating : 45/30 mA (typ.) 40/30 mA (typ.) 3. Revised CMOS Standby : 2 0.3mA (typ.) normal 4. Revised DC characteristics : a. Icc(-35) : 45 40mA (typ.), 60 50 mA (max) b. Icc(-70) : 45 40mA (max.) c. Icc1(Tcycle=1us)= 10mA(max.) d. Icc2(Tcycle=500ns)=20mA(max.) 5. Revised "Order information" : add Extended parts Add order information for lead free product Date May 3 ,2001 Jun.4,2001 Jan 15,2002
Rev. 1.2
May 14,2002
Rev. 1.3
Jul 30,2002
Rev. 1.4
May 15,2003
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80028
1
UTRON
Rev. 1.4
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM GENERAL DESCRIPTION
The UT6264C is a 65,536-bit low power CMOS static random access memory organized as 8,192 words by 8 bits. It is fabricated using high performance, high reliability CMOS technology. Easy memory expansion is provided by using two chip enable input.( CE ,CE2) ,and supports low data retention voltage for battery back-up operation with low data retention current. The UT6264C operates from a single 4.5V~5.5V power supply and all inputs and outputs are fully TTL compatible.
FEATURES
Access time : 35/70ns (max.) Low power consumption : Operating : 40/30 mA (typ.) CMOS Standby : 0.3mA (typ.) normal 2 A (typ.) L-version 1 A (typ.) LL-version Single 4.5V~5.5V power supply Operating temperature : Commercial : 0J ~70J Extended : -20J ~85J All inputs and outputs TTL compatible Fully static operation Three state outputs Data retention voltage : 2V (min.) Package : 28-pin 600 mil PDIP 28-pin 330 mil SOP
PIN CONFIGURATION
NC A12 A7 1 2 3 4 28 27 26 25 Vcc
WE
FUNCTIONAL BLOCK DIAGRAM
A0-A12 DECODER 8K X 8 MEMORY ARRAY
CE2 A8 A9 A11
OE
A6 A5 A4 A3 A2 A1 A0
UT6264C
5 6 7 8 9 10 11 12 13 14
24 23 22 21 20 19 18 17 16 15
Vcc Vss
A10
CE
I/O8 I/O7 I/O6 I/O5 I/O4
I/O1-I/O8
I/O DATA CIRCUIT
COLUMN I/O
I/O1 I/O2 I/O3 Vss
PDIP/SOP
CE CE2
OE
PIN DESCRIPTION
CONTROL CIRCUIT
WE
SYMBOL A0 - A12 I/O1 - I/O8 CE ,CE2 WE OE VCC VSS NC
DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Inputs Write Enable Input Output Enable Input Power Supply Ground No connection
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80028
2
UTRON
Rev. 1.4
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
SYMBOL VTERM TA TA TSTG PD IOUT Tsolder RATING -0.5 to 7.0 0 to 70 -20 to 85 -65 to 150 1 50 260 UNIT V J J J W mA J
ABSOLUTE MAXIMUM RATINGS*
PARAMETER Terminal Voltage with Respect to VSS Operating Temperature Commercial Extended Storage Temperature Power Dissipation DC Output Current Soldering Temperature (under 10 sec)
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE Standby Standby Output Disable Read Write CE H X L L L CE2 X L H H H
OE X X H L X
WE X X H H L
I/O OPERATION High - Z High - Z High - Z DOUT DIN
SUPPLY CURRENT ISB, ISB1 ISB, ISB1 Icc,Icc1,Icc2 Icc,Icc1,Icc2 Icc,Icc1,Icc2
note: H = VIH, L=VIL, X = Don't care.
DC ELECTRICAL CHARACTERISTICS (VCC = 4.5V~5.5V, TA = 0J to 70J/ -20J to 85J (E))
SYMBOL TEST CONDITION MIN. TYP. MAX. 1 VIH 2.2 VCC+0.5 2 VIL - 0.5 0.8 O VIN O VCC -1 1 ILI VSS VSS O VI/OO VCC; CE =VIH;or CE2=VIL; Output Leakage Current ILO -1 1 or OE = VIH ;or WE = VIL Output High Voltage VOH IOH = -1mA 2.4 Output Low Voltage VOL IOL = 4mA 0.4 - 35 40 50 CE = VIL , ICC - 70 30 40 II/O = 0mA ,Cycle=Min. Operating Power Tcycle 10 CE = 0.2V; II/O = 0mA; Icc1 Supply Current =1s CE2=Vcc-0.2V; 20 other pins at 0.2V or VCC-0.2V Tcycle Icc2 =500ns normal ISB 1 10 CE =VIH or CE2= VIL 0.3 5 ISB1 CE U VCC-0.2V or CE2O 0.2V Standby Power ISB -L/-LL 3 CE =VIH or CE2= VIL Supply Current ISB1 -L 2 100 CE U VCC-0.2V or CE2O 0.2V -LL 1 50 Notes: 1. Overshoot : Vcc+2.0v for pulse width less than 10ns. 2. Undershoot : Vss-2.0v for pulse width less than 10ns. 3. Overshoot and Undershoot are sampled, not 100% tested.
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
PARAMETER Input High Voltage Input Low Voltage Input Leakage Current
UNIT V V A A V V mA mA mA mA mA mA mA A A
P80028
3
UTRON
Rev. 1.4
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
CAPACITANCE (TA=25J , f=1.0MHz)
PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN.
-
MAX 8 10
UNIT pF pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0V to 3.0V 5ns 1.5V CL = 100pF, IOH/IOL = -1mA/4mA
AC ELECTRICAL CHARACTERISTICS (VCC = 4.5V~5.5V, TA = 0J to 70J/ -20J to 85J (E))
(1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write-Time Output Active from End of Write Write to Output in High-Z SYMBOL UT6264C-35
MIN. MAX.
SYMBOL
UT6264C-35
MIN. MAX.
UT6264C-70
MIN. MAX.
UNIT
tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH
35 10 5 5
35 35 25 25 25 -
70 10 5 5
70 70 35 35 35 -
ns ns ns ns ns ns ns ns ns
UT6264C-70
MIN. MAX.
UNIT
tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ*
35 30 30 0 25 0 20 0 5 -
15
70 60 60 0 50 0 30 0 5 -
25
ns ns ns ns ns ns ns ns ns ns
*These parameters are guaranteed by device characterization, but not production tested.
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80028
4
UTRON
Rev. 1.4
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled)
(1,2)
tRC
Address
tAA tOH
Dout Previous data valid Data Valid
tOH
READ CYCLE 2 ( CE and CE2 and OE Controlled) (1,3,4,5)
tRC
Address
tAA
CE
tACE
CE2
OE
tOE tCLZ tOLZ
Dout High-Z Data Valid
tCHZ tOHZ tOH
High-Z
Notes : 1. WE is high for read cycle. 2.Device is continuously selected OE =low, CE =low, CE2=high. 3.Address must be valid prior to or coincident with CE =low, CE2=high; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL=5pF. Transition is measuredO 500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80028
5
UTRON
Rev. 1.4 WRITE CYCLE 1 ( WE Controlled) (1,2,3,5,6)
tW C
A ddress
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
tAW
CE
tCW
CE2
tAS
WE
tW P
tW R
tW H Z
D out (4)
H igh-Z
tOW
(4)
tDW
D in
tDH
D ata V alid
WRITE CYCLE 2 ( CE and CE2 Controlled) (1,2,5,6)
tW C
A d d re s s
tAW
CE
tAS tCW
tW R
CE2
tW P
WE
tW H Z
Dout D in (4 ) H ig h -Z
tDW
D a ta V a lid
tDH
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80028
6
UTRON
Rev. 1.4
Notes : 1. WE , CE must be high or CE2 must be low during all address transitions. 2.A write occurs during the overlap of a low CE , high CE2, low WE .
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
3. During a WE controlled write cycle with OE low, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5. If the CE low transition and CE2 high transition occurs simultaneously with or after WE low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured O 500mV from steady state.
DATA RETENTION CHARACTERISTICS (TA = 0J to 70J/ -20J to 85J (E))
PARAMETER Vcc for Data Retention Data Retention Current Chip Disable to Data Retention Time Recovery Time
tRC* = Read Cycle Time
SYMBOL TEST CONDITION VDR CE U VCC-0.2V or CE2 0.2V Vcc=2V IDR CE U VCC-0.2V or CE2 0.2V tCDR tR See Data RetentionWaveforms (below)
-L -LL
MIN. 2.0 0 tRC*
TYP. 1 0.5 -
MAX. 5.5 50 10 -
UNIT V A A ns ns
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1) ( CE controlled)
VDR U VCC Vcc(min.)
2V Vcc(min.)
tCDR
CE U VCC-0.2V
tR
CE
VIH
VIH
Low Vcc Data Retention Waveform (2) (CE2 controlled)
VDR U VCC VCC(min.)
2V VCC(min.)
tCDR
CE2 VIL CE2 O 0.2V
tR
VIL
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80028
7
UTRON
Rev. 1.4
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
PACKAGE OUTLINE DIMENSION
28 pin ( 600mil ) PDIP Package Outline Dimension
UNIT SYMBOL A1 A2 B c D E e eB L K
INCH(BASE) 0.010 (MIN) 0.150 O 0.01 0.018 O 0.005 0.010 O 0.004 1.460 O 0.005 0.600 O 0.010 0.100 (TYP) 0.640O 0.03 0.130 O 0.010 o o 0 a 15
MM(REF) 0.254 (MIN) 3.810 O 0.254 0.457 O 0.127 0.254 O 0.102 37.084 O 0.127 15.240 O 0.254 2.540 (TYP) 16.256 O 0.762 3.302 O 0.254 o o 0 a 15
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80028
8
UTRON
Rev. 1.4 28 pin 330 mil SOP Package Outline Dimension
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
SYMBOL
UNIT
INCH(BASE) 0.112(max) 0.004(MIN) 0.0980.005 0.016(TYP) 0.010(TYP) 0.7130.005 0.3310.005 0.4650.012 0.050(TYP) 0.04040.008 0.0670.008 0.047(MAX) 0.003(MAX) 0~10
MM(REF) 2.845(max) 0.102(MIN) 2.4890.127 0.406(TYP) 0.254(TYP) 18.1100.127 8.4070.127 11.8110.305 1.270(TYP) 1.02550.203 1.7020.203 1.194(MAX) 0.076(MAX) 0~10
A A1 A2 b c D E E1 e L L1 S y
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80028
9
UTRON
Rev. 1.4
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
ORDERING INFORMATION Commerical temperature
PART NO. UT6264CPC-35 UT6264CPC-35L UT6264CPC-35LL UT6264CPC-70 UT6264CPC-70L UT6264CPC-70LL UT6264CSC-35 UT6264CSC-35L UT6264CSC-35LL UT6264CSC-70 UT6264CSC-70L UT6264CSC-70LL ACCESS TIME (ns) 35 35 35 70 70 70 35 35 35 70 70 70 STANDBY CURRENT (A) (TYP.) 0.3mA 2 A 1 A 0.3mA 2 A 1 A 0.3mA 2 A 1 A 0.3mA 2 A 1 A PACKAGE 28 PIN PDIP 28 PIN PDIP 28 PIN PDIP 28 PIN PDIP 28 PIN PDIP 28 PIN PDIP 28 PIN SOP 28 PIN SOP 28 PIN SOP 28 PIN SOP 28 PIN SOP 28 PIN SOP
Extended temperature
PART NO. UT6264CPC-35E UT6264CPC-35LE UT6264CPC-35LLE UT6264CPC-70E UT6264CPC-70LE UT6264CPC-70LLE UT6264CSC-35E UT6264CSC-35LE UT6264CSC-35LLE UT6264CSC-70E UT6264CSC-70LE UT6264CSC-70LLE ACCESS TIME (ns) 35 35 35 70 70 70 35 35 35 70 70 70 STANDBY CURRENT (A) (TYP.) 0.3mA 2 A 1 A 0.3mA 2 A 1 A 0.3mA 2 A 1 A 0.3mA 2 A 1 A PACKAGE 28 PIN PDIP 28 PIN PDIP 28 PIN PDIP 28 PIN PDIP 28 PIN PDIP 28 PIN PDIP 28 PIN SOP 28 PIN SOP 28 PIN SOP 28 PIN SOP 28 PIN SOP 28 PIN SOP
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80028
10
UTRON
Rev. 1.4
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
ORDERING INFORMATION (for lead free product) Commerical temperature
PART NO. UT6264CPCL-35 UT6264CPCL-35L UT6264CPCL-35LL UT6264CPCL-70 UT6264CPCL-70L UT6264CPCL-70LL UT6264CSCL-35 UT6264CSCL-35L UT6264CSCL-35LL UT6264CSCL-70 UT6264CSCL-70L UT6264CSCL-70LL ACCESS TIME (ns) 35 35 35 70 70 70 35 35 35 70 70 70 STANDBY CURRENT (A) (TYP.) 0.3mA 2 A 1 A 0.3mA 2 A 1 A 0.3mA 2 A 1 A 0.3mA 2 A 1 A PACKAGE 28 PIN PDIP 28 PIN PDIP 28 PIN PDIP 28 PIN PDIP 28 PIN PDIP 28 PIN PDIP 28 PIN SOP 28 PIN SOP 28 PIN SOP 28 PIN SOP 28 PIN SOP 28 PIN SOP
Extended temperature
PART NO. UT6264CPCL-35E UT6264CPCL-35LE UT6264CPCL-35LLE UT6264CPCL-70E UT6264CPCL-70LE UT6264CPCL-70LLE UT6264CSCL-35E UT6264CSCL-35LE UT6264CSCL-35LLE UT6264CSCL-70E UT6264CSCL-70LE UT6264CSCL-70LLE ACCESS TIME (ns) 35 35 35 70 70 70 35 35 35 70 70 70 STANDBY CURRENT (A) (TYP.) 0.3mA 2 A 1 A 0.3mA 2A 1 A 0.3mA 2A 1 A 0.3mA 2A 1 A PACKAGE 28 PIN PDIP 28 PIN PDIP 28 PIN PDIP 28 PIN PDIP 28 PIN PDIP 28 PIN PDIP 28 PIN SOP 28 PIN SOP 28 PIN SOP 28 PIN SOP 28 PIN SOP 28 PIN SOP
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80028
11
UTRON
Rev. 1.4
UT6264C
8K X 8 BIT LOW POWER CMOS SRAM
THIS PAGE IS LEFT BLANK INTENTIONALLY.
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80028
12

▲Up To Search▲

Price & Availability of UT6264

	To Download UT6264 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .