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| PRELIMINARY DATA SHEET MICRONAS VPC 3205C, VPC 3215C Video Processor Family Edition Oct. 19, 1998 6251-457-2PD MICRONAS VPC 3205C, VPC 3215C Contents Page 4 4 4 5 6 6 6 6 6 6 6 6 7 7 8 8 8 9 9 9 9 10 10 11 11 11 11 12 12 12 12 12 12 12 13 13 13 15 17 17 17 29 29 Section 1. 1.1. 1.2. 1.3. 2. 2.1. 2.1.1. 2.1.2. 2.1.3. 2.1.4. 2.1.5. 2.1.6. 2.2. 2.3. 2.3.1. 2.3.2. 2.3.3. 2.3.4. 2.3.5. 2.3.6. 2.3.7. 2.3.8. 2.3.9. 2.4. 2.5. 2.6. 2.6.1. 2.6.2. 2.6.3. 2.6.4. 2.6.5. 2.6.6. 2.6.7. 2.6.8. 2.6.9. 2.7. 2.7.1. 2.8. 3. 3.1. 3.2. 3.2.1. 3.2.2. Title Introduction System Architecture Video Processor Family VPC Applications Functional Description Analog Front-End Input Selector Clamping Automatic Gain Control Analog-to-Digital Converters Digitally Controlled Clock Oscillator Analog Video Output Adaptive Comb Filter Color Decoder IF-Compensation Demodulator Chrominance Filter Frequency Demodulator Burst Detection Color Killer Operation PAL Compensation/1-H Comb Filter Luminance Notch Filter Skew Filtering Horizontal Scaler Blackline Detector Control and Data Output Signals Line-Locked Clock Generation Sync Signals DIGIT3000 Output Format Line-Locked 4:2:2 Output Format Line-Locked 4:1:1 Output Format Output Code Levels Output Signal Levels Test Pattern Generator Priority Bus Codec PAL+ Support Output Signals for PAL+/Color+ Support Video Sync Processing PRELIMINARY DATA SHEET Serial Interface I2C-Bus Interface Control and Status Registers Calculation of Vertical and East-West Deflection Coefficients Scaler Adjustment 2 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C Contents, continued Page 31 31 31 33 35 36 37 37 37 38 39 39 39 39 40 40 41 41 41 43 44 45 46 47 48 Section 4. 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.6.1. 4.6.2. 4.6.3. 4.6.4. 4.6.4.1. 4.6.4.2. 4.6.4.3. 4.6.4.4. 4.6.4.5. 4.6.4.6. 4.6.4.7. 4.6.4.8. 4.6.4.9. 4.6.4.10. 4.6.4.11. 5. 5.1. 6. Title Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions (pin numbers for PLCC68 package) Pin Configuration Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Recommended Crystal Characteristics Characteristics Characteristics, 5 MHz Clock Output Characteristics, 20 MHz Clock Input/Output, External Clock Input (XTAL1) Characteristics, Reset Input, Test Input Characteristics, Priority, FPDAT Input/Output Characteristics, VGAV Input Characteristics, I2C Bus Interface Characteristics, Analog Video Inputs Characteristics, Analog Front-End and ADCs Characteristics, Output Pin Specification Characteristics, Input Pin Specification Characteristics, Clock Output Specification Application Circuit VGA mode with VPC3215C Data Sheet History Micronas 3 VPC 3205C, VPC 3215C Video Processor Family Release Note: Revision bars indicate significant changes to the previous edition. - I2C-Bus Interface PRELIMINARY DATA SHEET - one 20.25 MHz crystal, few external components - 68-pin PLCC package 1. Introduction The VPC 32x5 is a high-quality, single-chip video front-end, which is targeted for 4:3 and 16:9, 50/60 and 100/120 Hz TV sets. It can be combined with other members of the DIGIT3000 IC family (such as CIP 3250A, DDP 3300A, TPU 3040) and/or it can be used with 3rd-party products. The main features of the VPC 32x5 are - all-digital video processing - high-performance adaptive 4H comb filter Y/C separator with adjustable vertical peaking - multi-standard color decoder PAL/NTSC/SECAM including all substandards - 4 composite, 1 S-VHS input, 1 composite output - integrated high-quality A/D converters and associated clamp and AGC circuits - multi-standard sync processing - linear horizontal scaling (0.25 ... 4), as well as non-linear horizontal scaling `panorama vision' - PAL+ preprocessing (VPC 3215) - line-locked clock, data and sync output (VPC 3215) - display/deflection control (VPC 3205) - submicron CMOS technology 1.1. System Architecture Fig. 1-1 shows the block diagram of the video processor. 1.2. Video Processor Family The VPC video processor family supports 15/32 kHz systems and is available with different comb filter options. The 50 Hz/single scan versions provide controlling for the display and the vertical/east west deflection of DDP 3300A. The 100 Hz/double scan versions have a line-locked clock output interface and the PAL+ preprocessing option. Table 1-1 gives an overview of the VPC video processor family. Table 1-1: VPC Processor Family Features 4H comb filter 2H comb filter no comb filter 50 Hz/ single scan VPC 3205C VPC 3200A VPC 3201A 100 Hz/ double scan VPC 3215C VPC 3210A VPC 3211A V1 V2/Y C V3 V4 CVBS Out clock 2*ADC, 8 bit Front-End Adaptive Combfilter Color Decoder NTSC PAL SECAM Horizontal Scaler Panorama mode Output Formatter YUV Clock Gen. DCO 20.25 MHz I2C Sync Processing line-locked clock synthesis H/V I2C Fig. 1-1: VPC 32x5C block diagram 4 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C The IP indicates memory based image processing, such as scan rate conversion, vertical processing (Zoom), or PAL+ reconstruction. Examples: - Europe: 15 kHz/50 Hz 32 kHz/100 Hz interlaced - US: 15 kHz/60 Hz 32 kHz/60 Hz non-interlaced Note that the VPC supports memory based applications through line-locked clocks, syncs, and data. CIP may run either with the native DIGIT3000 clock but also with a line-locked clock system. 1.3. VPC Applications Fig. 1-2 depicts several VPC applications. Since the VPC functions as a video front-end, it must be complemented with additional functionality to form a complete TV set. The DDP 33x0 contains the video back-end with video postprocessing (contrast, peaking, DTI,...), H/V-deflection, RGB insertion (SCART, Text, PIP,...) and tube control (cutoff, white drive, beam current limiter). It generates a beam scan velocity modulation output from the digital YCrCb and RGB signals. Note that this signal is not generated from the external analog RGB inputs. The CIP 3250A provides a high quality analog RGB interface with character insertion capability. This allows appropriate processing of external sources, such as MPEG2 set-top boxes in transparent (4:2:2) quality. Furthermore, it translates RGB/Fastblank signals to the common digital video bus and makes those signals available for 100 Hz upconversion or double scan processing. In some European countries (Italy), this feature is mandatory. a) CVBS RGB VPC 320x DDP 3300A RGB H/V Defl. b) CVBS VPC 321x IP DDP 3310B RGB H/V Defl. c) CVBS RGB VPC 321x CIP 3250A IP DDP 3310B RGB H/V Defl. Fig. 1-2: VPC 32xx applications a) 15 kHz application Europe b) double scan application (US, Japan) c) 100 Hz application (Europe) with RGB inputs Micronas 5 VPC 3205C, VPC 3215C 2. Functional Description 2.1. Analog Front-End This block provides the analog interfaces to all video inputs and mainly carries out analog-to digital conversion for the following digital video processing. A block diagram is given in Fig. 2-1. Most of the functional blocks in the front-end are digitally controlled (clamping, AGC, and clock-DCO). The control loops are closed by the Fast Processor (`FP') embedded in the decoder. PRELIMINARY DATA SHEET 2.1.3. Automatic Gain Control A digitally working automatic gain control adjusts the magnitude of the selected baseband by +6/-4.5 dB in 64 logarithmic steps to the optimal range of the ADC. The gain of the video input stage including the ADC is 213 steps/V with the AGC set to 0 dB. 2.1.4. Analog-to-Digital Converters Two ADCs are provided to digitize the input signals. Each converter runs with 20.25 MHz and has 8 bit resolution. An integrated bandgap circuit generates the required reference voltages for the converters. The two ADCs are of a 2-stage subranging type. 2.1.1. Input Selector Up to five analog inputs can be connected. Four inputs are for input of composite video or S-VHS luma signal. These inputs are clamped to the sync back porch and are amplified by a variable gain amplifier. One input is for connection of S-VHS carrier-chrominance signal. This input is internally biased and has a fixed gain amplifier. 2.1.5. Digitally Controlled Clock Oscillator The clock generation is also a part of the analog front end. The crystal oscillator is controlled digitally by the control processor; the clock frequency can be adjusted within 150 ppm. 2.1.6. Analog Video Output 2.1.2. Clamping The composite video input signals are AC coupled to the IC. The clamping voltage is stored on the coupling capacitors and is generated by digitally controlled current sources. The clamping level is the back porch of the video signal. S-VHS chroma is also AC coupled. The input pin is internally biased to the center of the ADC input range. The input signal of the Luma ADC is available at the analog video output pin. The signal at this pin must be buffered by a source follower. The output voltage is 2 V, thus the signal can be used to drive a 75 line. The magnitude is adjusted with an AGC in 8 steps together with the main AGC. Analog Video Output CVBS/Y CVBS/Y CVBS/Y CVBS/Y Chroma VIN4 VIN3 VIN2 VIN1 CIN input mux clamp gain bias AGC +6/-4.5 dB ADC digital CVBS or Luma ADC digital Chroma system clocks reference generation frequency DVCO 150 ppm 20.25 MHz Fig. 2-1: Analog front-end 6 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C HDG typically defines the comb strength on horizontal edges. It determines the amount of the remaining cross-luminance and the sharpness on edges respectively. As HDG increases, the comb strength, e. g. cross luminance reduction and sharpness, increases. VDG typically determines the comb filter behaviour on vertical edges. As VDG increases, the comb strength, e. g. the amount of hanging dots, decreases. After selecting the combfilter performance in horizontal and vertical direction, the diagonal picture performance may further be optimized by adjusting DDR. As DDR increases, the dot crawl on diagonal colored edges is reduced. To enhance the vertical resolution of the the picture, the VPC 32x5 provides a vertical peaking circuitry. The filter gain is adjustable between 0 - +6 dB and a coring filter suppresses small amplitudes to reduce noise artifacts. In relation to the comb filter, this vertical peaking widely contributes to an optimal two-dimensional resolution homogeneity. 2.2. Adaptive Comb Filter The 4H adaptive comb filter is used for high-quality luminance/chrominance separation for PAL or NTSC composite video signals. The comb filter improves the luminance resolution (bandwidth) and reduces interferences like cross-luminance and cross-color. The adaptive algorithm eliminates most of the mentioned errors without introducing new artifacts or noise. A block diagram of the comb filter is shown in Fig. 2-2. The filter uses four line delays to process the information of three video lines. To have a fixed phase relationship of the color subcarrier in the three channels, the system clock (20.25 MHz) is fractionally locked to the color subcarrier. This allows the processing of all color standards and substandards using a single crystal frequency. The CVBS signal in the three channels is filtered at the subcarrier frequency by a set of bandpass/notch filters. The output of the three channels is used by the adaption logic to select the weighting that is used to reconstruct the luminance/chrominance signal from the 4 bandpass/notch filter signals. By using soft mixing of the 4 signals switching artifacts of the adaption algorithm are completely suppressed. The comb filter uses the middle line as reference, therefore, the comb filter delay is two lines. If the comb filter is switched off, the delay lines are used to pass the luma/chroma signals from the A/D converters to the luma/chroma outputs. Thus, the processing delay is always two lines. In order to obtain the best-suited picture quality , the user has the possibility to influence the behaviour of the adaption algorithm going from moderate combing to strong combing. Therfore, the following three parameters may be adjusted: - HDG ( horizontal difference gain ) - VDG ( vertical difference gain ) - DDR ( diagonal dot reducer ) 2.3. Color Decoder In this block, the standard luma/chroma separation and multi-standard color demodulation is carried out. The color demodulation uses an asynchronous clock, thus allowing a unified architecture for all color standards. A block diagram of the color decoder is shown in Fig. 2-4. The luma as well as the chroma processing, is shown here. The color decoder also provides several special modes, e.g. wide band chroma format which is intended for S-VHS wide bandwidth chroma. Also, filter settings are available for processing a PAL+ helper signal. If the adaptive comb filter is used for luma chroma separation, the color decoder uses the S-VHS mode processing. The output of the color decoder is YCrCb in a 4:2:2 format. CVBS Input 2H Delay Line Bandpass/ Notch Filter Bandpass Filter Luma / Chroma Mixers Adaption Logic Bandpass Filter Luma Output Chroma Output 2H Delay Line Chroma Input Fig. 2-2: Block diagram of the adaptive comb filter (PAL mode) Micronas 7 VPC 3205C, VPC 3215C 2.3.1. IF-Compensation With off-air or mistuned reception, any attenuation at higher frequencies or asymmetry around the color subcarrier is compensated. Four different settings of the IF-compensation are possible (see Fig. 2-3): - flat (no compensation) - 6 dB/octave - 12 dB/octave - 10 dB/MHz The last setting gives a very large boost to high frequencies. It is provided for SECAM signals that are decoded using a SAW filter specified originally for the PAL standard. 2.3.2. Demodulator PRELIMINARY DATA SHEET The entire signal (which might still contain luma) is quadrature-mixed to the baseband. The mixing frequency is equal to the subcarrier for PAL and NTSC, thus achieving the chroma demodulation. For SECAM, the mixing frequency is 4.286 MHz giving the quadrature baseband components of the FM modulated chroma. After the mixer, a lowpass filter selects the chroma components; a downsampling stage converts the color difference signals to a multiplexed half rate data stream. The subcarrier frequency in the demodulator is generated by direct digital synthesis; therefore, substandards such as PAL 3.58 or NTSC 4.43 can also be demodulated. 2.3.3. Chrominance Filter The demodulation is followed by a lowpass filter for the color difference signals for PAL/NTSC. SECAM requires a modified lowpass function with bell-filter characteristic. At the output of the lowpass filter, all luma information is eliminated. The lowpass filters are calculated in time multiplex for the two color signals. Three bandwidth settings (narrow, normal, broad) are available for each standard (see Fig. 2-5). For PAL/NTSC, a wide band chroma filter can be selected. This filter is intended for high bandwidth chroma signals, e.g. a nonstandard wide bandwidth S-VHS signal. Fig. 2-3: Frequency response of chroma IF-compensation Luma / CVBS Notch Filter Luma MUX 1 H Delay CrossSwitch Chroma ACC MUX IF Compensation MIXER DC-Reject Lowpass Filter Phase/Freq Demodulator Chroma ColorPLL/ColorACC Fig. 2-4: Color decoder 8 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C The ACC has a control range of +30 ... -6 dB. For SECAM decoding, the frequency of the burst is measured. Thus, the current chroma carrier frequency can be identified and is used to control the SECAM processing. The burst measurements also control the color killer operation; they can be used for automatic standard detection as well. 2.3.6. Color Killer Operation PAL/NTSC The color killer uses the burst-phase/burst-frequency measurement to identify a PAL/NTSC or SECAM color signal. For PAL/NTSC, the color is switched off (killed) as long as the color subcarrier PLL is not locked. For SECAM, the killer is controlled by the toggle of the burst frequency. The burst amplitude measurement is used to switch-off the color if the burst amplitude is below a programmable threshold. Thus, color will be killed for very noisy signals. The color amplitude killer has a programmable hysteresis. SECAM Fig. 2-5: Frequency response of chroma filters 2.3.7. PAL Compensation/1-H Comb Filter The color decoder uses one fully integrated delay line. Only active video is stored. The delay line application depends on the color standard: - NTSC: - PAL: 1-H comb filter or color compensation color compensation 2.3.4. Frequency Demodulator The frequency demodulator for demodulating the SECAM signal is implemented as a CORDIC-structure. It calculates the phase and magnitude of the quadrature components by coordinate rotation. The phase output of the CORDIC processor is differentiated to obtain the demodulated frequency. After the deemphasis filter, the Dr and Db signals are scaled to standard CrCb amplitudes and fed to the crossover-switch. - SECAM: crossover-switch In the NTSC compensated mode, Fig. 2-6 c), the color signal is averaged for two adjacent lines. Thus, cross-color distortion and chroma noise is reduced. In the NTSC 1-H comb filter mode, Fig. 2-6 d), the delay line is in the composite signal path, thus allowing reduction of cross-color components, as well as cross-luminance. The loss of vertical resolution in the luminance channel is compensated by adding the vertical detail signal with removed color information. If the 4H adaptive comb filter is used, the 1-H NTSC comb filter has to be deselected. 2.3.5. Burst Detection In the PAL/NTSC-system the burst is the reference for the color signal. The phase and magnitude outputs of the CORDIC are gated with the color key and used for controlling the phase-lock-loop (APC) of the demodulator and the automatic color control (ACC) in PAL/NTSC. Micronas 9 VPC 3205C, VPC 3215C PRELIMINARY DATA SHEET 2.3.8. Luminance Notch Filter CVBS 8 Notch filter Chroma Process. Y Cr C b Luma 8 Y Chroma Process. chroma 8 Cr C b a) conventional CVBS 8 Notch filter b) S-VHS Y If a composite video signal is applied, the color information is suppressed by a programmable notch filter. The position of the filter center frequency depends on the subcarrier frequency for PAL/NTSC. For SECAM, the notch is directly controlled by the chroma carrier frequency. This considerably reduces the cross-luminance. The frequency responses for all three systems are shown in Fig. 2-9. 10 0 dB Chroma Process. 1H Delay Cr C b c) compensated CVBS 8 1H Delay Notch filter -10 Y -20 -30 Chroma Process. Cr C b -40 0 2 4 6 8 10 MHz d) comb filter Fig. 2-6: NTSC color decoding options PAL/NTSC notch filter dB 10 0 -10 -20 CVBS 8 -30 Notch filter Y -40 0 2 4 6 8 10 MHz Chroma Process. 1H Delay Cr C b SECAM notch filter Fig. 2-9: Frequency responses of the luma notch filter for PAL, NTSC, SECAM a) conventional Luma 8 Y 2.3.9. Skew Filtering Chroma Process. 1H Delay Chroma 8 Cr C b b) S-VHS Fig. 2-7: PAL color decoding options The system clock is free-running and not locked to the TV line frequency. Therefore, the ADC sampling pattern is not orthogonal. The decoded YCrCb signals are converted to an orthogonal sampling raster by the skew filters, which are part of the scaler block. The skew filters are controlled by a skew parameter and allow the application of a group delay to the input signals without introducing waveform or frequency response distortion. The amount of phase shift of this filter is controlled by the horizontal PLL1. The accuracy of the filters is 1/32 clocks for luminance and 1/4 clocks for chroma. Thus the 4:2:2 YCrCb data is in an orthogonal pixel format even in the case of nonstandard input signals such as VCR. CVBS 8 Notch filter Y Chroma Process. 1H Delay MUX Cr C b Fig. 2-8: SECAM color decoding 10 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C to the previous measurement and the minima are stored in the I2C-register BLKLIN. To adjust the picture amplitude, the external controller reads this register, calculates the vertical scaling coefficient and transfers the new settings, e.g. vertical sawtooth parameters, horizontal scaling coefficient etc., to the VPC. Letterbox signals containing logos on the left or right side of the black areas are processed as black lines, while subtitles, inserted in the black areas, are processed as non-black lines. Therefore the subtitles are visible on the screen. To suppress the subtitles, the vertical zoom coefficient is calculated by selecting the larger number of black lines only. Dark video scenes with a low contrast level compared to the letterbox area are indicated by the BLKPIC bit. 2.4. Horizontal Scaler The 4:2:2 YCrCb signal from the color decoder is processed by the horizontal scaler. The scaler block allows a linear or nonlinear horizontal scaling of the input video signal in the range of 0.25 to 4. Nonlinear scaling, also called "panorama vision", provides a geometrical distortion of the input picture. It is used to fit a picture with 4:3 format on a 16:9 screen by stretching the picture geometry at the borders. Also, the inverse effect can be produced by the scaler. A summary of scaler modes is given in Table 2-1. The scaler contains a programmable decimation filter, a 1-line FIFO memory, and a programmable interpolation filter. The scaler input filter is also used for pixel skew correction, see 2.3.9. The decimator/interpolator structure allows optimal use of the FIFO memory. The controlling of the scaler is done by the internal Fast Processor. Table 2-1: Scaler modes Mode Compression 4:3 16:9 Panorama 4:3 16:9 Zoom 4:3 4:3 Scale Factor 0.75 linear nonlinear compr 1.33 linear Description 4:3 source displayed on a 16:9 tube, with side panels 4:3 source displayed on a 16:9 tube, Borders distorted Letterbox source (PAL+) displayed on a 4:3 tube, vertical overscan with cropping of side panels Letterbox source (PAL+) displayed on a 4:3 tube, vertical overscan, borders distorted, no cropping sample rate conversion to line-locked clock 2.6. Control and Data Output Signals The VPC 32xx supports two output modes: In DIGIT3000 mode, the output interfaces run at the main system clock, in line-locked mode, the VPC generates an asynchronous line-locked clock that is used for the output interfaces. 2.6.1. Line-Locked Clock Generation An on-chip rate multiplier will be used to synthesize any desired output clock frequency of 13.5/16/18 MHz. A double clock frequency output is available to support 100 Hz systems. The synthesizer is controlled by the embedded RISC controller, which also controls all front-end loops (clamp, AGC, PLL1, etc.). This allows the generation of a line-locked output clock regardless of the system clock (20.25 MHz) which is used for comb filter operation and color decoding. The control of scaling and output clock frequency is kept independent to allow aspect ratio conversion combined with sample rate conversion. The line-locked clock circuity generates control signals, e.g. horizontal/vertical sync, active video output, it is also the interface from the internal (20.25 MHz) clock to the external line-locked clock system. If no line-locked clock is required, i.e. in the DIGIT3000 mode, the system runs at the 20.25 MHz main clock. The horizontal timing reference in this mode is provided by the front-sync signal. In this case, the line-locked clock block and all interfaces run from the 20.25 MHz main clock. The synchronization signals from the line-locked clock block are still available, but for every line the internal counters are reset with the main-sync signal. A double clock signal is not available in DIGIT3000 mode. Panorama 4:3 4:3 nonlinear zoom 20.25 13.5 MHz 0.66 2.5. Blackline Detector In case of a letterbox format input video, e.g. Cinemascope, PAL+ etc., black areas at the upper and lower part of the picture are visible. It is suitable to remove or reduce these areas by a vertical zoom and/or shift operation. The VPC 32xx supports this feature by a letterbox detector. The circuitry detects black video lines by measuring the signal amplitude during active video. For every field the number of black lines at the upper and lower part of the picture are measured, compared Micronas 11 VPC 3205C, VPC 3215C 2.6.2. Sync Signals The front end will provide a number of sync/control signals which are output with the output clock. The sync signals are generated in the line-locked clock block. - Href : - AVO: - HC: - Vref : - INTLC: - HELPER: horizontal sync active video out (programmable) horizontal clamp (programmable) vertical sync interlace PAL+ helper lines PRELIMINARY DATA SHEET 2.6.5. Line-Locked 4:1:1 Output Format The orthogonal 4:1:1 output format is compatible to the industry standard. The YCrCb samples are skew-corrected and interpolated to an orthogonal sampling raster (see Table 2-3). Table 2-3: 4:1:1 Orthogonal output format Luma Chroma C3 , C7 C2 , C6 C1 , C5 C0 , C4 note: C*xY Y1 Cb17 Cb16 Cr17 Cr16 Y2 Cb15 Cb14 Cr15 Cr14 Y3 Cb13 Cb12 Cr13 Cr12 Y4 Cb11 Cb10 Cr11 Cr10 All horizontal signals are not qualified with field information, i.e. the signals are present on all lines. The horizontal timing is shown in Fig. 2-10. Details of the horizontal/vertical timing are given in Fig. 2-14. (x = pixel number and y = bit number) 2.6.3. DIGIT3000 Output Format 2.6.6. Output Code Levels The picture bus format between all DIGIT3000 ICs is 4:2:2 YCrCb with 20.25 MHz samples/s. Only active video is transferred, synchronized by the system main sync signal (MSY) which indicates the start of valid data for each scan line and which initializes the color multiplex. The video data is orthogonally sampled YCrCb, the output format is given in Table 2-2. The number of active samples per line is 1080 for all standards (525 and 625). The output can be switched to 4:1:1 mode with the output format according to Table 2-3. Via the MSY line, serial data is transferred which contains information about the main picture such as current line number, odd/even field etc.). It is generated by the deflection circuitry and represents the orthogonal timebase for the entire system. Table 2-2: Orthogonal 4:2:2 output format Luma Chroma Y1 Cb1 Y2 Cr1 Y3 Cb3 Y4 Cr3 Output Code Levels correspond to ITU-R code levels: Y = 16...240 Black Level = 16 CrCb = 128112 An overview over the output code levels is given in Table 2-4. 2.6.7. Output Signal Levels All data and sync lines operate at TTL compliant levels. With an optional external 3.3 V supply for the output pins, reduced voltage swings can be obtained. 2.6.8. Test Pattern Generator The YCrCb outputs can be switched to a test mode where YCrCb data are generated digitally in the VPC32xx. Test patterns include luma/chroma ramps, flat field, and a pseudo color bar. 2.6.4. Line-Locked 4:2:2 Output Format In line-locked mode, the VPC 32xx will produce the industry standard pixel stream for YCrCb data. The difference to DIGIT3000 native mode is only the number of active samples, which of course, depends on the chosen scaling factor. Thus, Table 2-2 is valid for both 4:2:2 modes. 12 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C - delay compensation to composite video path - helper window (line# identification) - output at the luma output port Helper signals are processed like the main video luma signals, i.e. they are subject to scaling, sample rate conversion and orthogonalization if activated. The adaptive comb filter processing is switched off for the helper lines. It is expected that further helper processing (e.g. nonlinear expansion, matched filter) is performed outside the VPC. 2.6.9. Priority Bus Codec The VPC data outputs are controlled by the priority bus interface. This interface allows a maximum of 8 signal sources to be connected on a common video YCrCb bus. The 3-bit priority bus signal controls the arbitration and source switching of the video sources on a pixel-by-pixel basis. The priority bus makes features possible, such as - real time digital PIP insertion - Teletext/Mixed-mode picture insertion. In general, each source has its own YCrCb bus request. This bus request may either be software or hardware controlled, i.e. a fast blank signal. Data collision on the bus is avoided by a bus arbiter that provides the individual bus grant in accordance to the user defined source priority. Each master sends a bus request using his individual priority ID onto the bus and immediately reads back the bus state. Only in case of a positive arbitration, e.g. the master reads back his own priority ID, the bus is granted to the master. 2.7.1. Output Signals for PAL+/Color+ Support For a PAL+/Color+ signal, the 625 line PAL image contains a 16/9 core picture of 431 lines which is in standard PAL format. The upper and lower 72 lines contain the PAL+ helper signal, and line 23 contains signalling information for the PAL+ transmission. For PAL+ mode, the Y signal of the core picture, which is during lines 60-274 and 372-586, is replaced by the orthogonal composite video input signal. In order to fit the signal to the 8-bit port width, the ADC signal amplitudes are used. During the helper window, which is in lines 24-59, 275-310, 336-371, 587-622, the demodulated helper is signal processed by the horizontal scaler and the output circuitry. It is available at the luma output port. The processing in the helper reference lines 23 and 623 is different for the wide screen signaling part and the black reference and helper burst signals. The code levels are given in detail in Table 2-4, the output signal for the helper reference line is shown in Fig. 2-11. 2.7. PAL+ Support For PAL+, the VPC 321x provides basic helper preprocessing: - A/D conversion (shared with the existing ADCs) - mixing with subcarrier frequency - lowpass filter 2.5 MHz - gain control by chroma ACC Table 2-4: Output signal code levels for PAL/PAL+ signal Output Signal Luma Outputs Y[7:0] Output Format Standard YCrCb (100% Chroma CVBS, CrCb binary Black/Zero Level 16 Amplitude 224 Chroma Outputs C[7:0] Output Format offset binary signed binary 64 149 (luma) offset binary signed Demodulated Helper Helper WSS Helper black level, Ref. Burst signed binary offset binary 0 68 128 Amplitude 128112 112 128112 112 - - - 109 149 (WSS:106) 19 (128-109) - - - Micronas 13 VPC 3205C, VPC 3215C PRELIMINARY DATA SHEET horizontal pixel counter 0 horizontal sync (HS) 1 horizontal clamp (HC) 31 start / stop programmable line length (programmable) newline (internal signal) start of video output (programmable) active video out (AVO) start / stop programmable vertical sync (VS), field 1 16 vertical sync (VS), field 2 line length/2 field 1 field 2 Fig. 2-10: Horizontal timing for line-locked mode 255 black level WSS Signal 174 Helper Burst (demodulated) 255 128 68 19 0 binary format signed format Fig. 2-11: PAL+ helper reference line output signal 14 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C For vertical sync separation, the sliced video signal is integrated. The FP uses the integrator value to derive vertical sync and field information. The information extracted by the video sync processing is multiplexed onto the hardware front sync signal (FSY) and is distributed to the rest of the video processing system. The format of the front sync signal is given in Fig. 2-13. The data for the vertical deflection, the sawtooth, and the East-West correction signal is calculated by the VPC 32xx. The data is buffered in a FIFO and transferred to the back-end IC DDP 3300A by a single wire interface. Frequency and phase characteristics of the analog video signal are derived from PLL1. The results are fed to the scaler unit for data interpolation and orthogonalization and to the clock synthesizer for line-locked clock generation. Horizontal and vertical syncs are latched with the line-locked clock. 2.8. Video Sync Processing Fig. 2-12 shows a block diagram of the front-end sync processing. To extract the sync information from the video signal, a linear phase lowpass filter eliminates all noise and video contents above 1 MHz. The sync is separated by a slicer; the sync phase is measured. A variable window can be selected to improve the noise immunity of the slicer. The phase comparator measures the falling edge of sync, as well as the integrated sync pulse. The sync phase error is filtered by a phase-locked loop that is computed by the FP. All timing in the front-end is derived from a counter that is part of this PLL, and it thus counts synchronously to the video signal. A separate hardware block measures the signal back porch and also allows gathering the maximum/minimum of the video signal. This information is processed by the FP and used for gain control and clamping. PLL1 lowpass 1 MHz & syncslicer video input frontend timing clamp & signal meas. clamping, colorkey, FIFO_write clock synthesizer syncs clock H/V syncs horizontal sync separation phase comparator & lowpass counter front sync generator front sync skew vblank field vertical sync separation Sawtooth Parabola Calculation FIFO vertical serial data vertical E/W sawtooth Fig. 2-12: Sync separation block diagram F1 input analog video skew LSB skew not MSB used F V F0 reserved (not in scale) F0 F1 V: vertical sync 0 = off Parity 1 = on F: field # 0 = field 1 1 = field 2 FSY Fig. 2-13: Front sync format Micronas 15 VPC 3205C, VPC 3215C PRELIMINARY DATA SHEET field 1 CCIR 623 624 625 1 2 3 4 5 6 7 8 23 24 Front-Sync (FSY) Vertical Sync (VS) Interlace (INTLC) > 1clk field 2 CCIR 310 311 312 313 314 315 316 317 318 319 320 335 336 Vertical Sync (VS) Interlace (INTLC) >1 clk Active Video Output (AVO) helper ref line 23, 623 (internal signal) signal matches output video The following signals are identical for field1 / field2 helper lines 23-59, 275-310, 336-371, 587-623, signal matches output video Fig. 2-14: Vertical timing of VPC 32x5 shown in reference to input video. Video output signals are delayed by 3-h for comb filter version (VPC 32x5). 16 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C 3.2. Control and Status Registers Table 3-1 gives definitions of the VPC control and status registers. The number of bits indicated for each register in the table is the number of bits implemented in hardware, i.e. a 9-bit register must always be accessed using two data bytes but the 7 MSB will be `don't care' on write operations and `0' on read operations. Write registers that can be read back are indicated in Table 3-1. Functions implemented by software in the on-chip control microprocessor (FP) are explained in Table 3-2. A hardware reset initializes all control registers to 0. The automatic chip initialization loads a selected set of registers with the default values given in Table 3-1. The register modes given in Table 3-1 are - w: - w/r: - r: - v: write only register write/read data register read data from VPC register is latched with vertical sync 3. Serial Interface 3.1. I2C-Bus Interface Communication between the VPC and the external controller is done via I2C-bus. The VPC has an I2C-bus slave interface and uses I2C clock synchronization to slow down the interface if required. The I2C-bus interface uses one level of subaddress: one I2C-bus address is used to address the IC and a subaddress selects one of the internal registers. The I2C-bus chip address is given below: A6 1 A5 0 A4 0 A3 0 A2 1 A1 1 A0 1 R/W 1/0 The registers of the VPC have 8 or 16-bit data size; 16-bit registers are accessed by reading/writing two 8-bit data words. Figure 3-1 shows I2C-bus protocols for read and write operations of the interface; the read operation requires an extra start condition and repetition of the chip address with read command set. The mnemonics used in the Intermetall VPC demo software are given in the last column. S 1000 111 W Ack 0111 1100 Ack 1 or 2 byte Data P I2C write access subaddress 7c I2C read access subaddress 7c S 1000 111 W Ack 0111 1100 Ack S 1000 111 R Ack high byte Data Ack low byte Data Nak P SDA 1 0 S P SCL W R Ack Nak S P = = = = = = 0 1 0 1 Start Stop Fig. 3-1: I2C-bus protocols Micronas 17 VPC 3205C, VPC 3215C Table 3-1: Control and status registers I2C Subaddress Number of bits Mode Function PRELIMINARY DATA SHEET Default Name FP Interface h'35 8 r FP status bit [0] bit [1] bit [2] bit[8:0] bit[11:9] bit[8:0] bit[11:9] bit[11:0] - write request read request busy 9-bit FP read address reserved, set to zero 9-bit FP write address reserved, set to zero FP data register, reading/writing to this register will autoincrement the FP read/ write address. Only 16 bit of data are transferred per I2C telegram. Black Line Detector h'12 16 w/r read only register, do not write to this register! After reading, LOWLIN and UPLIN are reset to 127 to start a new measurement. bit[6:0] number of lower black lines bit[7] always 0 bit[14:8] number of upper black lines bit[15] 0/1 normal/black picture Pin Circuits h'1F 16 w/r SYNC pins (HS, HC, AVO, HELP, INTLC, VS): bit[2:0] 0..7 output strength for SYNC Pins (7 = tristate, 6 = weak ... 0 = strong) bit[3] 0/1 pushpull/tristate for AVO Pin bit[4] 0/1 pushpull/tristate for other SYNC Pins bit[5] 0/1 synchronization/no synchronization with horizontal HS for signals VS and INTLC CLOCK pins (LLC1, LLC2): bit[6] 0/1 pushpull/tristate for LLC1 bit[7] 0/1 pushpull/tristate for LLC2 DATA pins (LB[7:0], CB[7:0]): bit[10:8] 0..7 output strength for DATA pins (7 = tristate, 6 = weak ... 0 = strong) bit[11] 0/1 tristate/pushpull for DATA pins bit[12] 0/1 half-cycle pull-up(DIGIT3000)/pushpull for LB, CB (LCC) bit[13] reserved (set to 0) bit[14:15] output strength for LLC1: (-2,-1,0,1) 0 0 0 0 TRPAD SNCSTR AVODIS SNCDIS VASYSEL - BLKLIN - - - FPRD FPWR FPDAT FPSTA h'36 h'37 h'38 16 16 16 w w w/r LOWLIN UPLIN BLKPIC 0 0 0 0 0 LLC1DIS LLC2DIS DATSTR DATEN LCPUDIS 0 LLC1STR 18 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C I2C Subaddress Number of bits Mode Function Default Name h'20 8 w/r SYNC GENERATOR CONTROL: bit[1:0] 00 AVO and active Y/C data at same time 01 AVO precedes Y/C data one clock cycle 10 AVO precedes Y/C data two clock cycles 11 AVO precedes Y/C data three clock cycles bit[2] 0/1 positive/negative polarity for HS signal bit[3] 0/1 positive/negative polarity for HC signal bit[4] 0/1 positive/negative polarity for AVO signal bit[5] 0/1 positive/negative polarity for VS signal bit[6] 0/1 positive/negative polarity for HELP signal bit[7] 0/1 positive/negative polarity for INTLC signal V-SYNC DELAY CONTROL: bit[7:0] VS delay (8 LLC clock cycles per LSB) Priority Bus SYNCMODE 0 AVOPRE 0 0 0 0 0 0 0 HSINV HCINV AVOINV VSINV HELPINV INTLCINV VSDEL VSDEL h'30 8 w/r h'23 h'24 8 8 w/r w/r priority bus overwrite register bit [7:0] 8 bit mask, bit[x] = 1 : overwrite priority x priority bus ID register and control bit [2:0] 0..7 priority ID, 0 highest bit [4:3] 0..3 pad driver strength, 0 (strong) to 3 (weak) bit [5] 0/1 output mode: DIGIT3000/LLC bit [6] 0/1 source for prio request: AVO/active always bit [7] 0/1 disable/enable priority interface, if disabled data pins are tristate ! 0 0 0 0 0 0 PRIOVR PRIOMODE PID PRIOSTR OMODE PIDSRC PIDE Sync Generator h'21 16 w/r LINE LENGTH: bit[10:0] LINE LENGTH register In LLC mode, this register defines the cycle of the sync counter which generates the SYNC pulses. In LLC mode, the synccounter counts from 0 to LINE LENGTH, so this register has to be set to "number of pixels per line -1". In DIGIT3000 mode, LINE LENGTH has to be set to 1295 for correct adjustment of vertical signals. reserved (set to 0) HC START defines the beginning of the HC signal in respect to the value of the sync counter. reserved (set to 0) HC STOP defines the end of the HC signal in respect to the value of the sync counter. reserved (set to 0) 1295 LINLEN bit[15:11] h'26 16 w/r HC START: bit[10:0] 50 HCSTRT bit[15:11] h'27 16 w/r HC STOP: bit[10:0] bit[15:11] 800 HCSTOP Micronas 19 VPC 3205C, VPC 3215C PRELIMINARY DATA SHEET I2C Subaddress Number of bits Mode Function Default Name h'28 16 w/r AVO START: bit[10:0] bit[11] bit[12] 0/1 bit[13] 0/1 bit[15:14] -2..1 h'29 16 w/r AVO STOP: bit[10:0] AVO START defines the beginning of the AVO signal in respect to the value of the sync counter. reserved (set to 0) vertical window disable/enable vertical window 312/262 lines vertical window interlace offset AVO STOP defines the end of the AVO signal in respect to the value of the sync counter. reserved for test picture generation (set to 0 in normal operation) disable/enable test pattern generator luma output mode: Y = ramp (240 ... 17) Y = 16 Y = 90 Y = 240 chroma output: 422/411 mode chroma output: pseudo color bar/zero if LMODE = 0 NEWLINE defines the readout start of the next line inrespect to the value of the sync counter. The value of this register must be greater than 31 for correct operation and should be identical to AVOSTART (recommended). In case of 1H-bypass mode for scaler block, NEWLINE has no function. reserved (set to 0) vertical free run mode enabled, the vertical frequency is selected via VERWIN (h'28) reserved (set to 0) 60 AVSTRT VERWIN 0 AVSTOP bit[15:11] bit[11] 0/1 bit[13:12] 00 01 10 11 bit[14] 0/1 bit[15] 0/1 h'22 16 w/r NEWLINE: bit[10:0] 0 0 COLBAREN LMODE 0 0 M411 CMODE 50 NEWLIN bit[12:11] bit[13] bit[15:14] 0 FLW 20 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C Table 3-2: Control Registers of the Fast Processor - default values are initialized at reset - * indicates: register is initialized according to the current standard when SDT register is changed. FP Subaddress Function Standard Selection h'20 Standard select: bit[2:0] standard 0 PAL B,G,H,I 1 NTSC M 2 SECAM 3 NTSC44 4 PAL M 5 PAL N 6 PAL 60 7 NTSC COMB 0/1 0 (50 Hz) (60 Hz) (50 Hz) (60 Hz) (60 Hz) (50 Hz) (60 Hz) (60 Hz) 4.433618 3.579545 4.286 4.433618 3.575611 3.582056 4.433618 3.579545 0 PAL NTSC SECAM NTSC44 PALM PALN PAL60 NTSCC SDTMOD SDT Default Name bit[3] MOD standard modifier PAL modified to simple PAL NTSC modified to compensated NTSC SECAM modified to monochrome 625 NTSCC modified to monochrome 525 PAL+ mode off/on 4-H COMB mode S-VHS mode: The S-VHS/COMB bits allow the following modes: composite input signal comb filter active S-VHS input signal CVBS mode (composite input signal, no luma notch) bit[4] bit[5] bit[6] 0/1 0/1 0/1 00 01 10 11 0 0 0 PALPLUS COMB SVHS Option bits allow to suppress parts of the initialization; this can be used for color standard search: bit[7] bit[8] bit[9] bit[10] bit[11] no hpll setup no vertical setup no acc setup 4-H comb filter setup only status bit, normally write 0. After the FP has switched to a new standard, this bit is set to 1 to indicate operation complete. Standard is automatically initialized when the insel register is written. 0 SDTOPT Micronas 21 VPC 3205C, VPC 3215C PRELIMINARY DATA SHEET FP Subaddress h'21 Function Input select: bit[1:0] 00 01 10 11 bit[2] 0/1 bit[4:3] 00 01 10 11 bit[6:5] 00 01 10 11 0/1 0/1 00 01 10 11 bit[11] writing to this register will also initialize the standard luma selector VIN3 VIN2 VIN1 VIN4 chroma selector VIN1/CIN IF compensation off 6 dB/Okt 12 dB/Okt 10 dB/MHz only for SECAM chroma bandwidth selector narrow normal broad wide adaptive/fixed SECAM notch filter enable luma lowpass filter hpll speed no change terrestrial vcr mixed status bit, write 0, this bit is set to 1 to indicate operation complete. Default Name INSEL 0 VIS 1 0 CIS IFC 2 CBW bit[7] bit[8] bit[10:9] 0 0 3 FNTCH LOWP HPLLMD h'22 picture start position: This register sets the start point of active video and can be used e.g. for panning. The setting is updated when `sdt' register is updated or when the scaler mode register `scmode' is written. luma/chroma delay adjust. The setting is updated when `sdt' register is updated. bit[5:0] reserved, set to zero bit[11:6] luma delay in clocks, allowed range is +1 ... -7 helper delay register (PAL+ mode only) bit[11:0] delay adjust for helper lines adjustable from -96...96, 1 step corresponds to 1/32 clock VGA mode select, pull-in range is limited to 2% bit[1:0] 0 31.5 kHz 1 35.2 kHz 2/3 37.9 kHz is set to 0 by FP if VGA = 0 bit[10] 0/1 disable/enable VGA mode bit[11] status bit, write 0, this bit is set to 1 to indicate operation complete. 0 SFIF h'23 0 LDLY h'29 0 HLP_DLY h'2f VGA_C 0 VGAMODE 0 VGA 22 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C FP Subaddress Function Comb Filter Default Name h'28 comb filter control register bit[1:0] notch filter select 00 flat frequency characteristic 01 min. peaked 10 med. peaked 11 max. peaked bit[3:2] diagonal dot reduction 00 min. reduction ... 11 max. reduction bit[4:5] horizontal difference gain 00 min. gain ... 11 max. gain bit[7:6] vertical difference gain 00 max. gain ... 11 min. gain bit[11:8] vertical peaking gain 0 no vertical peaking... 15 max. vertical peaking comb filter test register bit[1:0] reserved, set ot 0 bit[2] 0/1 disable/enable vertical peaking DC rejection filter bit[3] 0/1 disable/enable vertical peaking coring bit[11:4] reserved, set to 0 Color Processing h'e7 3 COMB_UC NOSEL 1 2 3 0 DDR HDG VDG VPK CMB_TST h'55 0 0 DCR COR h'34 h'36 ACC multiplier value for PAL+ Helper Signal b[10:0] eeemmmmmmmm m * 2-e ACC PAL+ Helper gain adjust, gain is referenced to PAL burst, allowed values from 256..1023 a value of zero allows manual adjust of Helper amplitude via ACCh amplitude killer level (0:killer disabled) amplitude killer hysteresis automatic helper disable for nonstandard signals bit[11:0] 0 automatic function disabled bit[1:0] 01 enable bit[11:2] 1..50 number of fields to switch on helper signal NTSC tint angle, 512 = /4 Horizontal PLL 1280 787 ACCH HLPGAIN h'39 h'3a h'16c 25 5 0 KILVL KILHY HLPDIS h'dc 0 TINT h'aa h'ab h'ac h-pll gain setting, these registers are used to set the h-pll speed, pll speed selection is done via the input selection register DVCO h'f8 h'f9 crystal oscillator center frequency adjust, -2048 ... 2047 crystal oscillator center frequency adjustment value for line-lock mode, true adjust value is DVCO - ADJUST. For factory crystal alignment, using standard video signal: disable autolock mode, set DVCO = 0, set lock mode, read crystal offset from ADJUST register and use negative value for initial center frequency adjustment via DVCO. -720 read only DVCO ADJUST Micronas 23 VPC 3205C, VPC 3215C PRELIMINARY DATA SHEET FP Subaddress h'f7 Function crystal oscillator line-locked mode, lock command/status write: 100 enable lock 0 disable lock read: 0 unlocked >2047 locked crystal oscillator line-locked mode, autolock feature. If autolock is enabled, crystal oscillator locking is started automatically. bit[11:0] threshold, 0:autolock off FP Status Register Default 0 Name XLCK h'b5 400 AUTOLCK h'12 general purpose control bits bit[2:0] reserved, do not change bit[3] vertical standard force bit[8:4] reserved, do not change bit[9] disable flywheel interlace bit[11:10] reserved, do not change to enable vertical free run mode set vfrc to 1 and dflw to 0 standard recognition status bit[0] 1 vertical lock bit[1] 1 horizontally locked bit[2] 1 no signal detected bit[3] 1 color amplitude killer active bit[4] 1 disable amplitude killer bit[5] 1 color ident killer active bit[6] 1 disable ident killer bit[7] 1 interlace detected bit[8] 1 no vertical sync detection bit[9] 1 spurious vertical sync detection bit[12:10] reserved input noise level, available only for VPC 3215C number of lines per field, P/S: 312, N: 262 vertical field counter, incremented per field measured sync amplitude value, nominal: 768 (PAL), 732 (NTSC) measured burst amplitude firmware version number bit[7:0] internal revision number bit[11:8] firmware release hardware version number bit[5:0] internal hardware revision number bit[11:6] hardware id, VPC 32x5C = 01 0 1 VFRC DFLW h'13 - ASR h'14 h'cb h'15 h'74 h'31 h'f0 read only read only read only read only read only read only NOISE NLPF VCNT SAMPL BAMPL - h'f1 read only - 24 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C FP Subaddress Function Scaler Control Register Default Name h'40 scaler mode register bit[1:0] scaler mode 0 linear scaling mode 1 nonlinear scaling mode, 'panorama' 2 nonlinear scaling mode, 'waterglass' 3 reserved bit[2] reserved, set to 0 bit[3] color mode select 0/1 4:2:2 mode / 4:1:1 mode bit[4] scaler bypass bit[5] reserved, set to 0 bit[6] luma output format 0 ITU-R luma output format (16-240) 1 CVBS output format bit[7] chroma output format 0/1 ITU-R (offset binary) / signed bit[10:8] reserved, set to 0 bit[11] 0 scaler update command, when the registers are updated the bit is set to 1 luma offset register bit[6:0] luma offset 0..127 ITU-R output format: 57 CVBS output format: 4 this register is updated when the scaler mode register is written active video length for 1H-FIFO bit[11:0] length in pixels D3000 mode (1296/h)1080 LLC mode (864/h)720 this register is updated when the scaler mode register is written scaler1 coefficient: This scaler compresses the signal. For compression by a factor c, the value c*1024 is required. bit[11:0] allowed values from 1024... 4095 This register is updated when the scaler mode register is written. scaler2 coefficient: This scaler expands the signal. For expansion by a factor c, the value 1/c*1024 is required. bit[11:0] allowed values from 256..1024 This register is updated when the scaler mode register is written. scaler1/2 nonlinear scaling coefficient This register is updated when the scaler mode register is written. scaler1 window controls, see table 5 12-bit registers for control of the nonlinear scaling This register is updated when the scaler mode register is written. scaler2 window controls, see table 5 12-bit registers for control of the nonlinear scaling This register is updated when the scaler mode register is written. 0 SCMODE PANO S411 BYE YOF COF h'41 57 YOFFS h'42 1080 FFLIM h'43 1024 SCINC1 h'44 1024 SCINC2 h'45 h'47 - h'4b h'4c - h'50 0 0 SCINC SCW1_0 - 4 0 SCW2_0 - 4 Micronas 25 VPC 3205C, VPC 3215C PRELIMINARY DATA SHEET FP Subaddress Function LLC Control Register Default Name h'60 h'65 horizontal offset bit[11:0] offset between FSY and HS vertical freeze start freeze llc pll for llc_start < line number < llc_stop bit[11:0] allowed values from -156...+156 vertical freeze stop freeze llc pll for llc_start < line number < llc_stop bit[11:0] allowed values from -156...+156 20 bit llc clock center frequency 13.5 MHz 174763 = h'02AAAB 16 MHz -135927 = h'FDED08 18 MHz 174763 = h'02AAAB pll frequency limiter, 8% 13.5 MHz 54 16 MHz 48 18 MHz 54 llc clock generator control word bit[4:0] hardware register shadow llc_clkc = 513.5 MHz llc_clkc = 316 MHz llc_clkc = 318 MHz bit[10:5] reserved bit[11] 0/1 enable/disable llc pll 0 -10 LLC_OFFSET LLC_START h'66 4 LLC_STOP h'69 h'6a 42 = h'02A 2731 = h'AAB LLC_CLOCKH LLC_CLOCKL h'61 54 LLC_DFLIMIT h'6d 2053 LLC_CLKC 26 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C Table 3-3: Control Registers of the Fast Processor that are used for the control of DDP 3300A - this function is only available in the 50 Hz version (VPC 320x) - default values are initialized at reset - * indicates: register is initialized according to the current standard when SDT register is changed FP Subaddress Function FP Display Control Register h'130 h'131 h'132 h'139 h'13c White Drive Red White Drive Green White Drive Blue (0...1023) (0...1023) (0...1023) 700 700 700 256 256 WDR 1) WDG 1) WDB 1) IBR IBRM Default Name Internal Brightness, Picture (0 ..511), the center value is 256, the range allows for both increase and reduction of brightness. Internal Brightness, measurement (0...511), the center value is 256, the brightness for measurement can be set to measure at higher cutoff current. The measurement brightness is independent of the drive values. Analog Brightness for external RGB (0...511), the center value is 256, the range allows for both increase and reduction of brightness. Analog Contrast for external RGB (0...511) h'13a h'13b 1) 256 350 ABR ACT The white drive values will become active only after writing the blue value WDB, latching of new values is indicated by setting the MSB of WDB. FP Display Control Register, BCL h'144 h'142 h'143 h'145 h'105 BCL threshold current, 0...2047 (max ADC output ~1152) BCL time constant 0...15 13 ... 1700 msec BCL loop gain. 0..15 BCL minimum contrast 0 ...1023 Test register for BCL/EHT comp. function, register value: 0 normal operation 1 stop ADC offset compensation x>1 use x in place of input from Measurement ADC FP Display Control Register, Deflection h'103 h'102 interlace offset, -2048 ...2047 This value is added to the SAWTOOTH output during one field. discharge sample count for deflection retrace, SAWTOOTH DAC output impedance is reduced for DSCC lines after vertical retrace. vertical discharge value, SAWTOOTH output value during discharge operation, typically same as A0 init value for sawtooth. EHT (electronic high tension) compensation coefficient, 0...511 EHT time constant. 0 ..15 3.2 ...410 msec 0 7 INTLC DSCC 1000 15 0 307 0 BCLTHR BCLTM BCLG BCLMIN BCLTST h'11f -1365 DSCV h'10b h'10a 0 15 EHT EHTTM Micronas 27 VPC 3205C, VPC 3215C Control registers, continued FP Subaddress Function FP Display Control Register FP Display Control Register, Vertical Sawtooth h'110 h'11b h'11c h'11d h'11e DC offset of SAWTOOTH output This offset is independent of EHT compensation. accu0 init value accu1 init value accu2 init value accu3 init value FP Display Control Register, East-West Parabola h'12b h'12c h'12d h'12e h'12f accu0 init value accu1 init value accu2 init value accu3 init value accu4 init value PRELIMINARY DATA SHEET Default Name 0 -1365 900 0 0 OFS A0 A1 A2 A3 -1121 219 479 -1416 1052 A0 A1 A2 A3 A4 28 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C 3.2.2. Scaler Adjustment In case of linear scaling, most of the scaler registers need not be set. Only the scaler mode, active video length, and the fixed scaler increments (scinc1/scinc2) must be written. The adjustment of the scaler for nonlinear scaling modes should use the parameters given in table 3-5. An example for `panorama vision' mode with 13.5 MHz line-locked clock is depicted in Fig. 3-2. The figure shows the scaling of the input signal and the variation of the scaling factor during the active video line. The scaling factor starts below 1, i.e. for the borders the video data is expanded by scaler 2. The scaling factor becomes one and compression scaling is done by scaler 1. When the picture center is reached, the scaling factor is held constant. At the second border the scaler increment is inverted and the scaling factor changes back symmetrically. The picture indicates the function of the scaler increments and the scaler window parameters. The correct adjustment requires that pixel counts for the respective windows are always in number of output samples of scaler 1 or 2. 3.2.1. Calculation of Vertical and East-West Deflection Coefficients In Table 3-4 the formula for the calculation of the deflection initialization parameters from the polynominal coefficients a,b,c,d,e is given for the vertical and East-West deflection. Let the polynomial be P = a + b(x - 0.5) + c(x - 0.5)2 + d(x - 0.5)3 + e(x - 0.5)4 The initialization values for the accumulators a0..a3 for vertical deflection and a0..a4 for East-West deflection are 12-bit values. The coefficients that should be used to calculate the initialization values for different field frequencies are given below, the values must be scaled by 128, i.e. the value for a0 of the 50 Hz vertical deflection is a0 = (a * 128 - b * 1365.3 + c * 682.7 - d * 682.7) / 128 Table 3-4: Tables for the Calculation of Initialization values for Vertical Sawtooth and East-West Parabola Vertical Deflection 50 Hz a a0 a1 a2 a3 Vertical Deflection 60 Hz a a0 a1 a2 a3 128 b -1365.3 1083.5 c +682.7 -1090.2 429.9 d -682.7 +1645.5 -1305.8 1023.5 a3 a4 125.6 -2046.6 1584.8 a0 a1 a2 a 128 East-West Deflection 50 Hz d -682.7 +1363.4 -898.4 585.9 a0 a1 a2 a3 a4 a 128 b -341.3 111.9 c 1365.3 -899.6 586.8 d -85.3 84.8 -111.1 72.1 e 341.3 -454.5 898.3 -1171.7 756.5 b -1365.3 899.6 c +682.7 -904.3 296.4 128 East-West Deflection 60 Hz b -341.3 134.6 c 1365.3 -1083.5 849.3 d -85.3 102.2 -161.2 e 341.3 -548.4 1305.5 Micronas 29 VPC 3205C, VPC 3215C PRELIMINARY DATA SHEET border center border input signal video signal output signal scinc compression ratio scinc1 scinc2 expansion (scaler2) scaler window 0 cutpoints 1 compression (scaler1) 1 2 compression (scaler1) 3 expansion (scaler2) 4 Fig. 3-2: Scaler operation for `panorama' mode at 13.5 MHz Table 3-5: Set-up values for nonlinear scaler modes Mode DIGIT3000 (20.25 MHz) `waterglass' border 35% Register scinc1 scinc2 scinc fflim scw1 - 0 scw1 - 1 scw1 - 2 scw1 - 3 scw1 - 4 scw2 - 0 scw2 - 1 scw2 - 2 scw2 - 3 scw2 - 4 center 3/4 1643 1024 90 945 110 156 317 363 473 110 156 384 430 540 center 5/6 1427 1024 56 985 115 166 327 378 493 115 166 374 425 540 `panorama' border 30% center 4/3 center 6/5 1024 376 85 921 83 147 314 378 461 122 186 354 418 540 1024 611 56 983 94 153 339 398 492 118 177 363 422 540 LLC (13.5 MHz) `waterglass' border 35% center 3/4 center 5/6 2464 1024 202 719 104 104 256 256 360 104 104 256 256 360 2125 1024 124 719 111 111 249 249 360 111 111 249 249 360 `panorama' border 30% center 4/3 center 6/5 1024 573 190 681 29 115 226 312 341 38 124 236 322 360 1024 914 126 715 13 117 241 345 358 14 118 242 346 360 30 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C 4. Specifications 4.1. Outline Dimensions 1.1 x 45 9 1 61 0.48 16 x 1.27 0.1 = 20.32 0.1 1.27 0.1 1.2 x 45 0.9 10 2 1.6 9 25.125 0.125 60 1.27 0.1 15 24.22 0.1 2 0.711 9 0.22 0.07 26 27 25.125 0.125 43 44 1.9 4.05 4.75 0.15 0.1 SPGS7004-3/5E Fig. 4-1: 68-Pin Plastic Leaded Chip Carrier Package (PLCC68) Weight approximately 4.8 g Dimensions in mm 4.2. Pin Connections and Short Descriptions NC = not connected LV = if not used, leave vacant X = obligatory; connect as described in circuit diagram Pin No. PLCC 68-pin Pin Name Type Connection (if not used) Short Description 1 2 3 4 5 6 7 9 10 12 13 14 15 GNDF GNDF CLK5 VSTBY XTAL2 XTAL1 GNDF GNDP INTLC VS FSY MSY/HS HELPER SUPPLY SUPPLY OUT SUPPLY OUT IN SUPPLY SUPPLY OUT OUT OUT IN/OUT OUT X X LV X X X X X LV LV LV LV LV Ground, Analog Front-End Ground, Analog Front-End CCU 5 MHz Clock Output Standby Supply Voltage Analog Crystal Output Analog Crystal Input Ground, Analog Front-End Ground, Output Pad Circuitry Interlace Output Vertical Sync Pulse Front Sync Pulse Main Sync/Horizontal Sync Pulse Helper Line Output Micronas 16 x 1.27 0.1 = 20.32 0.1 23.4 24.22 0.1 31 VPC 3205C, VPC 3215C PRELIMINARY DATA SHEET Pin No. PLCC 68-pin Pin Name Type Connection (if not used) Short Description 16 17 18 19 20 21 22 23 24 25 26 28 29 30 31 34 35 36 38 39 40 41 42 43 46 47 48 49 50 51 52 HC AVO LLC2 LLC1 Y7 Y6 Y5 Y4 Y3 Y2 GNDP Y1 Y0 CLK20 VSUPD GNDD GNDP VSUPP C7 C6 C5 C4 C3 C2 C1 C0 PR0 PR1 PR2 GNDP VGAV IN/OUT OUT OUT IN/OUT OUT OUT OUT OUT OUT OUT LV LV LV LV GNDP GNDP GNDP GNDP GNDP GNDP X Horizontal Clamp Pulse Active Video Output Double Output Clock Output Clock Picture Bus Luma (MSB) Picture Bus Luma Picture Bus Luma Picture Bus Luma Picture Bus Luma Picture Bus Luma Ground, Output Pad Circuitry Picture Bus Luma Picture Bus Luma (LSB) Main Clock Output 20.25 MHz Supply Voltage, Digital Circuitry Ground, Digital Circuitry Ground, Output Pad Circuitry Supply Voltage, Output Pad Supply Picture Bus Chroma (MSB) Picture Bus Chroma Picture Bus Chroma Picture Bus Chroma Picture Bus Chroma Picture Bus Chroma Picture Bus Chroma Picture Bus Chroma (LSB) Picture Bus Priority (LSB) Picture Bus Priority Picture Bus Priority (MSB) Ground, Output Pad Circuitry VGAV Input OUT OUT IN/OUT SUPPLY SUPPLY SUPPLY SUPPLY OUT OUT OUT OUT OUT OUT OUT OUT IN/OUT IN/OUT IN/OUT SUPPLY IN GNDP GNDP LV X X X X GNDP GNDP GNDP GNDP GNDP GNDP GNDP GNDP LV LV LV X GNDP 32 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C Pin No. PLCC 68-pin Pin Name Type Connection (if not used) Short Description 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 8, 11 27, 32 33, 37 44, 45 FPDAT RESQ SDA SCL TEST VIN4 GNDF VIN3 VIN2 VIN1 CIN VOUT ASGF VSUPF ISGND VRT NC IN/OUT IN IN/OUT IN/OUT IN IN SUPPLY IN IN IN IN OUT LV X X X GNDD VRT X VRT VRT VRT* LV* LV X Front-End/Back-End Data Reset Input, Active Low I2C Bus Data I2C Bus Clock Test Pin, connect to GNDD Video 4 Analog Input Ground, Analog Front-End Video 3 Analog Input Video 2 Analog Input Video 1 Analog Input Chroma/Video 4 Analog Input Analog Video Output Analog Shield GNDF Supply Voltage, Analog Front-End Signal Ground for Analog Input, connect to GNDF Reference Voltage Top, Analog Not connected SUPPLY SUPPLY OUTPUT - X X X LV OR GNDD *) chroma selector must be set to 1 (CIN chroma select) 4.3. Pin Descriptions (pin numbers for PLCC68 package) Pin 1 - Ground, Analog Front-End GNDF Pin 2 - Ground, Analog Front-End GNDF Pin 3 - CCU 5 MHz Clock Output CLK5 (Fig. 4-11) This pin provides a clock frequency for the TV microcontroller, e.g. a CCU 3000 controller. It is also used by the DDP 3300A display controller as a standby clock. Pin 4 - Standby Supply Voltage VSTDBY In standby mode, only the clock oscillator is active, GNDF should be ground reference. Please activate RESQ before powering-up other supplies Pins 6 and 5 - XTAL1 Crystal Input and XTAL2 Crystal Output (Fig. 4-8) These pins are connected to an 20.25 MHz crystal oscillator which is digitally tuned by integrated shunt capacitances. The CLK20 and CLK5 clock signals are derived from this oscillator. An external clock can be fed into XTAL1. In this case, clock frequency adjustment must be switched off. Pin 7 - Ground, Analog Front-End GNDF Pin 9 - Ground, Output Pad Circuitry GNDP Pin 10 - Interlace Output, INTLC (Fig. 4-4) This pin supplies the interlace information, 0 indicates first field, 1 indicates second field. Micronas 33 VPC 3205C, VPC 3215C Pin 12 - Vertical Sync Pulse, VS (Fig. 4-4) This pin supplies the vertical sync signal. Pin 13 - Front Sync Pulse, FSY (Fig. 4-4) This pin supplies the front sync information. Pin 14 - Main Sync/Horizontal Sync Pulse MSY/HS (Fig. 4-4) This pin supplies the horizontal sync pulse information in line-locked mode. In DIGIT3000 mode, this pin is the main sync input. Pin 15 - Helper Line Output, Helper (Fig. 4-4) This signal indicates a helper line in PAL+ mode. Pin 16 - Horizontal Clamp Pulse, HC (Fig. 4-4) This signal can be used to clamp an external video signal, that is synchronous to the input signal. The timing is programmable. Pin 17 - Active Video Output, AVO (Fig. 4-4) This pin indicates the active video output data. The signal is clocked with the LLC1 clock. Pin 18 - Double Output Clock, LLC2 (Fig. 4-6) PRELIMINARY DATA SHEET Pin 51 - Ground, Output Pad Circuitry GNDP Pin 52 - VGAV-Input. (Fig. 4-3) This pin is connected to the vertical sync signal of a VGA signal. Pin 53 - Front-End/Back-End Data FPDAT (Fig. 4-6) This pin interfaces to the DDP 3300A back-end processor. The information for the deflection drives and for the white drive control, i.e. the beam current limiter, is transmitted by this pin. Pin 54 - Reset Input RESQ (Fig. 4-3) A low level on this pin resets the VPC 32xx. Pin 55 - I2C Bus Data SDA (Fig. 4-13) This pin connects to the I2C bus data line. Pin 56 - I2C Bus Clock SCL (Fig. 4-3) This pin connects to the I2C bus clock line. Pin 57 - Test Input TEST (Fig. 4-3) This pin enables factory test modes. For normal operation, it must be connected to ground. Pin 59 - Ground, Analog Front-End GNDF Pin 19 - Output Clock, LLC1 (Fig. 4-6) This is the clock reference for the luma, chroma, and status outputs. Pin 26 - Ground, Output Pad Circuitry GNDP Pins 20 to 25,28,29 - Luma Outputs Y0 - Y7 (Fig. 4-4) These output pins carry the digital luminance data. The data are clocked with the LLC1 clock. Pin 30 - Main Clock Output CLK20 (Fig. 4-5) This is the 20.25 MHz main clock output. Pin 31 - Supply Voltage, Digital Circuitry VSUPD Pin 34 - Ground, Digital Circuitry GNDD Pin 35 - Ground, Output Pad Circuitry GNDP Pin 36 - Supply Voltage, Output Pad Supply VSUPP Pins 62,61,60,58 - Video Input 1-4 (Fig. 4-12) These are the analog video inputs. A CVBS or S-VHS luma signal is converted using the luma (Video 1) AD converter. The VIN1 input can also be switched to the chroma (Video 2) ADC. The input signal must be AC-coupled. Pin 63 - Chroma Input CIN (Fig. 4-10) This pin is connected to the S-VHS chroma signal. A resistive divider is used to bias the input signal to the middle of the converter input range. CIN can only be connected to the chroma (Video 2) A/D converter. The signal must be AC-coupled. Pin 64 - Analog Video Output, VOUT (Fig. 4-7) The analog video signal that is selected for the main (luma, CVBS) ADC is output at this pin. An emitter follower is required at this pin. Pin 65 - Ground, Analog Shield Front-End GNDF Pins 38 to 43,46,47 - Chroma Outputs C0-C7 (Fig. 4-4) These outputs carry the digital CrCb chrominance data. The data are clocked with the LL1 clock. The data are sampled at half the clock rate and multiplexed. The CrCb multiplex is reset for each TV line. Pins 48 to 50 - Picture Bus Priority PR0-PR2 (Fig. 4-6) The Picture Bus Priority lines carry the digital priority selection signals. The priority interface allows digital switching of up to 8 sources to the back-end processor. Switching for different sources is prioritized and can be on a per pixel basis. Pin 66 - Supply Voltage, Analog Front-End VSUPF (Fig. 4-9) Pin 67 - Signal GND for Analog Input ISGND (Fig. 4- 11) This is the high quality ground reference for the video input signals. Pin 68 - Reference Voltage Top VRT (Fig. 4-9) Via this pin, the reference voltage for the A/D converters is decoupled. The pin is connected with 10 F/47 nF to the Signal Ground Pin. 34 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C 4.4. Pin Configuration GNDF GNDF CLK5 VSTBY XTAL2 XTAL1 GNDF NC GNDP VRT ISGND VSUPF ASGF VOUT CIN VIN1 VIN2 9 INTLC NC VS FSY MSY/HS HELPER HC AVO LLC2 LLC1 Y7 Y6 Y5 Y4 Y3 Y2 GNDP 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 VIN3 GNDF VIN4 TEST SCL SDA RESQ FPDAT VGAV GNDP PR2 PR1 PR0 C0 C1 NC NC VPC 32x5C 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 NC Y1 Y0 CLK20 VSUPD NC NC GNDD GNDP NC VSUPP C7 C6 C5 C4 C3 C2 Fig. 4-2: 68-pin PLCC package Micronas 35 VPC 3205C, VPC 3215C 4.5. Pin Circuits VSUPD 0.5M PRELIMINARY DATA SHEET P P VSTBY N GNDD Fig. 4-3: Input pins RESQ, TEST, VGAV - + N f ECLK GNDF Fig. 4-8: Input/Output Pins XTAL1, XTAL2 VSUPF P VRT ADC Reference V SUPD P P V SUPP Vref N N GND P Fig. 4-4: Output pins C0-C7, Y0-Y7, FSY, HC, AVO, HELPER, VS, INTLC, HS, LLC1, LLC2 Fig. 4-9: Pins VRT, ISGND ISGND VSUPF To ADC GNDF Fig. 4-10: Chroma input CIN VSUPD P P N N GNDD P VSTBY Fig. 4-5: Output pin CLK20 N VSUPD P GNDF Fig. 4-11: Output pin CLK5 N N GNDD VSUPF To ADC Fig. 4-6: Input/Output pins PR0-PR2, FPDAT GNDF Vin's - + VSUPF P VOUT VREF N GNDF Fig. 4-7: Output pin VOUT GNDD Fig. 4-13: Pins SDA, SCL Fig. 4-12: Input pins VIN1-VIN4 36 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C 4.6. Electrical Characteristics 4.6.1. Absolute Maximum Ratings Symbol TA TS VSUP VI VO Parameter Ambient Operating Temperature Storage Temperature Supply Voltage, all Supply Inputs Input Voltage, all Inputs Output Voltage, all Outputs Pin No. - - - - - Min. 0 -40 -0.3 -0.3 -0.3 Max. 65 125 6 VSUP+0.3 VSUP+0.3 Unit C C V V V Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions/Characteristics" of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 4.6.2. Recommended Operating Conditions Symbol TA VSUP VSUPP fXTAL Parameter Ambient Operating Temperature Supply Voltages, all Supply Pins Supply Volt., Output Pad Supply Clock Frequency Pin Name - - VSUPP XTAL1/2 Min. 0 4.75 3.15 - Typ. - 5.0 - 20.25 Max. 65 5.25 5.25 - Unit C V V MHz Micronas 37 VPC 3205C, VPC 3215C 4.6.3. Recommended Crystal Characteristics PRELIMINARY DATA SHEET Symbol TA fP Parameter Operating Ambient Temperature Parallel Resonance Frequency with Load Capacitance CL = 13 pF Accuracy of Adjustment Frequency Temperature Drift Series Resistance Shunt Capacitance Motional Capacitance Min. 0 - - - - 3 20 Typ. - 20.250000 - - - - - Max. 65 - Unit C MHz ppm ppm fP/fP fP/fP RR C0 C1 20 30 25 7 30 pF fF Load Capacitance Recommendation CLext External Load Capacitance 1) from pins to Ground (pin names: Xtal1 Xtal2) - 3.3 - pF DCO Characteristics 2,3) CICLoadmin Effective Load Capacitance @ min. DCO-Position, Code 0, package: 68PLCC Effective Load Capacitance Range, DCO Codes from 0..255 3 4.3 5.5 pF CICLoadrng 1) 11 12.7 15 pF Remarks on defining the External Load Capacitance: External capacitors at each crystal pin to ground are required. They are necessary to tune the effective load capacitance of the PCBs to the required load capacitance CL of the crystal. The higher the capacitors, the lower the clock frequency results. The nominal free running frequency should match fp MHz. Due to different layouts of customer PCBs the matching capacitor size should be determined in the application. The suggested value is a figure based on experience with various PCB layouts. Tuning condition: Code DVCO Register=-720 2) Remarks on Pulling Range of DCO: The pulling range of the DCO is a function of the used crystal and effective load capacitance of the IC (CICLoad +CLoadBoard). The resulting frequency fL with an effective load capacitance of CLeff = CICLoad + CLoadBoard is: 1 + 0.5 * [ C1 / (C0 + CL) ] fL = fP * _______________________ 1 + 0.5 * [ C1 / (C0 + CLeff) ] 3) Remarks on DCO codes The DCO hardware register has 8 bits, the fp control register uses a range of -2048...2047 38 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C 4.6.4. Characteristics at TA = 0 to 65 C, VSUPD/F = 4.75 to 5.25 V, VSUPP = 3.15 to 3.5V f = 20.25 MHz for min./max. values at TC = 60 C, VSUPD/F = 5 V, Vsupp = 3.15V f = 20.25 MHz for typical values Symbol PTOT IVSUPA IVSUPD IVSUPP IVSTDBY IL Parameter Total Power Dissipation Current Consumption Current Consumption Current Consumption Current Consumption Input / Output Leakage Current Pin Name - VSUPF VSUPD VSUPP VSTDBY All I/O Pins Min. - - - - - -1 Typ. 1.15 40 160 40 1 - Max. 1.5 - - - - 1 Unit W mA mA mA mA A 4.6.4.1. Characteristics, 5 MHz Clock Output Symbol VOL VOH tOT Parameter Output Low Voltage Output High Voltage Pin Name CLK5 Min. - 4.0 Typ. - - Max. 0.4 V- STDBY - Unit V V Test Conditions IOL = 0.4 mA -IOL = 0.9 mA CLOAD = 30 pF Output Transition Time - 50 ns 4.6.4.2. Characteristics, 20 MHz Clock Input/Output, External Clock Input (XTAL1) Symbol VDCAV VPP tOT VIT VI Parameter DC Average Pin Name CLK20 Min. VSUP/2 - 0.3 1.3 - 2.1 XTAL1 1.3 Typ. VSUP/2 1.6 - 2.5 - Max. VSUP/2 + 0.3 - 18 2.9 - Unit V Test Conditions CLOAD = 30 pF CLOAD = 30 pF CLOAD = 30 pF only for test purposes capacitive coupling used, XTAL2 open VOUT Peak to Peak Output Transition Time Input Trigger Level Clock Input Voltage V ns V VPP 4.6.4.3. Characteristics, Reset Input, Test Input Symbol VIL VIH Parameter Input Low Voltage Input High Voltage Pin Name RESQ TEST Min. - 3.0 Typ. - - Max. 1.5 - Unit V V Test Conditions Micronas 39 VPC 3205C, VPC 3215C 4.6.4.4. Characteristics, Priority, FPDAT Input/Output Symbol VOL Parameter Output Low Voltage Pin Name PR[2:0] FPDAT Min. - Typ. - Max. 0.5 PRELIMINARY DATA SHEET Unit V Test Conditions IOL = 14.4 mA, strength 0 IOL = 10.8 mA, strength 1 IOL = 7.2 mA, strength 2 IOL = 3.6 mA, strength 3 note: FPDAT strength = 2 -IOL = 10 A CLOAD = 70 pF VOH tOH tODL Output High Voltage 1.8 2.0 2.5 V Output Hold Time Output Delay Time 6 - - - - 35 ns ns CLOAD = 70 pF IL = 14.4 mA strength = 3 VOL = 0 V IPL VIL VIH tIS tIH Output Pull-up Current Input Low Voltage Input High Voltage Input Setup Time Input Hold Time PR[2:0] FPDAT 1.2 - 1.5 7 5 1.5 - - - - 1.5 0.8 - - - mA V V ns ns 20.25 MHz Clock tIS tIH Priority Bus Input VIH VIL tOH tOH Priority Bus Output tODL VOHTRI VOL Fig. 4-14: Priority, FPDAT input/output 4.6.4.5. Characteristics, VGAV Input Symbol VIL VIH Parameter Input Low Voltage Input High Voltage Pin Name VGAV Min. - 2.0 Typ. - - Max. 0.8 - Unit V V Test Conditions 40 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C 4.6.4.6. Characteristics, I2C Bus Interface Symbol VIL VIH VOL VIH tF tR fSCL tLOW tHIGH tSU Data tHD Data Parameter Input Low Voltage Input High Voltage Output Low Voltage Pin Name SDA, SCL Min. - 3.0 - Typ. - - - Max. 1.5 - 0.4 0.6 5 300 300 400 - - - 0.9 Unit V V V V pF ns ns kHz CL = 400 pF CL = 400 pF Il = 3 mA Il = 6 mA Test Conditions Input Capacitance Signal Fall Time Signal Rise Time Clock Frequency Low Period of SCL High Period of SCL Data Set Up Time to SCL high DATA Hold Time to SCL low SDA SCL - - - 0 1.3 0.6 100 0 - - - - - - - - s s ns s 4.6.4.7. Characteristics, Analog Video Inputs Symbol VVIN Parameter Analog Input Voltage Pin Name VIN1, VIN2 VIN3, VIN4 CIN VIN1, VIN2 VIN3, VIN4 CIN Min. 0 Typ. - Max. 3.5 Unit V Test Conditions CCP CCP Input Coupling Capacitor Video Inputs Input Coupling Capacitor Chroma Input - 680 - nF - 1 - nF 4.6.4.8. Characteristics, Analog Front-End and ADCs Symbol VVRT Luma - Path RVIN CVIN VVIN VVIN AGC DNLAGC Input Resistance Input Capacitance Full Scale Input Voltage Full Scale Input Voltage AGC step width AGC Differential Non-Linearity VIN1 VIN2 VIN3 VIN4 VIN1 VIN2 VIN3 VIN4 1 - 1.8 0.5 - - - 5 2.0 0.6 0.166 - - - 2.2 0.7 - M pF VPP VPP dB LSB min. AGC Gain max. AGC Gain 6-Bit Resolution= 64 Steps fsig=1MHz, - 2 dBr of max. AGC-Gain Code Clamp-DAC=0 Parameter Reference Voltage Top Pin Name VRT Min. 2.5 Typ. 2.6 Max. 2.8 Unit V Test Conditions 10 F/10 nF, 1 G Probe 0.5 Micronas 41 VPC 3205C, VPC 3215C PRELIMINARY DATA SHEET Symbol VVINCL QCL ICL-LSB DNLICL Chroma - Path RCIN VCIN VCINDC Parameter Input Clamping Level, CVBS Pin Name VIN1 VIN2 VIN3 VIN4 Min. - Typ. 1.0 Max. - Unit V Test Conditions Binary Level = 64 LSB min. AGC Gain 5 Bit - I-DAC, bipolar VVIN=1.5 V Clamping DAC Resolution Input Clamping Current per step Clamping DAC Differential NonLinearity -16 0.7 - 1.0 - 15 1.3 steps A LSB 0.5 Input Resistance SVHS Chroma Full Scale Input Voltage, Chroma Input Bias Level, SVHS Chroma Binary Code for Open Chroma Input CIN VIN1 1.4 2.0 2.6 k 1.08 1.2 1.32 VPP V - 1.5 - - 128 - - Dynamic Characteristics for all Video-Paths (Luma + Chroma) BW XTALK THD Bandwith Crosstalk, any Two Video Inputs Total Harmonic Distortion VIN1 VIN2 VIN3 VIN4 8 - - 10 -56 50 - - - MHz dB dB -2 dBr input signal level 1 MHz, -2 dBr signal level 1 MHz, 5 harmonics, -2 dBr signal level 1 MHz, all outputs, -2 dBr signal level Code Density, DC-ramp SINAD Signal to Noise and Distortion Ratio Integral Non-Linearity Differential Non-Linearity Differential Gain Differential Phase - 45 - dB INL DNL DG DP - - - - - - - - 1 0.8 3 1.5 LSB LSB % deg -12 dBr, 4.4 MHz signal on DC-ramp Analog Video Output VOUT AGCVOUT DNLAGC VOUTDC BW Output Voltage AGC step width, VOUT AGC Differential Non-Linearity DC-level VOUT Bandwidth VOUT Total Harmonic Distortion Out: VOUT In: VIN1 VIN2 VIN3 VIN4 1.7 - - - 8 2.0 1.333 - 1 10 2.3 - VPP dB LSB V MHz clamped to Back porch Input: -2 dBr of main ADC range, CL10 pF Input: -2 dBr of main ADC range, CL10 pF 1 MHz, 5 Harmonics VIN = 1 VPP, AGC= 0 dB 3 Bit Resolution=7 Steps 3 MSB's of main AGC 0.5 - - THD - - -40 dB CLVOUT ILVOUT Load Capacitance Output Current VOUT - - - - 10 pF mA 0.1 42 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C 4.6.4.9. Characteristics, Output Pin Specification Output Specification for SYNC, CONTROL, and DATA Pins: Y[7:0], C[7:0], AVO, HS, HC, HELPER, INTLC, VS, FSY Symbol VOL VOH tOH tOD Parameter Output Low Voltage Output High Voltage Output Hold Time Output Delay Time Pin Name - - - - Min. - 2.4 6 - Typ. - - - - Max. 0.4 - - 35 Unit V V ns ns NOTE 1 Test Conditions see table below see table below NOTE 1: CLOAD depends on the selected driver strength which is I2C-programmable. Table 4-1: Driver strength Strength 000 001 010 011 100 101 110 111 VSUPP = 5 V Load < 100 pF < 55 pF < 37 pF < 28 pF < 23 pF < 18 pF < 14 pF pins tristate VSUPP = 3.3 V Load < 50 pF < 28 pF < 20 pF < 14 pF < 12 pF < 10 pF < 8 pF CLK20 20.25 MHz in case of DIGIT3000 mode LLC1 13.5 MHz in case of LLC Mode 2.0 V tR, tF 5 ns 0.8 V VOH Output Data valid tOH tOD Data valid VOL Fig. 4-15: Sync, control, and data outputs Micronas 43 VPC 3205C, VPC 3215C 4.6.4.10. Characteristics, Input Pin Specification PRELIMINARY DATA SHEET Input Specification for SYNC, CONTROL, and DATA Pin: MSY (DIGIT3000 mode only) Symbol VIL VIH tIS tIH Parameter Input Low Voltage Input High Voltage Input Setup Time Input Hold Time Pin Name - - - - Min. - 1.5 7 5 Typ. - - - - Max. 0.8 - - - Unit V V ns ns Test Conditions CLK20 20.25 MHz in case of DIGIT3000 Mode VIH Input tIS Data valid tIH VIL 2.0 V tR, tF 5ns 0.8 V VIH LLC1 13.5 MHz in case of LLC Mode Input tIS Data valid tIH VIL Fig. 4-16: Sync, control, and data inputs 44 Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C 4.6.4.11. Characteristics, Clock Output Specification Line-Locked Clock Pins: LLC1, LLC2 Symbol CL Parameter Load capacitance Pin Name - Min. - Typ. - Max. 50 Unit pF Test Conditions 13.5 MHz Line Locked Clock 1/T13 tWL13 tWH13 1/T27 tWL27 tWH27 LLC1 Clock Frequency LLC1 Clock Low Time LLC1 Clock High Time LLC2 Clock Frequency LLC2 Clock Low Time LLC2 Clock High Time - - - - - - 12.5 26 26 25 10 10 - - - - - - 14.5 - - 29 - - MHz ns ns MHz ns ns CL = 30 pF CL = 30 pF CL = 30 pF CL = 30 pF 16 MHz Line Locked Clock 1/T13 LLC1 Clock Frequency - 14.8 - 17.2 MHz 18 MHz Line Locked Clock 1/T13 LLC1 Clock Frequency - 16.6 - 19.4 MHz common timings - all modes tSK tR, tF VIL VIH VOL VOH Clock Skew Clock Rise/Fall Time Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage - - - - - - 0 - - 2.0 - 2.4 - - - - - - 4 5 0.8 - 0.4 - ns ns V V V V IL = 2 mA IH = -2 mA CL = 30 pF T13 tWH13 tWL13 LLC1 (13.5 MHz 7%) tR tWH27 tWL27 tF tSK T27 tSK VIH VIL LLC2 (27 MHz 7%) tR tF VIH VIL Fig. 4-17: Line-locked clock output pins Micronas 45 VPC 3205C, VPC 3215C 5. Application Circuit PRELIMINARY DATA SHEET 46 VPC 32x5C Micronas PRELIMINARY DATA SHEET VPC 3205C, VPC 3215C 5.1. VGA mode with VPC3215C In 100 Hz TV applications it can be desirable to display a VGA-signal on the TV. In this case a VGA-graphic card delivers the H, V and RGB signals. These signals can be feed "directly" to the backend signal processing. The VPC can generate a stable line locked clock for the 100 Hz system in relation to the VGA sync signals. While the V-sync is connected to the VGAV pin directly, the H-sync has to be pulse-shaped and amplitude adjusted until it is connected to one of the video input pins of the VPC. The recommended circuitry to filter the H sync is given in the figure below. +5V analog 47pF 1k 270 H 31kHz 540 BC848B 1N4148 2k 1N4148 GND analog GND analog 100 680 nF Video Input VPC Fig. 5-1: Application circuit for horizontal VGA-input Micronas 47 VPC 3205C, VPC 3215C 6. Data Sheet History 1. Preliminary data sheet: "VPC 3205C, VPC 3215C Video Processor Family, Aug. 15, 1997 6251-457-1PD. First release of the preliminary data sheet. 2. Preliminary data sheet: "VPC 3205C, VPC 3215C Video Processor Family, Oct. 19, 1998, 6251-457-2PD. Second release of the preliminary data sheet. Major changes: - Fig. 4-1: Outline Dimensions for PLCC68 changed. - Additional information contained in Supplement No.3 / 6251-457-3PDS, Edition May 25 1998 has been included. PRELIMINARY DATA SHEET Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-457-2PD All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH. 48 Micronas |
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