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| FA5304AP(S)/FA5305AP(S) s Description The FA5304AP(S) and FA5305AP(S) are bipolar ICs for switching power supply control and can directly drive a power MOSFET. These ICs contain many functions in a small 8-pin package. With these ICs, a high-performance power supply can be created compactly because not many external components are needed. Bipolar IC For Switching Power Supply Control FA5304AP(S)/FA5305AP(S) s Dimensions, mm SOP-8 8 5 s Features * Drive circuit for connecting a power MOS-FET (IO = 1.5A) * Wide operating frequency range (5 to 600kHz) * Pulse-by-pulse overcurrent limiting function Positive voltage detection: FA5304AP(S) Negative voltage detection: FA5305AP(S) * Overload cutoff function (Latch or non-protection mode selectable) * Output ON/OFF control function by external signals * Overvoltage cutoff function in latch mode * Undervoltage malfunction prevention function (ON at 16V and OFF at 8.7V) * Error amplifier for control by tertiary winding detection * Low standby current (90A typ.) * 8-pin package (DIP/SOP) 1 6.05 4 +0.1 -0.05 8.20.3 5.3 0~10 0.40.1 1.270.2 0.6 DIP-8 8 5 s Applications * Switching power supply for general equipment 1 9.3 1.5 4 6.5 3.0min 4.5max 3.4 0.3 7.6 2.540.25 0.50.1 0~15 0~1 5 2.0max +0.1 5 -0.0 0.20 1 FA5304AP(S)/FA5305AP(S) s Block diagram FA5304AP(S) Pin No. 1 2 3 4 5 6 7 8 Pin symbol Description Inverting input to error amplifier Error amplifier output Overcurrent (+) detection Ground Output Power supply Oscillator timing capacitor Soft-start and ON/OFF control IN (-) FB IS (+) GND OUT VCC CT CS FA5305AP(S) Pin No. 1 2 3 4 5 6 7 8 Pin symbol Description Inverting input to error amplifier Error amplifier output Overcurrent (-) detection Ground Output Power supply Oscillator timing capacitor Soft-start and ON/OFF control IN (-) FB IS (-) GND OUT VCC CT CS 2 FA5304AP(S)/FA5305AP(S) s Absolute maximum ratings Common to FA5304AP(S) and FA5305AP(S) Item Supply voltage Output current Error amplifier input voltage Feedback terminal input voltage Overcurrent detection terminal input voltage CS terminal input current Total power dissipation (Ta = 25C) Operating temperature Storage temperature Symbol Rating 30 1.5 4 4 -0.3 to +4 2 800 (DIP-8) *1 550 (SOP-8) *2 -30 to +85 -40 to +150 Unit V A V V V mA mW C C Notes: * 1 Derating factor Ta > 25C : 8.0mW/C ( on PC board ) * 2 Derating factor Ta > 25C : 5.5mW/C ( on PC board ) s Recommended operating conditions Common to FA5304AP(S) and FA5305AP(S) Item Supply voltage Symbol Min. 10 100 0.1 5 1 600 Max. 30 Unit V k VCC IO VIN VFB VIS ICS Pd Topr Tstg VCC Error amplifier feedback resistor RNF Soft-start capacitor CS Oscillation frequency fOSC F kHz s Electrical characteristics (Ta=25C, VCC=18V,fosc=135kHz) Oscillator section Item Oscillation frequency Frequency variation 1 (due to supply voltage change) Frequency variation 2 (due to temperature change) Common to FA5304AP(S) and FA5305AP(S) Symbol Test condition Min. 112 Typ. 135 1 4 Max. 148 Unit kHz % % fOSC fdv fdT CT = 360pF VCC = 10 to 30V Ta = -30 to +85C Error amplifier section Item Reference voltage Input bias current Open-loop voltage gain Unity-gain bandwidth Maximum output voltage (Pin 2) Output source current (Pin 2) Common to FA5304AP(S) and FA5305AP(S)) Symbol Test condition Min. 1.90 -500 80 1.0 Typ. 2.00 -50 Max. 2.10 Unit V nA dB MHz V 200 -100 -50 mV VB IB AV fT VOM+ VOM- IMO+ V1 = 2V RNF = 100k RNF = 100k VOM = 1V 2.70 A Pulse width modulation circuit section Item Input threshold voltage (Pin 2) Maximum duty cycle Common to FA5304AP(S) and FA5305AP(S) Symbol Test condition Duty cycle = 0% Duty cycle = DMAX Min. 0.80 1.70 42 Typ. 1.00 1.90 45 Max. 1.20 2.10 50 Unit V V % VTH FBO VTH FBM DMAX Soft-start circuit section Item Charge current (Pin 8) Input threshold voltage (Pin 8) Common to FA5304AP(S) and FA5305AP(S) Symbol Test condition Pin 8 = 0V Duty cycle = 0% Duty cycle = DMAX Min. -15 0.80 1.70 Typ. -10 1.00 1.90 Max. -5 1.20 2.10 Unit ICHG VTH CSO VTH CSM A V V 3 FA5304AP(S)/FA5305AP(S) Overcurrent limiting circuit section Item Input threshold voltage (Pin 3) Overcurrent detection terminal source current Delay time Symbol Test condition FA5304AP(S) Min. Typ. 0.24 150 0.20 Pin 3 = 0V 0.28 FA5305AP(S) Max. Min. Typ. Max. Unit VTH IS IIS TPD IS -0.20 -0.17 -0.14 V -300 -200 -100 -240 -160 -80 200 A ns Latch-mode cutoff circuit section Item CS terminal sink current Cutoff threshold voltage (Pin 8) Common to FA5304AP(S) and FA5305AP(S) Symbol Test condition Pin 8 = 6V, Pin 2 = 1V Min. 40 6.5 Typ. 70 7.0 Max. 150 7.5 Unit ISINK CS VTH CS A V Overload cutoff circuit section Item Cutoff threshold voltage (Pin 2) Common to FA5304AP(S) and FA5305AP(S) Symbol Test condition Min. 2.5 Typ. 2.7 Max. 2.9 Unit V VTH FB Undervoltage lock-out circuit section Common to FA5304AP(S) and FA5305AP(S) Item OFF-to-ON threshold voltage ON-to-OFF threshold voltage Voltage hysteresis Symbol Test condition Min. 15.5 8.20 Typ. 16.0 8.70 7.30 Max. 16.5 9.20 Unit V V V VTH ON VTH OFF VHYS Output section Common to FA5304AP(S) and FA5305AP(S) Item L-level output voltage H-level output voltage Rise time Fall time Symbol Test condition Min. Typ. 1.30 16.0 16.5 50 50 Max. 1.80 Unit V V ns ns VOL VOH tr tf IO = 100mA IO = -100mA, VCC = 18V No load No load Output ON/OFF control circuit section Common to FA5304AP(S) and FA5305AP(S) Item CS terminal source current OFF-to-ON threshold voltage (Pin 8) ON-to-OFF threshold voltage (Pin 8) Symbol Test condition Pin 8 = 0V CS pin voltage CS pin voltage 0.30 Min. -15 Typ. -10 0.56 0.42 Max. -5 0.76 Unit ISOURCE CS VTH ON VTH OFF A V V Overall device Common to FA5304AP(S) and FA5305AP(S) Item Standby current Operating-state supply current OFF-state supply current Cutoff-state supply current Symbol Test condition Min. Typ. 90 9 1.1 1.1 Max. 150 15 1.8 1.8 Unit ICC ST ICC OP ICC OFF ICCL VCC = 14V A mA mA mA 4 FA5304AP(S)/FA5305AP(S) s Description of each circuit 1. Oscillator (See block diagram on page 8.) The oscillator generates a triangular waveform by charging and discharging a capacitor. CT pin voltage oscillates between an upper limit of approx. 3.0V and a lower limit of approx. 1.0V. The oscillation frequency is determined by a external capacitance CT connected to CT pin, and approximately given by the following equation: f (kHZ) = 4.8 * 104 CT (pF) ..................(1) The recommended oscillation range is between 5k and 600kHz. The oscillator output is connected to a PWM comparator. 2. Feedback circuit Figure 1 gives an example of connection in which built-in error amplifier is used to couple the feedback signal to IN(-) pin. Let n2 be the number of turns of secondary winding L2 and n3 be the number of turns of tertiary winding L3. VCC and Vout are given by Vcc= 2(V)*(R1+R2)/R2....................................(2) VOUT (n2/n3)*(Vcc+VD3)-VD2........................(3) (where VD2 and VD3 are the forward voltage drops across diodes D2 and D3 respectively). Fig. 1 Configuration with error amplifier Here, the following equation must be satisfied to prevent from the malfunction of OUT pin at shutdown. (R1*R2)/ (R1+R2)11k...............................(4) Figure 2 gives an example of connection in which an optocoupler is used to couple the feedback signal to the FB pin. If this circuit causes power supply instability, the frequency gain can be decreased by connecting R4 and C4 as shown in figure 2. R4 should be between several tens of ohms to several kiloohms and C4 should be between several thousand picofarads to one microfarads. Fig. 2 Configuration with optocoupler (FB pin input) 3. PWM comparator The PWM comparator has four inputs as shown in Figure 3. Oscillator output x is compared with CS pin voltage , FB pin , and DT voltage {. The lowest of three inputs , , and { is compared with output x. If it is lower than the oscillator output, the PWM comparator output is high, and if it is higher than the oscillator output, the PWM comparator output is low (see Fig. 4). The IC output voltage is high during when the comparator output is low, and the IC output voltage is low during when the comparator output is high. When the IC is powered up, CS pin voltage controls soft start operation. The output pulse then begins to widen gradually. During normal operation, the output pulse width is determined within the maximum duty cycle (FA5304A, FA5305A: 45%) set by DT voltage { under the condition set by feedback signal , to stabilize the output voltage. Fig. 3 PWM comparator Fig. 4 PWM comparator timing chart 5 FA5304AP(S)/FA5305AP(S) 4. CS pin circuit As shown in Figure 5, capacitor CS is connected to the CS pin. When power is turned on, the constant current source (10A) begins to charge capacitor CS. Accordingly, the CS pin voltage rises as shown in Figure 6. The CS pin is connected to an input of the PWM comparator. The device is in soft-start mode while the CS pin voltage is between 1.0V and 1.9V common to FA5304A and FA5305A. During normal operation, the CS pin is clamped at 3.6V by internal zener diode Zn. If the output voltage drops due to an overload, etc., the clamp voltage shifts from 3.6V to 8.0V. As a result, the CS pin voltage rises to 8.0V. The CS pin is also connected to latch comparator C2. If the pin voltage rises above 7.0V, the output of comparator C2 goes high to turn off the bias circuit , thereby shutting the output down. Comparator C2 can be used not only for shutdown in response to an overload, but also for shutdown in response to an overvoltage. Comparator C1 is also connected to the CS pin, and the bias circuit is turned off and the output is shut down if the CS pin voltage drops below 0.42V. In this way, comparator C1 can also be used for output on/off control. As explained above, the CS pin can be used for soft-start operation, overload and overvoltage output shutdown and output on/off control. Further details on the four functions of the CS pin are given below. 4.1 Soft start function Figure 7 shows the soft start circuit. Figure 8 is the soft-start operation timing chart. The CS pin is connected to capacitor CS . When power is turned on, a 10A constant-current source begins to charge the capacitor. As shown in the timing chart, the CS pin voltage rises slowly in response to the charging current. The CS pin is connected internally to the PWM comparator. The comparator output pulse slowly widens as shown in the timing chart. The soft start period can be approximately evaluated by the period ts from the time the IC is activated to the time the output pulse width widens to 30%. Period ts is given by the following equation: tS (mS) = 160CS (F).................................(2) Fig. 5 CS pin circuit Fig. 6 CS pin waveform Fig. 7 Soft-start circuit Fig. 8 Soft-start timing chart 6 FA5304AP(S)/FA5305AP(S) 4.2 Overload shutdown Figure 9 shows the overload shutdown circuit, and Figure 10 is a timing chart which illustrates overload shutdown operation.If the output voltage drops due to an overload or short-circuit, the output voltage of the FB pin rises. If FB pin voltage exceeds the reference voltage (2.7V) of comparator C3, the output of comparator C3 switches low to turn transistor Q off. In normal operation, transistor Q is on and the CS pin is clamped at 3.6V by zener diode Zn. With Q off, the clamp is released and the 10A constant-current source begins to charge capacitor CS again and the CS pin voltage rises. When the CS pin voltage exceeds the reference voltage (7.0V) of comparator C2, the output of comparator C2 switches high to turn the bias circuit off. The IC then enters the latched mode and shuts the output down. Shutdown current consumption is 400A(VCC=9V). This current must be supplied through the startup resistor. The IC then discharges the MOSFET gates. Shutdown operation initiated by an overload can be reset by lowering supply voltage VCC below 8.7V or forcing the CS pin voltage below 7.0V.The period tOL from the time that the output is short-circuited to the time that the bias circuit turns off is given by the following equation: tOL(mS) = 340Cs(F).........................................(3) 4.3 Overvoltage shutdown Figure 11 shows the overvoltage shutdown circuit, and Figure 12 is a timing chart which illustrates overvoltage shutdown operation. The optocoupler PC1 is connected between the CS and VCC pins. If the output voltage rises too high, the PC1 turns on to raise the voltage at the CS pin via resistor R6. When the CS pin voltage exceeds the reference voltage (7.0V) of comparator C2, comparator C2 switches high to turn the bias circuit off. The IC then enters the latched mode and shuts the output down. The shutdown current consumption of the IC is 400A(VCC=9V). This current must be applied via startup resistor R5. The IC then discharges the MOSFET gates. The shutdown operation initiated by an overvoltage condition can be reset by lowering supply voltage VCC below 8.7V or forcing the CS pin voltage below 7.0V. During normal operation, the CS pin is clamped by a 3.6V zener diode with a sink current of 150A max. Therefore, a current of 150A or more must be supplied by the optocoupler in order to raise the CS pin voltage above 7.0V. Fig. 9 Overload shutdown circuit Fig. 10 Overload shutdown timing chart Fig. 11 Overvoltage shutdown circuit Fig. 12 Overvoltage shutdown timing chart 7 FA5304AP(S)/FA5305AP(S) 4.4 Output ON/OFF control The IC can be turned on and off by an external signal applied to the CS pin. Figure 13 shows the external output on/off control circuit, and Figure 14 is the timing chart. The IC is turned off if the CS pin voltage falls below 0.42V. The output of comparator C1 switches high to turn the bias circuit off. This shuts the output down. The IC then discharges the MOSFET gates. The IC turns on if the CS pin is opened for automatic soft start. The power supply then restarts operation. 5. Overcurrent limiting circuit The overcurrent limiting circuit detects the peak value of every drain current pulse of the main switching MOSFET to limit the overcurrent. The detection threshold is +0.24V for FA5304A with respect to ground as shown in Figure 15. The drain current of the MOSFET is converted to voltage by resistor R7 and fed to the IS pin of the IC. If the voltage exceeds the reference voltage (0.24V) of comparator C4, the output of comparator C4 goes high to set flip-flop output Q high. The output is immediately turned off to shut off the current. Flip-flop output Q is reset on the next cycle by the output of the PWM comparator to turn the output on again. This operation is repeated to limit the overcurrent. If the overcurrent limiting circuit malfunctions due to noise, place an RC filter between the IS pin and the MOSFET. Figure 16 is a timing chart which illustrates current-limiting operations. Fig. 13 External output on/off control circuit Fig. 14 Timing chart for external output on/off control Fig. 15 Overcurrent limiting circuit for FA5304A Fig. 16 Overcurrent timing chart for FA5304A 8 FA5304AP(S)/FA5305AP(S) The detection threshold is -0.17v for FA5305A with respect to ground as shown in Figure 17. The operation is similar to that of FA5304A except the threshold is minus voltage compared to that which is plus voltage for FA5304A. Figure 18 is a timing chart which illustrates current limiting operations. 6. Undervoltage lockout circuit The IC incorporates a circuit which prevents the IC from malfunctioning when the supply voltage drops. When the supply voltage is raised from 0V, the IC starts operation with VCC=16.0V. If the supply voltage drops, the IC shuts its output down when VCC=8.7V. When the undervoltage lockout circuit operates, the CS pin goes low to reset the IC. 7. Output circuit As shown in Figure 19, the IC's totem-pole output can directly drive the MOSFET. The OUT pin can source and sink currents of up to 1.5A. If IC operation stops when the undervoltage lockout circuit operates, the gate voltage of the MOSFET goes low and the MOSFET is shut down. Fig. 17 Overcurrent limiting circuit for FA5305A CS pin voltage (3.6V) DT voltage Oscillator output OUT pin output H L IS ( - ) pin voltage Minus detection Comparator C4 Reference voltage (- 0.17V) Bias voltage OFF Overcurrent limiting FB pin voltage Fig. 18 Overcurrent timing chart for FA5305A Fig. 19 Output circuit 9 FA5304AP(S)/FA5305AP(S) s Design advice 1. Startup circuit It is necessary to start-up IC that the voltage inclination of VCC terminal "dVcc/dt" satisfies the following equation(4). dVcc/dt(V/s)>1.8/(Cs(F)).................................(4) Cs : capacitor connected between CS terminal and GND Note that equation (4) must be satisfied in any condition. Also, it is necessary to keep "latch mode" for overload protection or overvoltage protection that the current supplied to VCC terminal through startup resistor satisfies the following equation(5). Icc(Lat)>0.4mA for Vcc 9.2V.......................(5) Icc(Lat): Cutoff-state(=Latch mode) supply current The detail is explained as follows. (1) Startup circuit connected to AC line directly Fig. 20 shows a typical startup circuit that a startup resistor Rc is connected to AC line directly. The period from power-on to startup is determined by Rc, RD and CA. Rc, RD and CA must be designed to satisfy the following equations. dVcc/dt(V/s)= (1/CA) * {(VAVE-Vccon )/RC-Vccon/RD-Iccst} > 1.8/(Cs(F)).....................................................(6) Rc(k)< (VAVE-9.2(V))/{0.4 (mA) + (9.2(V)/RD(k) } ...........(7) VAVE = Vac * 2/: Average voltage applied to AC line side of Rc Vac: AC input effective voltage Vccon: ON threshold of UVLO, 16.5V(max.) Iccst: Standby current, 0.15 mA(max.) Fig. 20 Startup circuit example(1) In this method, Vcc voltage includes ripple voltage influenced by AC voltage. Therefore, enough dVcc/dt required by equation (6) tend to be achieved easily when Vcc reaches to Vccon even if Vcc goes up very slowly. After power-off, Vcc does not rise up because a voltage applied from bias winding to VCC terminal decreases and the current flowing RC becomes zero, therefore, re-startup does not occur after Vcc falls down below OFF threshold of UVLO until next power-on. 10 FA5304AP(S)/FA5305AP(S) (2) Startup circuit connected to rectified line This method is not suitable for FA5304A and FA5305A, especially concerned with re-startup operation just after poweroff or startup which AC input voltage goes up slowly. Fig. 21 shows a startup circuit that a startup resistor RA is connected to rectified line directly. The period from power-on to startup is determined by RA, RB and CA. RA, RB and CA must be designed to satisfy the following equations. dVcc/dt(V/s)= (1/CA )*{( VIN -Vccon )/RA- Vccon/RB -Iccst } > 1.8/(Cs(F))................................................(8) RA(k)< (VIN- 9.2(V))/{0.4(mA) + (9.2(V)/RB(k))}..............(9) VIN: 2 *(AC input effective voltage) After power-off, once VCC falls down below OFF threshold voltage, VCC rises up again and re-startup occurs while the capacitor C1 is discharged until approximately zero because VCC voltage rises up by the current flowing RA. This operation is repeated several times. After the repeated operation, IC stops in the condition that VCC voltage is equal to Vccon (=ON threshold) because capacitor C1 is discharged gradually and the decreased VCC inclination is out of the condition required by equation (4). After that, re-startup by power-on can not be guaranteed even when equation (8) is satisfied. The image of that the startup is impossible is shown in Fig. 22. It is necessary to startup IC that supply current Icc (startup) to VCC is over 4mA in the condition of Tj < 100 C during Vcc is kept at Vccon( 16V, balance state at Vccon after the repeated operation. Icc (start-up) > 4mA..............................(10) at Vcc=Vccon, Tj<100C, after power-off Startup is impossible Vccoff Fig. 21 Startup circuit example(2) Startup is impossible (dVcc/dt <1.8/Cs just before Vcc reaches Vccon). Icc>4mA is necessary for startup at Tj <100C and dVcc/dt=0. Power OFF Power ON Vccon This balance state that startup is impossible tends to occur at higher temperature. If power-on is done when Vcc is not kept at Vccon (for example: power-off is done and after enough time that C1 is discharged until Vcc can not be pulled up to Vccon), the IC can startup in the condition given by equation(8). In some cases, such as when the load current of power supply is changed rapidly, you may want to prolong the hold time of the power supply output by means of maintaining Vcc over the off threshold. For this purpose, connect diode D4 and electrolytic capacitor C4 as shown in Fig. 23. This prolongs the hold time of the power supply voltage Vcc regardless of the period from poweron to startup. Fig. 22 Image of Vcc waveform when re-startup is impossible Fig. 23 Startup circuit example(3) 11 FA5304AP(S)/FA5305AP(S) 2. Disabling overload shutdown function As shown in Figure 24, connect a 330k to 470k resistor between the CS pin and ground. Then, the CS pin voltage does not rise high enough to reach the reference voltage (7.0V) of the latch comparator, and the IC does not enter the OFF latch mode. With this connection, the overvoltage shutdown function is not available. 3. Setting soft start period and OFF latch delay independently Figure 25 shows a circuit for setting the soft start period and OFF latch delay independently. In this circuit, capacitance CS determines the soft start period, and capacitance CL determines the OFF latch delay. If the overload shutdown and overvoltage shutdown functions raise the CS pin voltage to around 5V, zener diode Zn becomes conductive to charge CL. The OFF latch delay can be thus prolonged by CL. 4. Laying out Vcc and ground lines Figure 26 and Figure 27 show the recommended layouts of VCC and ground lines. The bold lines represent paths carrying large currents. The lines must have an adequate thickness. 5. Sink current setting for CS terminal A sink current to CS terminal must be satisfied the following condition to prevent from the malfunction which uncontrolled pulse output generates at OUT terminal when latch-mode protection should be operated for overvoltage. 150A < Ics(sink) < 500A at Vcs= 6.5(V) Ics(sink): Sink current to CS terminal Fig. 26 Vcc line and ground line for FA5304A Fig. 25 Independent setting of soft-start period and OFF latch delay Example (for the circuit shown in Fig. 28 ) Ics(sink) = (28(V)-18(V)- 6.5(V))/7.5(k) 467 (A) < 500 (A) Fig. 27 Vcc line and ground line for FA5305A 7.5k CS 18V Zener diode Fig. 24 Disabling overload shutdown function Under 500A VCC Fig. 28 Setting sink current for CS terminal 12 FA5304AP(S)/FA5305AP(S) s Characteristic curves (Ta = 25C) Oscillation frequency (fOSC) vs. timing capacitor capacitance (CT) Oscillation frequency (fOSC) vs. ambient temperature (Ta) Output duty cycle vs. FB terminal voltage (VFB) Output duty cycle vs. FB terminal source current (Isource) Output duty cycle vs. CS terminal voltage (VCS) H-level output voltage (VOH) vs. output source current (ISOURCE) 13 FA5304AP(S)/FA5305AP(S) L-level output voltage (VOL) vs. output sink current (ISINK) IS (+) terminal threshold voltage (VTH IS(+)) vs. ambient temperature (Ta) FA5304AP(S) VOL [V] ISINK [A] IS (-) terminal threshold voltage (VTH IS(-)) vs. ambient temperature (Ta) FA5305AP(S) IS (+) terminal current (IIS(+)) vs. IS (+) terminal voltage (VIS(+)) FA5304AP(S) IS (-) terminal current (IIS(-)) vs. IS (-) terminal voltage (VIS(-)) FA5305AP(S) CS terminal sink current (ISINK CS) vs. CS terminal voltage (VCS) 14 FA5304AP(S)/FA5305AP(S) Error amplifier frequency (f) vs. voltage gain (Av) /phase () Supply current (ICC) vs. supply voltage (VCC) Normal operation Supply current (ICC) vs. supply voltage (VCC) OFF or OFF latch mode 15 FA5304AP(S)/FA5305AP(S) s Application circuit Example of FA5304AP(S) application circuit (1) Example of FA5304AP(S) application circuit (2) 16 FA5304AP(S)/FA5305AP(S) Example of FA5304AP(S) application circuit (3) Example of FA5305AP(S) application circuit Parts tolerances characteristics are not defined in the circuit design sample shown above. When designing an actual circuit for a product, you must determine parts tolerances and characteristics for safe and economical operation. Fuji Semiconductor, Inc. - P.O. Box 702708 - Dallas, TX 75370 - 972-733-1700 - www.fujisemiconductor.com 17 |
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