View ICS85304-01_283619.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Integrated Circuit Systems, Inc.
ICS85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
FEATURES
* 5 differential 3.3V LVPECL outputs * Selectable differential CLK, nCLK or LVPECL clock inputs * CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL * PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL * Maximum output frequency: 650MHz * Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input * Output skew: 35ps (maximum) * Part-to-part skew: 150ps (maximum) * Propagation delay: 2.1ns (maximum) * 3.3V operating supply * 0C to 70C ambient operating temperature * Lead-Free package available * Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS85304-01 is a low skew, high performance 1-to-5 Differential-to-3.3V LVPECL fanout HiPerClockSTM buffer and a member of the HiPerClockSTMfamily of High Performance Clock Solutions from ICS. The ICS85304-01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
ICS
Guaranteed output and part-to-part skew characteristics make the ICS85304-01 ideal for those applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK_EN D Q LE CLK nCLK PCLK nPCLK
PIN ASSIGNMENT
Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC CLK_EN VCC nPCLK PCLK VEE nCLK CLK CLK_SEL VCC
00 11
Q0 nQ0 Q1 nQ1
CLK_SEL Q2 nQ2 Q3 nQ3 Q4 nQ4
ICS85304-01
20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm package body G Package Top View
85304AG-01
www.icst.com/products/hiperclocks.html
1
REV. D JUNE 17, 2004
Integrated Circuit Systems, Inc.
ICS85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Type Description Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Positive supply pins. Clock select input. When HIGH, selects PCLK, nPCLK inputs. Pulldown When LOW, selects CLK, nCLK inputs. LVTTL / LVCMOS interface levels. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. Negative supply pin. Pulldown Non-inver ting differential LVPECL clock input. Pullup
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5, 6 7, 8 9 , 10 11, 18, 20 12 13 14 15 16 17 Name Q0, nQ0 Q1, nQ1 Q2, nQ2 Q3, nQ3 Q4, nQ4 VCC CLK_SEL CLK nCLK VEE PCLK nPCLK Output Output Output Output Output Power Input Input Input Power Input Input
Inver ting differential LVPECL clock input. Synchronizing clock enable. When HIGH, clock outputs follow clock input. 19 CL K _ E N Input Pullup When LOW, Q outputs are forced low, nQ outputs are forced high. LVTTL / LVCMOS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF K K
85304AG-01
www.icst.com/products/hiperclocks.html
2
REV. D JUNE 17, 2004
Integrated Circuit Systems, Inc.
ICS85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Inputs Outputs Selected Source CLK, nCLK PCLK, nPCLK CLK, nCLK Q0:Q4 Disabled; LOW Disabled; LOW Enabled nQ0:nQ4 Disabled; HIGH Disabled; HIGH Enabled
TABLE 3A. CONTROL INPUT FUNCTION TABLE
CLK_EN 0 0 1 CLK_SEL 0 1 0
1 1 PCLK, nPCLK Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK, nCLK and PCLK, nPCLK inputs as described in Table 3B.
Disabled
Enabled
nCLK, nPCLK CLK, PCLK
CLK_EN
nQ0:nQ4 Q0:Q4
FIGURE 1. CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs CLK or PCLK 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nCLK or nPCLK 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 Q0:Q4 LOW HIGH LOW HIGH HIGH LOW Outputs nQ0:nQ4 HIGH LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting
NOTE 1: Please refer to the Application Information section, Wiring the Differential Input to Accept Single Ended levels.
85304AG-01
www.icst.com/products/hiperclocks.html
3
REV. D JUNE 17, 2004
Integrated Circuit Systems, Inc.
ICS85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
4.6V -0.5V to VCC + 0.5V 50mA 100mA 73.2C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C
Symbol VCC I EE Parameter Power Supply Voltage Power Supply Current Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 55 Units V mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current CLK_EN, CLK_SEL CLK_EN, CLK_SEL CLK_EN CLK_SEL CLK_EN CLK_SEL Test Conditions Minimum 2 -0.3 VIN = VCC = 3.465V VIN = VCC = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -150 -5 Typical Maximum 3.765 0.8 5 150 Units V V A A A A
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current nCLK CLK nCLK CLK Test Conditions VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -150 -5 1.3 VCC - 0.85 Minimum Typical Maximum 5 150 Units A A A A V V
Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR 0.5 NOTE 1, 2 NOTE 1: For single ended applications the maximum input voltage for CLK, nCLK is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
85304AG-01
www.icst.com/products/hiperclocks.html
4
REV. D JUNE 17, 2004
Integrated Circuit Systems, Inc.
ICS85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Test Conditions PCLK nPCLK PCLK nPCLK VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 0.15 VEE + 1.5 VCC - 1.4 VCC - 2.0 1.3 VCC VCC - 1.0 VCC - 1.7 0.85 Minimum Typical Maximum 150 5 Units A A A A V V V V V
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C
Symbol Parameter IIH IIL VPP VCMR VOH VOL Input High Current Input Low Current
Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2 Output High Voltage; NOTE 3 Output Low Voltage; NOTE 3
VSWING Peak-to-Peak Output Voltage Swing 0.6 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications the maximum input voltage for PCLK, nPCLK is VCC + 0.3V. NOTE 3: Outputs terminated with 50 to VCC - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C
Symbol fMAX t PD Parameter Maximum Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise Time Output Fall Time 20% to 80% @ 50MHz 20% to 80% @ 50MHz 300 300 650MHz 1.0 Test Conditions Minimum Typical Maximum 650 2.1 35 150 700 700 52 Units MHz ns ps ps ps ps ps
t sk(o) t sk(pp)
tR tF
o dc Output Duty Cycle 48 50 All parameters measured at 500MHz unless noted otherwise. The cycle-to-cycle jitter on the input will equal the jitter on the output. The par t does not add jitter NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
85304AG-01
www.icst.com/products/hiperclocks.html
5
REV. D JUNE 17, 2004
Integrated Circuit Systems, Inc.
ICS85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
V CC
Qx
V CC
SCOPE
nCLK, nPCLK V
PP
LVPECL
VEE
nQx
Cross Points
V
CMR
CLK, PCLK VEE
-1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx 80% Qx nQy Qy Clock Outputs 20% tR tF 80% VSW I N G 20%
tsk(o)
OUTPUT SKEW
OUTPUT RISE/FALL TIME
nCLK, nPCLK CLK, PCLK nQ0:nQ4 Q0:Q4
tPD
nQ0:nQ4 Q0:Q4
Pulse Width t
PERIOD
odc =
t PW t PERIOD
PROPAGATION DELAY
85304AG-01
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
www.icst.com/products/hiperclocks.html
6
REV. D JUNE 17, 2004
Integrated Circuit Systems, Inc.
ICS85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K CLK_IN + V_REF
-
C1 0.1uF R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50
125
FOUT FIN
125
Zo = 50
Zo = 50 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FOUT
FIN
Zo = 50 84 84
FIGURE 3A. LVPECL OUTPUT TERMINATION
85304AG-01
FIGURE 3B. LVPECL OUTPUT TERMINATION
REV. D JUNE 17, 2004
www.icst.com/products/hiperclocks.html
7
Integrated Circuit Systems, Inc.
ICS85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 4A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 4B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V
3.3V
Zo = 50 Ohm
LVDS_Driv er
CLK
R1 100
nCLK
Receiv er
Zo = 50 Ohm
FIGURE 4C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVDS DRIVER
3.3V
3.3V
3.3V
LVPECL
Zo = 50 Ohm
C1
R3 125
R4 125
CLK
Zo = 50 Ohm
C2
nCLK
HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 4E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER WITH AC COUPLE
85304AG-01
www.icst.com/products/hiperclocks.html
8
REV. D JUNE 17, 2004
Integrated Circuit Systems, Inc.
ICS85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 5A to 5F show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested
3.3V
3.3V
3.3V
3.3V
R1 50
CML
Zo = 50 Ohm
3.3V Zo = 50 Ohm
R2 50
PCLK
Zo = 50 Ohm
nPCLK
HiPerClockS PCLK/nPCLK
R1 100 Zo = 50 Ohm
PCLK nPCLK HiPerClockS PCLK/nPCLK
CML Built-In Pullup
FIGURE 5A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER
FIGURE 5B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V LVPECL
3.3V
3.3V
R3 84
R4 84
R3 125
Zo = 50 Ohm
R4 125
PCLK
Zo = 50 Ohm
C1
PCLK
Zo = 50 Ohm
Zo = 50 Ohm
C2
nPCLK
nPCLK
LVPECL
HiPerClockS Input
R5 100 - 200
R6 100 - 200
HiPerClockS PCLK/nPCLK
R1 84
R2 84
R1 125
R2 125
FIGURE 5C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 5D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE
2.5V 3.3V 2.5V R3 120 SSTL Zo = 60 Ohm PCLK Zo = 60 Ohm nPCLK HiPerClockS PCLK/nPCLK
Zo = 50 Ohm
R5 100
C2
3.3V 3.3V
3.3V
Zo = 50 Ohm
R4 120
LVDS
C1
R3 1K
R4 1K
PCLK
nPCLK
HiPerClockS PCL K/n PC LK
R1 120
R2 120
R1 1K
R2 1K
FIGURE 5E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER
FIGURE 5F.
HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
85304AG-01
www.icst.com/products/hiperclocks.html
9
REV. D JUNE 17, 2004
Integrated Circuit Systems, Inc.
ICS85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85304-01. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS85304-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 55mA = 190.57mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 5 * 30.2mW = 151mW
Total Power_MAX (3.465V, with all outputs switching) = 190.57mW + 151mW = 341.57mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.341W * 66.6C/W = 92.71C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA FOR 20-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W
200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
85304AG-01
www.icst.com/products/hiperclocks.html
10
REV. D JUNE 17, 2004
Integrated Circuit Systems, Inc.
3. Calculations and Equations.
ICS85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
LVPECL output driver circuit and termination are shown in Figure 6.
VCC
Q1
VOUT RL 50 VCC - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V (V
CC_MAX
OH_MAX
=V
CC_MAX
- 1.0V
-V
OH_MAX
) = 1.0V =V - 1.7V
*
For logic low, VOUT = V (V
CC_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CC_MAX
CC_MAX
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
L
CC_MAX
-V
OH_MAX
)=
[(2V - 1V)/50] * 1V = 20.0mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
85304AG-01
www.icst.com/products/hiperclocks.html
11
REV. D JUNE 17, 2004
Integrated Circuit Systems, Inc.
ICS85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
by Velocity (Linear Feet per Minute)
JA
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W
200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85304-01 is: 489
85304AG-01
www.icst.com/products/hiperclocks.html
12
REV. D JUNE 17, 2004
Integrated Circuit Systems, Inc.
ICS85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 6.40 6.40 BASIC 4.50 Millimeters Minimum 20 1.20 0.15 1.05 0.30 0.20 6.60 Maximum
Reference Document: JEDEC Publication 95, MO-153
85304AG-01
www.icst.com/products/hiperclocks.html
13
REV. D JUNE 17, 2004
Integrated Circuit Systems, Inc.
ICS85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Package 20 lead TSSOP 20 lead TSSOP on Tape and Reel 20 lead "Lead Free" TSSOP 20 lead "Lead Free" TSSOP on Tape and Reel Count 72 per tube 2500 72 per tube 2500 Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS85304AG-01 ICS85304AG-01T ICS85304AG-01LF ICS85304AG-01LFT Marking ICS85304AG-01 ICS85304AG-01 ICS5304A01L ICS85304A01L
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 85304AG-01
www.icst.com/products/hiperclocks.html
14
REV. D JUNE 17, 2004
Integrated Circuit Systems, Inc.
ICS85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
REVISION HISTORY SHEET Date
Rev A
Table T4B T4D T5
Page pg. 4 pg. 5 pg. 5
B
T4D T5 T4D
pg. 5
C C C C C C
pg. 5 pg. 3 pg. 3
Description of Change * VCMR values changed from 1.5 min. to 0.5 min.; VDD max. to VCC - 0.85 max. * VOH values changed from 1.9 min. to VCC - 1.4 min.; 2.3 max. to VCC - 1.0 VOL values changed from 1.2 min. to VCC - 2.0; 1.6 max. to VCC - 1.7 max. * Replaced tpLH and tpHL with tPD at the same values * Replaced tPW and values of tCYCLE/2 - 40 min., tCYCLE/2 typ., tCYCLE/2 + 40 max. with odc at values of 48 min., 50 typ., 52 max. * Added IIH, IIL, VPP, and VCMR rows * tR and tF values changed from 275 min to 300 min; 650 max. to 700 max. * Deleted VSWING row * VCMR values changed from VCC - 0.85 max. to VCC * Revised Figure 1, CLK_EN Timing Diagram * Revised Figure 1, CLK_EN Timing Diagram * Revised Inputs heading from CLK or CLK, nPCLK or nPCLK to CLK or PCLK, nCLK or nPCLK. * Added Termination for LVEPCL Outptus section * 3.3V Output Load Test Circuit Diagram - corrected VEE = -1.3V 0.135V to VEE = -1.3V 0.165V. * Updated Output Rise/Fall Time Diagram. Add Lead-Free bullet in Features section. Pin Characteristics table - changed CIN 4pF max. to 4pF typical. Absolute Maximum Ratings, updated Outputs rating. Updated Parameter Measurement Information. Added Differential Clock Input Interface section. Added LVPECL Clock Input Interface section. Ordering Information table - added Lead Free par t number.
05/14/01
05/22/01 08/21/01 10/17/01 11/2/01 12/28/01 5/30/02 8/26/02
T3B
pg. 3 pg. 8 pg. 6 pg. 7 1 2 4 6 8 9 14
T2 D
6/17/04
T9
85304AG-01
www.icst.com/products/hiperclocks.html
15
REV. D JUNE 17, 2004

▲Up To Search▲

Price & Availability of ICS85304-01

	To Download ICS85304-01 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .