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| DDR SDRAM 256Mb F-die (x8, x16) DDR SDRAM 256Mb F-die DDR400 SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant) Revision 1.1 Rev. 1.1 August. 2003 DDR SDRAM 256Mb F-die (x8, x16) 256Mb F-die Revision History Revison 1.0 (June. 2003) 1. First release Revison 1.1 (August. 2003) 1. Added x8 org (K4H560838F) DDR SDRAM Rev. 1.1 August. 2003 DDR SDRAM 256Mb F-die (x8, x16) Key Features * 200MHz Clock, 400Mbps data rate. * VDD= +2.6V + 0.10V, VDDQ= +2.6V + 0.10V * Double-data-rate architecture; two data transfers per clock cycle * Bidirectional data strobe(DQS) * Four banks operation * Differential clock inputs(CK and CK) * DLL aligns DQ and DQS transition with CK transition * MRS cycle with address key programs -. Read latency 3 (clock) for DDR400 , 2.5 (clock) for DDR333 -. Burst length (2, 4, 8) -. Burst type (sequential & interleave) * All inputs except data & DM are sampled at the positive going edge of the system clock(CK) * Data I/O transactions on both edges of data strobe * Edge aligned data output, center aligned data input * LDM,UDM for write masking only (x16) * Auto & Self refresh * 7.8us refresh interval(8K/64ms refresh) * Maximum burst refresh cycle : 8 * 66pin TSOP II Pb-Free package * RoHS compliant DDR SDRAM Ordering Information Part No. K4H560838F-UCCC K4H560838F-UCC4 K4H561638F-UCCC K4H561638F-UCC4 16M x 16 32M x 8 Org. Max Freq. CC(DDR400@CL=3) C4(DDR400@CL=3) CC(DDR400@CL=3) C4(DDR400@CL=3) SSTL2 66pin TSOP II Interface SSTL2 Package 66pin TSOP II Operating Frequencies - CC(DDR400@CL=3) Speed @CL3 CL-tRCD-tRP *CL : CAS Latency 200MHz 3-3-3 - C4(DDR400@CL=3) 200MHz 3-4-4 Rev. 1.1 August. 2003 DDR SDRAM 256Mb F-die (x8, x16) Pin Description DDR SDRAM 16Mb x 16 32Mb x 8 VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM WE CAS RAS CS NC BA0 BA1 AP/A10 A0 A1 A2 A3 VDD VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD NC NC WE CAS RAS CS NC BA0 BA1 AP/A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS NC VREF VSS DM CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS 66Pin TSOPII (400mil x 875mil) (0.65mm Pin Pitch) Bank Address BA0~BA1 Auto Precharge A10 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 256Mb Package Pinout Organization 32Mx8 16Mx16 Row Address A0~A12 A0~A12 Column Address A0-A9 A0-A8 DM is internally loaded to match DQ and DQS identically. Row & Column address configuration Rev. 1.1 August. 2003 DDR SDRAM 256Mb F-die (x8, x16) Package Physical Demension DDR SDRAM Units : Millimeters (0.80) (0.50) #66 #34 10.160.10 (1.50) (10x) (10x) #1 (1.50) #33 (0.80) 0.125 +0.075 -0.035 0.6650.05 0.2100.05 (0.50) (R 0. 15 ) 0.05 MIN [ 0.075 MAX ] (10x) NOTE 1. ( ) IS REFERENCE 2. [ ] IS ASS'Y OUT QUALITY (R (0.71) 0.65TYP 0.650.08 0.300.08 0.10 MAX 0.2 5) 0x~8x 66pin TSOPII / Package dimension Rev. 1.1 August. 2003 (R 0. 25 ) (4 x ) (R 0.1 5) (10x) 1.20MAX 22.220.10 1.000.10 0.25TYP 0.45~0.75 11.760.20 (10.16) DDR SDRAM 256Mb F-die (x8, x16) Block Diagram (8Mb x 8 / 4Mb x 16 I/O x 4 Banks) DDR SDRAM 8/16 (L)WE I/O Control CK, CK Data Input Register Serial to parallel L(U)DM Bank Select 16/32 4Mx16 / 2Mx32 Output Buffer 2-bit prefetch Sense AMP Refresh Counter Row Buffer Row Decoder 4Mx16 / 2Mx32 4Mx16 / 2Mx32 4Mx16 / 2Mx32 16/32 8/16 x8/x16 DQi Address Register CK, CK ADD Column Decoder LCBR LRAS Col. Buffer Latency & Burst Length Strobe Gen. DLL Data Strobe Programming Register LCKE LRAS LCBR LWE LCAS LWCBR CK, CK L(U)DM Timing Register DM Input Register CK, CK CKE CS RAS CAS WE L(U)DM Rev. 1.1 August. 2003 DDR SDRAM 256Mb F-die (x8, x16) Input/Output Function Description SYMBOL CK, CK TYPE Input DESCRIPTION DDR SDRAM Clock : CK and CK are differential clock inputs. All address and control input signals are sampled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to both edges of CK. Internal clock signals are derived from CK/CK. Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for all functions except for disabling outputs, which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled during power-down and self refresh modes, providing low standby power. CKE will recognize an LVCMOS LOW level prior to VREF being stable on power-up. Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command decoder. All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. Command Inputs : RAS, CAS and WE (along with CS) define the command being entered. Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0~D7 ; UDM corresponds to the data on DQ8~DQ15. DM may be driven high, low, or floating during READs. Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. Address Inputs : Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register is loaded during the MODE REGISTER SET command (MRS or EMRS). A12 & A13 are used on device densities of 256Mb and greater, and A13 is used only on 1Gb decices. Data Input/Output : Data bus Data Strobe : Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0~D7 ; UDQS corresponds to the data on DQ8~DQ15 No Connect : No internal electrical connection is present. DQ Power Supply : +2.6V 0.1V. DQ Ground. Power Supply : +2.6V 0.1V (device specific). Ground. SSTL_2 reference voltage. CKE Input CS RAS, CAS, WE Input Input LDM,(UDM) Input BA0, BA1 Input A [0 : 12] Input DQ LDQS,(U)DQS NC VDDQ VSSQ VDD VSS VREF I/O I/O Supply Supply Supply Supply Input Rev. 1.1 August. 2003 DDR SDRAM 256Mb F-die (x8, x16) Command Truth Table COMMAND Register Register Extended MRS Mode Register Set Auto Refresh Refresh Entry Self Refresh Exit CKEn-1 CKEn H H H L H H H H Bank Selection All Banks Entry Exit Entry Precharge Power Down Mode Exit DM(UDM/LDM for x16 only) No operation (NOP) : Not defined L H H X H L H H H L H X X H L H X X X X X L H L CS L L L L H L L L L L H L X H L H L RAS L L L H X L H H H L X V X X H X V X X H X H X H DDR SDRAM (V=Valid, X=Dont Care, H=Logic High, L=Logic Low) CAS L L L H X H L L H H X V X X H X V WE L L H H X H H L L L X V X X H X V X X 8 9 9 X X V X L H V V V L H L H X X BA0,1 A10/AP A0 ~ A9, A11, A12 Note 1, 2 1, 2 3 3 3 3 4 4 4 4, 6 7 5 OP CODE OP CODE X X Row Address Column Address Column Address Bank Active & Row Addr. Read & Column Address Write & Column Address Burst Stop Precharge Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable Active Power Down Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2. EMRS/MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM(x4/8) sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). UDM/LDM(x16 only) sampled at the rising and falling edges of the UDQS/LDQS and Data-in are masked at the both edges (Write UDM/LDM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM. Rev. 1.1 August. 2003 DDR SDRAM 256Mb F-die (x8, x16) General Description DDR SDRAM 8M x 8bit x 4 Banks / 4M x 16Bit x 4 Banks Double Data Rate SDRAM The K4H560838F / K4H561638F is 268,435,456 bits of double data rate synchronous DRAM organized as 4x 8,388,608 / 4x 4,194,304 words by 8 / 16bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 400Mb/s per pin. I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications. Absolute Maximum Ratings Parameter Voltage on any pin relative to VSS Voltage on VDD & VDDQ supply relative to VSS Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -0.5 ~ 3.6 -1.0 ~ 3.6 -55 ~ +150 1.5 50 Unit V V C W mA Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommend operation condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC Operating Conditions Parameter Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70C) Symbol VDD VDDQ VREF VTT VIH(DC) VIL(DC) VIN(DC) VID(DC) VI(Ratio) II IOZ IOH IOL IOH IOL Min 2.5 2.5 0.49*VDDQ VREF-0.04 VREF+0.15 -0.3 -0.3 0.36 0.71 -2 -5 -16.8 16.8 -9 9 Max 2.7 2.7 0.51*VDDQ VREF+0.04 VDDQ+0.3 VREF-0.15 VDDQ+0.3 VDDQ+0.6 1.4 2 5 Unit V V V V V V V uA uA mA mA mA mA Note 5 5 1 2 Supply voltage(for device with a nominal VDD of 2.5V) I/O Supply voltage I/O Reference voltage I/O Termination voltage(system) Input logic high voltage Input logic low voltage Input Voltage Level, CK and CK inputs Input Differential Voltage, CK and CK inputs V-I Matching: Pullup to Pulldown Current Ratio Input leakage current Output leakage current Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V 3 4 Note : 1.VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same. Peak-to peak noise on VREF may not exceed +/-2% of the dc value. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0. 5. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20MHz. Any noise above 20MHz at the DRAM generated from any source other than the DRAM itself may not exceed the DC voltage range of 2.6V +/-100mV. Rev. 1.1 August. 2003 DDR SDRAM 256Mb F-die (x8, x16) DDR SDRAM Spec Items & Test Conditions Conditions Operating current - One bank Active-Precharge; tRC=tRCmin; tCK=5ns for DDR400; DQ,DM and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles; CS = high between valid commands. Operating current - One bank operation ; One bank open, BL=4, Reads - Refer to the following page for detailed test condition; CS = high between valid commands. DDR SDRAM Symbol IDD0 IDD1 IDD2P IDD2F Percharge power-down standby current; All banks idle; power - down mode; CKE = IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Input/Output Capacitance Parameter Input capacitance (A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS, WE) Input capacitance( CK, CK ) Data & DQS input/output capacitance Input capacitance(DM for 8, UDM/LDM for x16) (VDD=2.6, VDDQ=2.6V, TA= 25C, f=1MHz) Symbol CIN1 CIN2 COUT CIN3 Min 2 2 4 4 Max 3 3 5 Delta 0.5 0.25 0.5 Unit pF pF pF pF Note 4 4 1,2,3,4 1,2,3,4 5 Note : 1.These values are guaranteed by design and are tested on a sample basis only. 2. Although DM is an input -only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins. This is required to match signal propagation times of DQ, DQS, and DM in the system. 3. Unused pins are tied to ground. 4. This parameteer is sampled. VDDQ = +2.6V +0.1V, VDD = +2.6V +0.1V, f=100MHz, tA=25C, Vout(dc) = VDDQ/2, Vout(peak to peak) = 0.2V. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in loading (to facilitate trace matching at the board level). Rev. 1.1 August. 2003 DDR SDRAM 256Mb F-die (x8, x16) DDR SDRAM IDD spec table Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7A Normal Low power 32Mx8 - CC(DDR400@CL=3) 105 130 4 30 25 55 75 185 220 200 3 1.5 350 - C4(DDR400@CL=3) 100 130 4 30 25 55 75 185 220 200 3 1.5 350 DDR SDRAM (VDD=2.7V, T = 10C) Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Notes Optional Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7A Normal Low power 16Mx16 - CC(DDR400@CL=3) 110 150 4 30 25 55 75 220 250 200 3 1.5 380 - C4(DDR400@CL=3) 105 145 4 30 25 55 75 220 250 200 3 1.5 380 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Notes Optional Rev. 1.1 August. 2003 DDR SDRAM 256Mb F-die (x8, x16) < Detailed test conditions for DDR SDRAM IDD1 & IDD7A > DDR SDRAM IDD1 : Operating current: One bank operation 1. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs change logic state once per Deselect cycle. Iout = 0mA 2. Timing patterns - CC/C4(200Mhz,CL=3) : tCK=5ns, CL=3, BL=4, tRCD=3*tCK(CC) 4*tCK(C4), tRC=11*tCK(CC) 12*tCK(C4), tRAS=8*tCK Setup : A0 N N R0 N N N N P0 N N Read : A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing *50% of data changing at every transfer IDD7A : Operating current: Four bank operation 1. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on Deselet edge are not changing. Iout = 1mA 2. Timing patterns - CC/C4(200Mhz,CL=3) : tCK=5ns, CL=3, BL=4, tRCD=3*tCK(CC) 4*tCK(C4), tRC=11*tCK(CC) 12*tCK(C4), tRAS=8*tCK Setup : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N Read : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N - repeat the same timing with random address changing *50% of data changing at every transfer Legend : A = Activate, R=Read, W=Write, P=Precharge, N=NOP Rev. 1.1 August. 2003 DDR SDRAM 256Mb F-die (x8, x16) AC Operating Conditions Parameter/Condition Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Input Differential Voltage, CK and CK inputs Input Crossing Point Voltage, CK and CK inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 0.7 0.5*VDDQ-0.2 Min VREF + 0.31 Max-10 DDR SDRAM Unit V V V V Note VREF - 0.31 VDDQ+0.6 0.5*VDDQ+0.2 1 2 Notes : 1. VID is the magnitude of the difference between the input level on CK and the input level on /CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same. AC Overshoot/Undershoot specification for Address and Control Pins Parameter Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot The area between the overshoot signal and VDD must be less than or equal to The area between the undershoot signal and GND must be less than or equal to Specification DDR400 1.5V 1.5V 4.5V-ns 4.5V-ns VDD 5 4 3 2 Volts (V) 1 0 -1 -2 -3 -4 -5 0 Overshoot Maximum Amplitude = 1.5V Area = 4.5V-ns Maximum Amplitude = 1.5V GND 0.6875 1.5 2.5 3.5 4.5 5.5 6.3125 7.0 0.5 1.0 2.0 3.0 4.0 5.0 6.0 6.5 Tims(ns) undershoot AC overshoot/Undershoot Definition Rev. 1.1 August. 2003 DDR SDRAM 256Mb F-die (x8, x16) Overshoot/Undershoot specification for Data, Strobe, and Mask Pins Parameter Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot The area between the overshoot signal and VDD must be less than or equal to The area between the undershoot signal and GND must be less than or equal to DDR SDRAM Specification DDR400 1.2V 1.2V 2.5V-ns 2.5V-ns VDDQ Overshoot 5 4 3 2 Volts (V) 1 0 -1 -2 -3 -4 -5 0 0.5 1.0 1.42 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.68 6.0 6.5 7.0 Tims(ns) undershoot Maximum Amplitude = 1.2V GND Area = 2.5V-ns Maximum Amplitude = 1.2V DQ/DM/DQS AC overshoot/Undershoot Definition Rev. 1.1 August. 2003 DDR SDRAM 256Mb F-die (x8, x16) AC Timing Parameters and Specifications Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Internal write to read command delay Clock cycle time Clock high level width Clock low level width DQS-out access time from CK/CK Output data access time from CK/CK Data strobe edge to ouput data edge Read Preamble Read Postamble CK to valid DQS-in Write preamble setup time Write preamble Write postamble DQS falling edge to CK rising-setup time DQS falling edge from CK rising-hold time DQS-in high level width DQS-in low level width Address and Control Input setup time Address and Control Input hold time Data-out high impedence time from CK/CK Data-out low impedence time from CK/CK Mode register set cycle time DQ & DM setup time to DQS, slew rate 0.5V/ns DQ & DM hold time to DQS, slew rate 0.5V/ns DQ & DM input pulse width Control & Address input pulse width for each input Refresh interval time Output DQS valid window Clock half period CL=3.0 CL=2.5 Symbol tRC tRFC tRAS tRCD tRP tRRD tWR tWTR tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPRE tWPST tDSS tDSH tDQSH tDQSL tIS tIH tHZ tLZ tMRD tDS tDH tDIPW tIPW tREFI tQH tHP tHP -tQHS min tCH/tCL - CC(DDR400@CL=3) Min 55 70 40 15 15 10 15 2 5 6 0.45 0.45 -0.55 -0.65 0.9 0.4 0.72 0 0.25 0.4 0.2 0.2 0.35 0.35 0.6 0.6 tAC min 2 0.4 0.4 1.75 2.2 7.8 tHP -tQHS min tCH/tCL tAC max tAC max 0.6 10 12 0.55 0.55 +0.55 +0.65 0.4 1.1 0.6 1.28 70K Max DDR SDRAM - C4(DDR400@CL=3) Min 60 70 40 18 18 10 15 2 5 6 0.45 0.45 -0.55 -0.65 0.9 0.4 0.72 0 0.25 0.4 0.2 0.2 0.35 0.35 0.6 0.6 tAC min 2 0.4 0.4 1.75 2.2 7.8 tAC max tAC max 0.6 10 12 0.55 0.55 +0.55 +0.65 0.4 1.1 0.6 1.28 70K Max Unit ns ns ns ns ns ns ns tCK ns ns tCK tCK ns ns ns tCK tCK tCK ps tCK tCK tCK tCK tCK tCK ns ns ns ns tCK ns ns ns ns us ns ns i, j i, j 9 9 6 12 11, 12 h,7~10 h,7~10 3 3 4 5 13 16 Note Rev. 1.1 August. 2003 DDR SDRAM 256Mb F-die (x8, x16) Parameter Data hold skew factor Auto Precharge write recovery + precharge time Exit self refresh to non-READ command Exit self refresh to READ command Symbol tQHS tDAL tXSNR tXSRD 75 200 - CC(DDR400@CL=3) Min Max 0.5 75 200 Min DDR SDRAM - C4(DDR400@CL=3) Max 0.5 Unit ns ns ns tCK Note 12 14 15 Component Notes 1.VID is the magnitude of the difference between the input level on CK and the input level on CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same. 3. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level but specify when the device output in no longer driving (HZ), or begins driving (LZ). 4. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys tem performance (bus turnaround) will degrade accordingly. 5. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ ously in progress on the bus, DQS will be tran sitioning from High- Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 6. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. 7. For command/address input slew rate 0.5 V/ns 8. For CK & CK slew rate 0.5 V/ns 9. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 10. Slew Rate is measured between VOH(ac) and VOL(ac). 11. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces. 12. tQH = tHP - tQHS, where: tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and pchannel to n-channel variation of the output drivers. 13. tDQSQ Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle. 14. tDAL = (tWR/tCK) + (tRP/tCK) For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR400(CC) at CL=3 and tCK=5ns tDAL = (15 ns / 5 ns) + (15 ns/ 5ns) = {(3) + (3)}CLK tDAL = 6 clocks 15. In all circumstances, tXSNR can be satisfied using tXSNR=tRFCmin+1*tCK 16. The only time that the clock frequency is allowed to change is during self-refresh mode. Rev. 1.1 August. 2003 DDR SDRAM 256Mb F-die (x8, x16) System Characteristics for DDR SDRAM DDR SDRAM The following specification parameters are required in systems using DDR400 devices to ensure proper system performance. these characteristics are for system simulation purposes and are guaranteed by design. Table 1 : Input Slew Rate for DQ, DQS, and DM AC CHARACTERISTICS PARAMETER DQ/DM/DQS input slew rate measured between VIH(DC), VIL(DC) and VIL(DC), VIH(DC) SYMBOL DCSLEW DDR400 MIN 0.5 MAX 4.0 Units V/ns Notes a, k Table 2 : Input Setup & Hold Time Derating for Slew Rate Input Slew Rate 0.5 V/ns 0.4 V/ns 0.3 V/ns tIS 0 +50 +100 tIH 0 0 0 Units ps ps ps Notes h h h Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate Input Slew Rate 0.5 V/ns 0.4 V/ns 0.3 V/ns tDS 0 +75 +150 tDH 0 +75 +150 Units ps ps ps Notes j j j Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate Delta Slew Rate +/- 0.0 V/ns +/- 0.25 V/ns +/- 0.5 V/ns tDS 0 +50 +100 tDH 0 +50 +100 Units ps ps ps Notes i i i Table 5 : Output Slew Rate Characteristice (X8 Devices only) Slew Rate Characteristic Pullup Slew Rate Pulldown slew Typical Range (V/ns) 1.2 ~ 2.5 1.2 ~ 2.5 Minimum (V/ns) 1.0 1.0 Maximum (V/ns) 4.5 4.5 Notes a,c,d,f,g b,c,d,f,g Table 6 : Output Slew Rate Characteristice (X16 Devices only) Slew Rate Characteristic Pullup Slew Rate Pulldown slew Typical Range (V/ns) 1.2 ~ 2.5 1.2 ~ 2.5 Minimum (V/ns) 0.7 0.7 Maximum (V/ns) 5.0 5.0 Notes a,c,d,f,g b,c,d,f,g Table 7 : Output Slew Rate Matching Ratio Characteristics AC CHARACTERISTICS PARAMETER Output Slew Rate Matching Ratio (Pullup to Pulldown) DDR400 MIN MAX Notes e,k Rev. 1.1 August. 2003 DDR SDRAM 256Mb F-die (x8, x16) System Notes : a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1. DDR SDRAM Test point Output 50 VSSQ Figure 1 : Pullup slew rate test load b. Pulldown slew rate is measured under the test conditions shown in Figure 2. VDDQ 50 Output Test point Figure 2 : Pulldown slew rate test load c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV) Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV) Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output switching. Example : For typical slew rate, DQ0 is switching For minmum slew rate, all DQ bits are switching from either high to low, or low to high. For Maximum slew rate, only one DQ is switching from either high to low, or low to high. The remaining DQ bits remain the same as for previous state. d. Evaluation conditions Typical : 25 C (T Ambient), VDDQ = 2.6V, typical process Minimum : 70 C (T Ambient), VDDQ = 2.5V, slow - slow process Maximum : 0 C (T Ambient), VDDQ = 2.7V, fast - fast process e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. f. Verified under typical conditions for qualification purposes. g. TSOPII package divices only. h. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. i. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4. Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(Slew Rate2)} For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this would result in the need for an increase in tDS and tDH of 100 ps. Rev. 1.1 August. 2003 DDR SDRAM 256Mb F-die (x8, x16) DDR SDRAM j. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions. k. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi tions through the DC region must be monotony. Rev. 1.1 August. 2003 |
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