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SDRAM 256Mb E-die (x4, x8, x16)
CMOS SDRAM
256Mb E-die SDRAM Specification 54pin sTSOP-II
Revision 1.0 August. 2003
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.0 August, 2003
SDRAM 256Mb E-die (x4, x8, x16)
Revision History
Revision 1.0 (August. 2003) - First release.
CMOS SDRAM
Rev. 1.0 August, 2003
SDRAM 256Mb E-die (x4, x8, x16)
CMOS SDRAM
16M x 4Bit x 4 Banks / 8M x 8Bit x 4 Banks / 4M x 16Bit x 4 Banks SDRAM
FEATURES
* JEDEC standard 3.3V power supply * LVTTL compatible with multiplexed address * Four banks operation * MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) * All inputs are sampled at the positive going edge of the system clock. * Burst read single-bit write operation * DQM (x4,x8) & L(U)DQM (x16) for masking * Auto & self refresh * 64ms refresh period (8K Cycle)
GENERAL DESCRIPTION
The K4S560432E / K4S560832E / K4S561632E is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 16,785,216 / 4 x 8,392,608 / 4 x 4,196,304 words by 4bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
Ordering Information
Part No. K4S560432E-NC(L)75 K4S560832E-NC(L)75 K4S561632E-NC(L)60/75 Orgainization 64M x 4 32M x 8 16M x 16 Max Freq. 133MHz 133MHz 166/133MHz Interface LVTTL LVTTL LVTTL Package 54pin sTSOP 54pin sTSOP 54pin sTSOP
Organization 64Mx4 32Mx8 16Mx16
Row Address A0~A12 A0~A12 A0~A12
Column Address A0-A9, A11 A0-A9 A0-A8
Row & Column address configuration
Rev. 1.0 August, 2003
SDRAM 256Mb E-die (x4, x8, x16)
Package Physical Dimension
54pin sTSOP(II)-300
CMOS SDRAM
Units : Millimeters
(0.50) (14) (0.50) (8.22) (0.80) 0.125 +0.075 -0.035 (2-R 0.15) #54 #28 (0.80) (2-R 0.30)
( 2.00 Dp0~0.05 BTM) 9.220.20
(1.00)
(1.00)
#1
#27
0.6650.05
0.2100.05
7.6
(1.10)
0.10 MAX
(R 0.2 5)
(R
5)
(14
0.1
0. 30 )
(14)
NOTE 1. ( ) IS REFERENCE 2. [ ] IS ASS'Y OUT QUALITY
0.05 MIN
(0.50)
0.50TYP 0.500.05 [ 0.07 MAX ]
0.20
+0.075 -0.035
(2 -R
0x~8x
Rev. 1.0 August, 2003
0. 25 )
)
(2R
(14)
1.000.05
1.20MAX
14.40MAX (14.20) 14.000.10
0.25TYP
0.40~0.60
SDRAM 256Mb E-die (x4, x8, x16)
FUNCTIONAL BLOCK DIAGRAM
CMOS SDRAM
I/O Control
LWE LDQM
Data Input Register Bank Select 16M x 4 / 8M x 8 / 4M x 16 Sense AMP 16M x 4 / 8M x 8 / 4M x 16 16M x 4 / 8M x 8 / 4M x 16 16M x 4 / 8M x 8 / 4M x 16 Refresh Counter
Output Buffer
Row Decoder
Row Buffer
DQi
Address Register
CLK ADD
Column Decoder Col. Buffer Latency & Burst Length
LRAS
LCBR
LCKE LRAS LCBR LWE LCAS Timing Register
Programming Register LWCBR LDQM
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.0 August, 2003
SDRAM 256Mb E-die (x4, x8, x16)
PIN CONFIGURATION (Top view) x16
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE CAS RAS CS BA0 BA1 AP/A10 A0 A1 A2 A3 VDD
CMOS SDRAM
x4 x8
VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC VSS NC DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS
x8
VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC VDD NC WE CAS RAS CS BA0 BA1 AP/A10 A0 A1 A2 A3 VDD
x4
VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC VDD NC WE CAS RAS CS BA0 BA1 AP/A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46
x16
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS
VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC VSS NC DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS
54 PIN sTSOP(II)
300mil x 551mil (7.62mm x 14.00mm) (0.5 mm pin pitch)
45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
PIN FUNCTION DESCRIPTION
Pin CLK CS Name System clock Chip select Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA12, Column address : (x4 : CA0 ~ CA9,CA11), (x8 : CA0 ~ CA9), (x16 : CA0 ~ CA8) Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. Data inputs/outputs are multiplexed on the same pins. (x4 : DQ0 ~ 3), (x8 : DQ0 ~ 7), (x16 : DQ0 ~ 15) Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device.
CKE
Clock enable
A0 ~ A12
Address
BA0 ~ BA1 RAS CAS WE DQM DQ0 ~ N VDD/VSS VDDQ/VSSQ N.C/RFU
Bank select address Row address strobe Column address strobe Write enable Data input/output mask Data input/output Power supply/ground Data output power/ground No connection /reserved for future use
Rev. 1.0 August, 2003
SDRAM 256Mb E-die (x4, x8, x16)
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1 50
CMOS SDRAM
Unit V V C W mA
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70C) Parameter Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Symbol VDD, VDDQ VIH VIL VOH VOL ILI Min 3.0 2.0 -0.3 2.4 -10 Typ 3.3 3.0 0 Max 3.6 VDD+0.3 0.8 0.4 10 Unit V V V V V uA 1 2 IOH = -2mA IOL = 2mA 3 Note
Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
Clock
(VDD = 3.3V, TA = 23C, f = 1MHz, VREF =1.4V 200 mV) Pin Symbol CCLK CIN CADD COUT Min 2.5 2.5 2.5 4.0 Max 3.5 3.8 3.8 6.0 Unit pF pF pF pF Note
RAS, CAS, WE, CS, CKE, DQM Address (x4 : DQ0 ~ DQ3), (x8 : DQ0 ~ DQ7), (x16 : DQ0 ~ DQ15)
Rev. 1.0 August, 2003
SDRAM 256Mb E-die (x4, x8, x16)
DC CHARACTERISTICS (x4, x8)
(Recommended operating condition unless otherwise noted, TA = 0 to 70C) Parameter Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode Active standby current in power-down mode Active standby current in non power-down mode (One bank active) Symbol Burst length = 1 tRC tRC(min) IO = 0 mA CKE VIL(max), tCC = 10ns CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 10ns CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IO = 0 mA Page burst 4banks Activated. tCCD = 2CLKs tRC tRC(min) CKE 0.2V C L Test Condition
CMOS SDRAM
Version -75 80 2 2 20
Unit
Note
ICC1 ICC2P
mA
1
ICC2PS CKE & CLK VIL(max), tCC = ICC2N ICC2NS ICC3P
mA
mA 10 6 6 25 25 mA mA mA
ICC3PS CKE & CLK VIL(max), tCC = ICC3N ICC3NS
Operating current (Burst mode) Refresh current Self refresh current
ICC4
100
mA
1
ICC5 ICC6
180 3 1.5
mA mA mA
2 3 4
Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S5604(08)32E-NC75 4. K4S5604(08)32E-NL75 5. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).
Rev. 1.0 August, 2003
SDRAM 256Mb E-die (x4, x8, x16)
DC CHARACTERISTICS (x16)
(Recommended operating condition unless otherwise noted, TA = 0 to 70C) Parameter Operating current (One bank active) Precharge standby current in power-down mode Symbol Burst length = 1 tRC tRC(min) IO = 0 mA CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IO = 0 mA Page burst 4banks Activated. tCCD = 2CLKs tRC tRC(min) CKE 0.2V C L Test Condition
CMOS SDRAM
Version -60 140 2 2 20 10 6 6 25 25 -75 90
Unit Note
ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS
mA
1
mA mA
Precharge standby current in non power-down mode
Active standby current in power-down mode Active standby current in non power-down mode (One bank active)
mA mA mA
Operating current (Burst mode) Refresh current Self refresh current
ICC4
170
130
mA
1
ICC5 ICC6
200 3 1.5
180
mA mA mA
2 3 4
Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S561632E-NC75 4. K4S561632E-NL75 5. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).
Rev. 1.0 August, 2003
SDRAM 256Mb E-die (x4, x8, x16)
AC OPERATING TEST CONDITIONS (VDD = 3.3V 0.3V, TA = 0 to 70C)
Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2
CMOS SDRAM
Unit V V ns V
3.3V
Vtt = 1.4V
1200 Output 870 50pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Z0 = 50
50
50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data Symbol tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 CAS latency=2 60 2 2 CLK + tRP 1 1 1 2 1 Version -60 12 18 18 42 100 65 -75 15 20 20 45 Unit ns ns ns ns us ns CLK CLK CLK CLK ea 1 2, 5 5 2 2 3 4 Note 1 1 1 1
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
Rev. 1.0 August, 2003
SDRAM 256Mb E-die (x4, x8, x16)
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter CLK cycle time CLK to valid output delay Output data hold time CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 Symbol tCC tSAC tOH tCH tCL tSS tSH tSLZ tSHZ 2.5 2.5 2.5 1.5 1 1 5 -60 Min 6 Max 1000 5 3 3 2.5 2.5 1.5 0.8 1 Min 7.5 10 -75
CMOS SDRAM
Max 1000 5.4 6
Unit ns ns ns ns ns ns ns ns
Note 1 1,2 2 3 3 3 3 2
5.4 6
ns
Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.
DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
Parameter Output rise time Output fall time Output rise time Output fall time Symbol trh tfh trh tfh Condition Measure in linear region : 1.2V ~ 1.8V Measure in linear region : 1.2V ~ 1.8V Measure in linear region : 1.2V ~ 1.8V Measure in linear region : 1.2V ~ 1.8V Min 1.37 1.30 2.8 2.0 3.9 2.9 Typ Max 4.37 3.8 5.6 5.0 Unit Volts/ns Volts/ns Volts/ns Volts/ns Notes 3 3 1,2 1,2
Notes : 1. Rise time specification based on 0pF + 50 to VSS, use these values to design to. 2. Fall time specification based on 0pF + 50 to VDD, use these values to design to. 3. Measured into 50pF only, use these values to characterize to. 4. All measurements done with respect to VSS.
Rev. 1.0 August, 2003
SDRAM 256Mb E-die (x4, x8, x16)
IBIS SPECIFICATION
IOH Characteristics (Pull-up)
Voltage (V) 3.45 3.3 3.0 2.6 2.4 2.0 1.8 1.65 1.5 1.4 1.0 0.0 100MHz 133MHz Min I (mA) 100MHz 133MHz Max I (mA) -2.4 -27.3 -74.1 -129.2 -153.3 -197.0 -226.2 -248.0 -269.7 -284.3 -344.5 -502.4 66MHz Min I (mA) -200 -0.7 -7.5 -13.3 -27.5 -35.5 -41.1 -47.9 -52.4 -72.5 -93.0 mA -300 -400 -500 -600 Voltage 0 0 -100 0.5 1 1.5 2
CMOS SDRAM
66MHz and 100MHz/133MHz Pull-up 2.5 3 3.5
0.0 -21.1 -34.1 -58.7 -67.3 -73.0 -77.9 -80.8 -88.6 -93.0
IOH Min (100MHz) IOH Min (66MHz) IOH Max (66 and 100MHz)
66MHz and 100MHz/133MHz Pull-down
IOL Characteristics (Pull-down)
Voltage (V) 0.0 0.4 0.65 0.85 1.0 1.4 1.5 1.65 1.8 1.95 3.0 3.45 100MHz 133MHz Min I (mA) 0.0 27.5 41.8 51.6 58.0 70.7 72.9 75.4 77.0 77.6 80.3 81.4 100MHz 133MHz Max I (mA) 0.0 70.2 107.5 133.8 151.2 187.7 194.4 202.5 208.6 212.0 219.6 222.6 66MHz Min I (mA) 0.0 17.7 26.9 33.3 37.6 46.6 48.0 49.5 50.7 51.5 54.2 54.9
250
200
150 mA 100 50 0 0 0.5 1 1.5 2 2.5 3 3.5
Voltage
IOL Min (100MHz) IOL Min (66MHz) IOL Max (100MHz)
Rev. 1.0 August, 2003
SDRAM 256Mb E-die (x4, x8, x16)
CMOS SDRAM
Minimum VDD clamp current (Referenced to VDD) 20
VDD Clamp @ CLK, CKE, CS, DQM & DQ
VDD (V) 0.0 0.2 0.4 0.6 0.7 0.8 0.9 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 I (mA) 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.23 1.34 3.02 5.06 7.35 9.83 12.48 15.30 18.31
15
mA
10
5
0 0 1 Voltage
I (mA)
2
3
Minimum VSS clamp current
VSS Clamp @ CLK, CKE, CS, DQM & DQ
VSS (V) -2.6 -2.4 -2.2 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.9 -0.8 -0.7 -0.6 -0.4 -0.2 0.0 I (mA) -57.23 -45.77 -38.26 -31.22 -24.58 -18.37 -12.56 -7.57 -3.37 -1.75 -0.58 -0.05 0.0 0.0 0.0 0.0 0 -10 -20 mA -30 -40 -50 -60
-3
-2
-1
0
Voltage
I (mA)
Rev. 1.0 August, 2003
SDRAM 256Mb E-die (x4, x8, x16)
SIMPLIFIED TRUTH TABLE
Command Register Mode register set Auto refresh Refresh Entry Self refresh Exit
CKEn-1 CKEn CS RAS CAS
CMOS SDRAM
(V=Valid, X=Don't care, H=Logic high, L=Logic low)
WE DQM BA0,1 A10/AP A0 ~ A9 A11, A12 Note
H H L H H H H
X H L H X X X X X L H L H
L L L H L L L L L H L X H L H L H L
L L H X L H H H L X V X X H X V X X H
L L H X H L L H H X V X X H X V X H
L H H X H H L L L X V X X H X V X H
X X X X X X X X X X X V X V V V
OP code X X Row address L H L H X L H X X
Column address Column address
1,2 3 3 3 3 4 4,5 4 4,5 6
Bank active & row addr. Read & column address Write & column address Burst stop Precharge Bank selection All banks Entry Exit Entry Precharge power down mode Exit DQM No operation command Auto precharge disable Auto precharge enable Auto precharge disable Auto precharge enable
H H L H L H H
Clock suspend or active power down
X X V X X X 7
X
Notes : 1. OP Code : Operand code A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev. 1.0 August, 2003

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