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19-2153; Rev 0; 9/01
KIT ATION EVALU ABLE AVAIL
3.125Gbps XAUI Quad Equalizer
General Description Features
o Four Differential Digital Data "Lanes" at 3.125Gbps o Spans 40in (1.0m) of FR4 PC Board o Receiver Equalization Reduces Intersymbol Interference (ISI) o Low-Power, 175mW per Channel o Standby Mode--Power-Down State o Single +3.3V Supply o Signal Detect
MAX3980
The MAX3980 quad equalizer provides compensation for transmission medium losses for four "lanes" of digital NRZ data at a 3.125Gbps data rate in one package. It is tailor-made for 10-Gigabit Ethernet (10GbE) backplane applications requiring attenuation of noise and jitter that occur in communicating from MAC to PMD or from MAC to Switch. In support of the IEEE-802.3ae for the XAUI interface, the MAX3980 adaptively allows XAUI lanes to reach up to 40in (1.0m) on FR4 board material. The equalizer has 100 differential CML data inputs and outputs. The MAX3980 is available in a 44-pin exposed-pad QFN package. The MAX3980 consumes only 700mW at +3.3V or 175mW per channel.
Applications
IEEE-802.3ae XAUI Interface (3.125Gbps) InfiniBand (2.5Gbps)
PART MAX3980UGH
Ordering Information
TEMP. RANGE 0C to +85C PIN-PACKAGE 44 QFN-EP*
*Exposed pad
Pin Configuration appears at end of data sheet.
Typical Application Circuit
LINE CARD PC BOARD BACKPLANE PMD MAC 40in (1.0m) Rx Tx 4 Rx Tx 4 x 3.125Gbps 10GbE 4x 3.125Gbps 4 4 +3.3V SUPPLY 4 IN OUT 4 Rx SWITCH SWITCH CARD
MAX3980
+3.3V SUPPLY
Tx
Rx
Tx
Rx
OUT
MAX3980
IN 40in (1.0m)
4
Tx
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
3.125Gbps XAUI Quad Equalizer MAX3980
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC.............................................-0.5V to +4.0 V Voltage at SDET, IN_ ..............................+0.5V to (VCC + 0.5V) Current Out of OUT_.......................................-25mA to +25mA Continuous Power Dissipation (TA = +85C) 44-Pin QFN-EP (derate 26.3mW/C above +85C)...2105mW Operating Ambient Temperature Range ................0C to +85C Storage Temperature Range .............................-55C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, input data rate = 3.125Gbps, TA = 0C to +85C. Typical values are at VCC = +3.3V and TA = +25C, unless otherwise noted.)
PARAMETER Supply Power SYMBOL EN = TTL low EN = TTL high 10Hz < f < 100Hz Supply Noise Tolerance Signal Detect Assert Signal Detect Deassert Signal Detect Delay Latency CML RECEIVER INPUT Input Voltage Swing Return Loss Input Resistance EQUALIZATION Residual Jitter Random Jitter CML TRANSMITTER OUTPUT (into 100 1) Output Voltage Swing Common-Mode Voltage Transition Time Differential Skew Output Resistance tf, tr 20% to 80% (Note 3) Difference in 50% crossing between OUT_+ and OUT_Single ended 40 50 Differential swing 550 VCC - 0.3 60 130 12 60 850 mVp-p V ps ps Total jitter (Note 2) Deterministic jitter (Note 2) 1.5 0.3 0.2 UIp-p psRMS XAUI transmitter output measured differentially at point A, Figure 1, using K28.5 pattern 100MHz to 2.5GHz Differential 80 200 12 100 120 800 mVp-p dB From input to output 0.32 100Hz < f < 1MHz 1MHz < f < 2.5GHz Input signal level to assert SDET (Note 1) Input signal level to deassert SDET (Note 1) 100 30 10 0.7 100 40 10 mVp-p mVp-p s ns mVp-p CONDITIONS MIN TYP MAX 0.25 0.9 UNITS W
2
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3.125Gbps XAUI Quad Equalizer
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, input data rate = 3.125Gbps, TA = 0C to +85C. Typical values are at VCC = +3.3V and TA = +25C, unless otherwise noted.)
PARAMETER TTL CONTROL PINS Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage Output Low Voltage Internal 10k pullup Internal 10k pullup 2.4 0.4 2.0 0.8 250 500 V V A A V V SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX3980
Note 1: K28.7 pattern is applied differentially at point A as shown in Figure 1. Note 2: Total jitter does not include the signal source jitter. Total jitter (TJ) = [14.1 x RJ + DJ] where RJ is random RMS jitter and DJ is maximum deterministic jitter. Signal source is a K28.5 pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and K28.7 (0011111000) or equivalent for the random jitter test. Residual jitter is that which remains after equalizing media-induced losses of the environment of Figure 1 or its equivalent. The deterministic jitter at point B must be from mediainduced loss and not from clock-source modulation. Jitter is measured at 0 at point C of Figure 1. Note 3: Using K28.7 (0011111000) pattern.
A FR4 STRIPLINE 40in (1m)
B
C
MAX3980 SMA CONNECTOR SMA CONNECTOR IN OUT
Figure 1. Test Conditions Referenced in the Electrical Characteristics Table
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3.125Gbps XAUI Quad Equalizer MAX3980
Typical Operating Characteristics
(VCC = +3.3V, 3.125Gbps, 500mVp-p board input with 27 - 1 PRBS, TA = +25C, unless otherwise noted.)
EQUALIZER INPUT EYE DIAGRAM BEFORE EQUALIZATION (40in FR4 6mil STRIPLINE)
MAX3980 toc01
EQUALIZER OUTPUT EYE DIAGRAM AFTER EQUALIZATION (40in FR4 6mil STRIPLINE)
MAX3980 toc02
EQUALIZER OUTPUT EYE DIAGRAM (20in BACKPLANE WITH TWO TERADYNE HSD CONNECTORS AND 3in DAUGHTERBOARD)
MAX3980 toc03
50mV/ div
100mV/ div
100mV/ div
50ps/div
50ps/div
50ps/div
INPUT RETURN GAIN (S11, DIFFERENTIAL, INPUT SIGNAL = -60dBm, DEVICE POWERED OFF)
MAX3980 toc04
EQUALIZER DETERMINISTIC JITTER vs. LENGTH (FR4 6mil STRIPLINE, K28.5 PATTERN)
MAX3980 toc05
EQUALIZER LATENCY vs. TEMPERATURE
MAX3980 toc06
10 0 -10
40 35 30 JITTER (ps)
500 450 400 DELAY (ps) 350 300 250 200
GAIN (dB)
25 20 15 10
-20 -30 -40 -50 50 1050 2050 3050 4050 5050 FREQUENCY (MHz)
5 0 0 10 20 30 40 50 LENGTH (in)
0
10
20
30
40
50
60
70
80
90
TEMPERATURE (C)
EQUALIZER OPERATING CURRENT vs. TEMPERATURE
210 190 CURRENT (mA) 170 150 130 110 90 70 50 0 10 20 30 40 50 60 70 80 TEMPERATURE (C) STANDBY POWER (EN = TTL LOW)
MAX3980 toc07
NORMAL OPERATION (EN = TTL HIGH)
4
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3.125Gbps XAUI Quad Equalizer
Pin Description
PIN 1, 5, 9, 13, 23, 27, 31, 35 2 3 4, 8, 12, 16, 26, 30, 34, 38 6 7 10 11 14 15 17-22, 39-42 24 25 28 29 32 33 36 37 43 44 EP NAME VCC IN1+ IN1GND IN2+ IN2IN3+ IN3IN4+ IN4N.C. OUT4OUT4+ OUT3OUT3+ OUT2OUT2+ OUT1OUT1+ EN SDET Exposed Pad +3.3V Supply Voltage Positive Equalizer Input Channel 1, CML Negative Equalizer Input Channel 1, CML Supply Ground Positive Equalizer Input Channel 2, CML Negative Equalizer Input Channel 2, CML Positive Equalizer Input Channel 3, CML Negative Equalizer Input Channel 3, CML Positive Equalizer Input Channel 4, CML Negative Equalizer Input Channel 4, CML No Connection. Leave unconnected. Negative Equalizer Output Channel 4, CML Positive Equalizer Output Channel 4, CML Negative Equalizer Output Channel 3, CML Positive Equalizer Output Channel 3, CML Negative Equalizer Output Channel 2, CML Positive Equalizer Output Channel 2, CML Negative Equalizer Output Channel 1, CML Positive Equalizer Output Channel 1, CML Enable Equalizer Input. A TTL high selects normal operation. A TTL low selects low-power standby mode. Signal Detect Output for Channel 1. Produces a TTL high output when a signal is detected. Ground. The exposed pad must be soldered to the circuit board ground plane for proper thermal and electrical performance. FUNCTION
MAX3980
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3.125Gbps XAUI Quad Equalizer MAX3980
Functional Diagram
IP1, IN1 ONLY SIGNAL DETECT
TTL
SDET
IN1+
2
OUT1+ 3 CML 4 EQUALIZER LIMITING AMP OUT12 3 4 4 3 4
2
3
4
IN1-
2
3
2 4 3 4
2 3
2
2
3
4
EN SDET FUNCTION IS INDEPENDENT OF EN
POWER MANAGEMENT
MAX3980
Detailed Description
Receiver and Transmitter
The receiver accepts four lanes of 3.125Gbps currentmode logic (CML) digital data signals. The adaptive equalizer compensates each received signal for dielectric and skin losses. The limiting amp shapes the output of the equalizer. The regenerated XAUI lanes are transmitted as CML signals. The source impedance and termination impedances are 100 differential.
short-run DC-balanced transmission codes such as 8b/10b codes.
CML Input and Output Buffers
The input and output buffers are implemented using CML. Equivalent circuits are shown in Figures 2 and 3. For details on interfacing with CML, see Maxim application note HFAN-1.0, Interfacing Between CML, PECL, and LVDS. The common-mode voltage of the input and output is above 2.5V. AC-coupling capacitors are required when interfacing this part. Values of 0.10F or greater are recommended.
General Theory of Operation
Internally, the MAX3980 comprises signal-detect circuitry, four matched equalizers, and one equalizercontrol loop. The four equalizers are made up of a master equalizer and three slave equalizers. The adaptive control is generated from only channel 1. It is assumed that all channels have the same characterization in frequency content, coding, and transmission length. The master equalizer consists of the following functions: signal detect, adaptive equalizer, equalizer control, and limiting and output drivers. The signal detect indicates input signal power. When the input signal level is sufficiently high, the SDET output is asserted. This does not directly control the operation of the part. The equalizer core reduces intersymbol interference (ISI), compensating for frequency-dependent, mediainduced loss. The equalization control detects the spectral contents of the input signal and provides a control voltage to the equalizer core, adapting it to different media. The equalizer operation is optimized for
Media Equalization
Equalization at the input port compensates for the highfrequency loss encountered with up to 40in (1.0m) of FR4 transmission lines. This part is optimized for 40in and 3.125Gbps; however, the part reduces ISI for signals spanning longer distances and functions for data rates from 2Gbps to 4Gbps, provided that short-length balanced codes, such as 8b/10b, are used.
Applications Information
Standby Mode
The power-saver standby state allows reduced-power operation. The TTL input, EN, must be set to TTL high for normal operation. A TTL low at EN forces the equalizer into the standby state. The signal EN does not affect the operation of the signal detect (SDET) function. For constant operation, connect the EN signal directly to VCC.
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3.125Gbps XAUI Quad Equalizer MAX3980
VCC VCC
50 1.2k
50
OUT+ 50 IN+ Q1 INDATA 200A ESD STRUCTURES ESD STRUCTURES Q2 50 OUT-
Figure 2. CML Input Buffer
Figure 3. CML Output Buffer
Signal Detect with Standby Mode
Signal activity is detected on channel 1 only. When the peak-to-peak differential voltage at IN1 is less than 30mVp-p, the TTL output SDET goes low. When the peak-to-peak differential voltage becomes greater than 100mVp-p, SDET is asserted high. SDET can be used to automatically force the equalizer into standby mode by connecting SDET directly to the EN input. When not used, SDET should not be connected. The signal-detect function continues to operate while the part is in standby mode. While connected to the EN pin, the signal detect can "wake up" the part and resume normal operation.
TOP VIEW SDET
Pin Configuration
N.C. GND OUT1+ OUT139 38 37 36
44
43
42
41
40
35
34
VCC GND
EN N.C.
N.C. N.C.
VCC IN1+ IN1GND VCC IN2+ IN2GND VCC IN3+ IN3-
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
33 32 31 30 29 28 27 26 25 24 23
OUT2+ OUT2VCC GND OUT3+ OUT3VCC GND OUT4+ OUT4VCC
MAX3980
Layout Considerations
Circuit-board layout and design can significantly affect the MAX3980 performance. Use good high-frequency design techniques, including minimizing ground inductances and vias and using controlled-impedance transmission lines for the high-frequency data signals. Signals should be routed differentially to reduce EMI susceptibility and crosstalk. Power-supply decoupling capacitors should be placed as close as possible to the VCC pins.
GND
*NOTE: THE EXPOSED PAD MUST BE SOLDERED TO SUPPLY GROUND.
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IN4+ IN4GND N.C. N.C.
QFN*
N.C. N.C. N.C. N.C.
VCC
7
3.125Gbps XAUI Quad Equalizer MAX3980
Package Information
QFN 28, 32,44, 48L.EPS 8 _______________________________________________________________________________________
3.125Gbps XAUI Quad Equalizer
Package Information (continued)
MAX3980
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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