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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-21359-4E
ASSP
Single Serial Input PLL Frequency Synthesizer On-chip 1.2 GHz Prescaler
MB15E03SL
s DESCRIPTION
The Fujitsu MB15E03SL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 1.2 GHz prescaler. The 1.2 GHz prescaler has a dual modulus division ratio of 64/65 or 128/129 enabling pulse swallowing operation. The supply voltage range is between 2.4 V and 3.6 V. The MB15E03SL uses the latest BiCMOS process, as a result, the supply current is typically 2.0 mA at 2.7 V. A refined charge pump supplies a well balanced output currents of 1.5 mA or 6 mA. The charge pump current is selectable by serial data. MB15E03SL is ideally suited for wireless mobile communications, such as GSM.
s FEATURES
* High frequency operation: 1.2 GHz max * Low power supply voltage: VCC = 2.4 V to 3.6 V * Ultra Low power supply current: ICC = 2.0 mA typ. (VCC = Vp = 2.7 V, Ta = +25C, in locking state) ICC = 2.5 mA typ. (VCC = Vp = 3 V, Ta = +25C, in locking state) * Direct power saving function: Power supply current in power saving mode Typ. 0.1 A (VCC = Vp = 3 V, Ta = +25C), Max. 10 A (VCC = Vp = 3 V) * Dual modulus prescaler: 64/65 or 128/129 * Serial input 14-bit programmable reference divider: R = 3 to 16,383 * Serial input programmable divider consisting of: - Binary 7-bit swallow counter: 0 to 127 - Binary 11-bit programmable counter: 3 to 2,047 * Selectable charge pump current * On-chip phase control for phase comparator * Operating temperature: Ta = -40 to +85C * Pin compatible with MB15E03, MB15E03L
s PACKAGES
16-pin plastic SSOP 16-pad plastic BCC
(FPT-16P-M05)
(LCC-16P-M06)
MB15E03SL
s PIN ASSIGNMENTS
16-pin SSOP
1 2 3 4 5 6 7 8 16 15 14 TOP 13 VIEW 12 11 10 9 R P LD/fout ZC PS LE Data Clock OSCOUT VP VCC DO GND Xfin
16-pad BCC
OSCIN R 1 2 3 4 5 6 7 8 TOP VIEW 16 15 14 13 12 11 10 9 P LD/fout ZC PS LE Data
OSCIN OSCOUT VP VCC DO GND Xfin fin
fin Clock
(FPT-16P-M05)
(LCC-16P-M06)
2
MB15E03SL
s PIN DESCRIPTION
Pin No. SSOP-16 BCC-16 1 2 3 4 5 6 7 8 9 10 11 16 1 2 3 4 5 6 7 8 9 10 Pin Name OSCIN OSCOUT VP VCC DO GND Xfin fin Clock Data LE I/O I O -- -- O -- I I I I I Descriptions Programmable reference divider input. Oscillator input connection to a TCXO. Oscillator output. Power supply voltage input for the charge pump. Power supply voltage input. Charge pump output. Phase of the charge pump can be selected via programming of the FC bit. Ground. Prescaler complementary input which should be grounded via a capacitor. Prescaler input. Connection to an external VCO should be done via AC coupling. Clock input for the 19-bit shift register. Data is shifted into the shift register on the rising edge of the clock. (Open is prohibited.) Serial data input using binary code. The last bit of the data is a control bit. (Open is prohibited.) Load enable signal input. (Open is prohibited.) When LE is set high, the data in the shift register is transferred to a latch according to the control bit in the serial data. Power saving mode control. This pin must be set at "L" at Power-ON. (Open is prohibited.) PS = "H"; Normal mode PS = "L"; Power saving mode Forced high-impedance control for the charge pump (with internal pull up resistor.) ZC = "H"; Normal Do output. ZC = "L"; Do becomes high impedance. Lock detect signal output (LD)/phase comparator monitoring output (fout). The output signal is selected via programming of the LDS bit. LDS = "H"; outputs fout (fr/fp monitoring output) LDS = "L"; outputs LD ("H" at locking, "L" at unlocking.) Phase comparator N-channel open drain output for an external charge pump. Phase can be selected via programming of the FC bit. Phase comparator CMOS output for an external charge pump. Phase can be selected via programming of the FC bit.
12
11
PS
I
13
12
ZC
I
14
13
LD/fout P R
O
15 16
14 15
O O
3
MB15E03SL
s BLOCK DIAGRAM
(16) OSCIN 1
fr Reference oscillator circuit Phase comparator
(15) 16 R
(1) OSCOUT 2 Binary 14-bit reference counter (2) VP 3 14-bit latch SW FC LDS CS Lock detector
(14) 15 P
4-bit latch fp
LD/fr/fp selector
(13) 14 LD/fout
(3) VCC 4
C N T
19-bit shift register
(12) 13 ZC
Current switch Charge pump
7-bit latch Binary 7-bit swallow counter
11-bit latch Binary 11-bit programmable counter Intermittent mode control (power save)
(4) DO 5
(11) 12 PS
(5) GND 6 1-bit cotrol latch (6) Xfin 7 Prescaler 64 / 65, 128 / 129 (7) fin 8 MD
(10) 11 LE
(9) 10 Data
(8) 9 Clock
: SSOP ( ): BCC
4
MB15E03SL
s ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage Input voltage Output voltage Storage temperature Symbol VCC VP VI VO VO Tstg Condition -- -- -- Except Do Do -- Rating Min. -0.5 VCC -0.5 GND GND -55 Max. 4.0 6.0 VCC +0.5 VCC VP +125 Unit V V V V V C Remark
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage Input voltage Operating temperature Symbol VCC VP VI Ta Value Min. 2.4 VCC GND -40 Typ. 3.0 -- -- -- Max. 3.6 5.5 VCC +85 Unit V V V C Remark
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
5
MB15E03SL
s ELECTRICAL CHARACTERISTICS
(VCC = 2.4 to 3.6 V, Ta = -40 to +85C) Parameter Power supply current*1 Power saving current Operating frequency fin OSCIN fin*3 OSCIN*3 "H" level input voltage "L" level input voltage "H" level input current "L" level input current "H" level input current "L" level input current "H" level input current "L" level input current Data, Clock, LE, PS, ZC Data, Clock, LE, PS OSCIN ZC Symbol ICC IPS fin fOSC Pfin VOSC VIH VIL IIH*4 IIL*4 IIH IIL IIL
*4
Condition VCC = VP = 2.7 V (VCC = VP = 3.0 V) ZC = "H" or open -- -- 50 system (Refer to the Measurment circuit.) -- -- -- -- -- -- -- -- Pull up input Open drain output VCC = VP = 3 V, IOH = -1 mA VCC = VP = 3 V, IOL = 1 mA VCC = VP = 3 V, IDOH = -0.5 mA VCC = VP = 3 V, IDOL = 0.5 mA VCC = VP = 3 V, VOFF = 0.5 V to VP - 0.5 V Open drain output -- -- VCC = 3 V, VP = 3 V, VDO = VP/2 Ta = +25C CS bit = "H" CS bit = "L" CS bit = "H" CS bit = "L"
Value Min. -- -- 100 3 -15 0.5 VCC x 0.7 -- -1.0 -1.0 0 -100 -1.0 -100 -- VCC - 0.4 -- VP - 0.4 -- -- 1.0 -- 1.0 -- -- -- -- -- -- -- Typ. 2.0 (2.5) 0.1*2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -6.0 -1.5 6.0 1.5 3 10 10 Max. -- 10 1200 40 +2 VCC -- VCC x 0.3 +1.0 +1.0 +100 0 +1.0 0 0.4 -- 0.4 -- 0.4 2.5 -- -1.0 -- -- -- -- -- -- -- --
Unit mA A MHz MHz dBm Vp-p V
Input sensitivity
A A A V V V nA mA mA
IIH*4
*4
"L" level output voltage P "H" level output voltage R, "L" level output voltage LD/fout "H" level output voltage "L" level output voltage Do
VOL VOH VOL VDOH VDOL IOFF IOL IOH IOL IDOH*4
High impedance cutoff Do current "L" level output current P "H" level output current R, "L" level output current LD/fout "H" level output current Do "L" level output current
mA
IDOL
IDOL/IDOH IDOMT*5 VDD = VP/2 Charge pump current rate vs VDO vs Ta IDOVD*6 0.5 V VDO VP - 0.5 V IDOTA*7 - 40C Ta +85C
% % %
(Continued)
6
MB15E03SL
(Continued) *1: Conditions; fin = 1200 MHz, fosc = 12 MHz, Ta = +25C, in locking state. *2: VCC = VP = 3.0 V, fosc = 12.8 MHz, Ta = +25C, in power saving mode *3: AC coupling. 1000 pF capacitor is connected under the condition of min. operating frequency. *4: The symbol "-" (minus) means direction of current flow. *5: VCC = VP = 3.0 V, Ta = +25C (|I3| - |I4|) / [(|I3| + |I4|) /2] x 100(%) *6: VCC = VP = 3.0 V, Ta = +25C [(|I2| - |I1|) /2] / [(|I1| + |I2|) /2] x 100(%) (Applied to each IDOL, IDOH) *7: VCC = VP = 3.0 V, VDO = VP/2 (|IDO(+85C) - IDO(-40C)| /2) / (|IDO(+85C) + IDO(-40C)| /2) x 100(%) (Applied to each IDOL, IDOH)
I1 IDOL
I3 I2
IDOH
I2
I4 I1 0.5 VP/2 VP - 0.5 VP
Charge Pump Output Voltage (V)
7
MB15E03SL
s FUNCTIONAL DESCRIPTION
1. Pulse Swallow Function
The divide ratio can be calculated using the following equation: fVCO = [(M x N) + A] x fOSC / R (A < N) fVCO : Output frequency of external voltage controlled oscillator (VCO) N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047) A : Preset divide ratio of binary 7-bit swallow counter (0 A 127) fOSC : Output frequency of the reference frequency oscillator R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383) M : Preset divide ratio of the dual modulus prescaler (64 or 128)
2. Serial Data Input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference divider and the programmable divider separately. Binary serial data is entered through the Data pin. One bit of data is shifted into the shift register on the rising edge of the Clock. When the LE pin is taken high, stored data is latched according to the control bit data as follows:
Table 1. Control Bit
Control Bit (CNT) H L (1) Shift Register Configuration Programmable Reference Counter LSB Data Flow 1 2 3 R2 4 R3 5 R4 6 R5 7 R6 8 R7 9 R8 10 11 12 13 14 15 16 17 18 19 MSB Destination of Serial Data For the programmable reference divider For the programmable divider
CNT R1
R9 R10 R11 R12 R13 R14 SW
FC LDS CS
CNT R1 to R14 SW FC LDS CS
: Control bit : Divide ratio setting bit for the programmable reference counter (3 to 16,383) : Divide ratio setting bit for the prescaler (64/65 or 128/129) : Phase control bit for the phase comparator : LD/fout signal select bit : Charge pump current select bit
[Table 1] [Table 2] [Table 5] [Table 8] [Table 7] [Table 6]
Note: Start data input with MSB first.
8
MB15E03SL
Programmable Counter LSB 1 2 3 A2 4 A3 5 A4 6 A5 7 A6 8 A7 MSB Data Flow 9 N1 10 N2 11 N3 12 N4 13 N5 14 N6 15 N7 16 N8 17 18 19
CNT A1
N9 N10 N11
CNT : Control bit N1 to N11: Divide ratio setting bits for the programmable counter (3 to 2,047) A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127) Note: Start data input with MSB first.
[Table 1] [Table 3] [Table 4]
Table 2. Binary 14-bit Programmable Reference Counter Data Setting
Divide ratio (R) 3 4 16383 R14 0 0 1 R13 0 0 1 R12 0 0 1 R11 0 0 1 R10 0 0 1 R9 0 0 1 R8 0 0 1 R7 0 0 1 R6 0 0 1 R5 0 0 1 R4 0 0 1 R3 0 1 1 R2 1 0 1 R1 1 0 1
Note: Divide ratio less than 3 is prohibited.
Table 3. Binary 11-bit Programmable Counter Data Setting
Divide ratio (N) 3 4 2047 N11 0 0 1 N10 0 0 1 N9 0 0 1 N8 0 0 1 N7 0 0 1 N6 0 0 1 N5 0 0 1 N4 0 0 1 N3 0 1 1 N2 1 0 1 N1 1 0 1
Note: Divide ratio less than 3 is prohibited.
9
MB15E03SL
Table 4. Binary 7-bit Swallow Counter Data Setting
Divide ratio (A) 0 1 127 A7 0 0 1 A6 0 0 1 A5 0 0 1 A4 0 0 1 A3 0 0 1 A2 0 0 1 A1 0 1 1
Table 5. Prescaler Data Setting
SW H L Prescaler Divide Ratio 64/65 128/129
Table 6. Charge Pump Current Setting
CS H L Current Value 6.0 mA 1.5 mA
Table 7. LD/fout Output Select Data Setting
LDS H L fout signal LD signal LD/fOUT Output Signal
(2) Relation between the FC Input and Phase Characteristics The FC bit changes the phase characteristics of the phase comparator. Both the internal charge pump output level (DO) and the phase comparator output (R, P) are reversed according to the FC bit. Also, the monitor pin (fout) output is controlled by the FC bit. The relationship between the FC bit and each of DO, R, and P is shown below.
Table 8. FC Bit Data Setting (LDS = "H")
FC = High DO fr > fp fr < fp fr = fp H L Z* R L H L P L Z* Z* fout = fr LD/fout DO L H Z* H L L FC = Low R P Z* L Z* fout = fp LD/fout
* : High impedance
10
MB15E03SL
When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics. * When the LPF and VCO characteristics are similar to (1), set FC bit high. * When the VCO characteristics are similar to (2), set FC bit low.
(1)
PLL
LPF
VCO
VCO Output Frequency (2) LPF Output Voltage
3. Do Output Control Table 9. ZC Pin Setting
ZC pin H L Normal output High impedance Do output
11
MB15E03SL
4. Power Saving Mode (Intermittent Mode Control Circuit) Table 10. PS Pin Setting
PS pin H L Normal mode Power saving mode Status
The intermittent mode control circuit reduces the PLL power consumption. By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See the Electrical Characteristics chart for the specific value. The phase detector output, Do, becomes high impedance. For the signal PLL, the lock detector, LD, remains high, indicating a locked condition. Setting the PS pin high, releases the power saving mode, and the device works normally. The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation. When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparator output, resulting in a VCO frequency jump and an increase in lockup time. To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation. Notes: *When power (VCC) is first applied, the device must be in standby mode, PS = Low, for at least 1 s. *PS pin must be set "L" for Power-ON.
OFF VCC Clock Data LE PS tPS 100 ns tV 1 s ON
(1)
(2)
(3)
(1) PS = L (power saving mode) at Power ON (2) Set serial data 1 s later after power supply remains stable (VCC > 2.2 V). (3) Release power saving mode (PS: "L" "H") 100 ns later after setting serial data.
12
MB15E03SL
s SERIAL DATA INPUT TIMING
1st data Control bit Data MSB Clock LSB Invalid data 2nd data
t1 t7 LE
t2
t3 t6 t4 t5
On the rising edge of the clock, one bit of data is transferred into the shift register. Parameter t1 t2 t3 t4 Min. 20 20 30 30 Typ. -- -- -- -- Max. -- -- -- -- Unit ns ns ns ns Parameter t5 t6 t7 Min. 100 20 100 Typ. -- -- -- Max. -- -- -- Unit ns ns ns
Note: LE should be "L" when the data is transferred into the shift register.
13
MB15E03SL
s PHASE COMPARATOR OUTPUT WAVEFORM
fr
fp
tWU
tWL
LD
[FC = "H"]
H DO Z L
[FC = "L"]
H DO Z L
Notes:* Phase error detection range: -2 to +2 * Pulses on Do output signal during locked state are output to prevent dead zone. * LD output becomes low when phase is tWU or more. LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more. * tWU and tWL depend on OSCIN input frequency. tWU > 2/fosc (s) (e. g. tWU > 156.3 ns, fosc = 12.8 MHz) tWU < 4/fosc (s) (e. g. tWL < 312.5 ns, fosc = 12.8 MHz) * LD becomes high during the power saving mode (PS = "L").
14
MB15E03SL
s MEASURMENT CIRCUIT (for Measuring Input Sensitivity fin/OSCIN)
1000 pF 1000 pF S.G. 50 fin 8 Xfin GND 7 6 DO 5 VCC 4 VP OSCOUT OSCIN 3 2 1 50 0.1 F 0.1 F 1000 pF S.G.
9
10
11
12 PS
13
14
15
16 R Oscilloscope
Clock Data LE Controller (setting divide ratio)
ZC LD/fout P
VCC
Note: 16-pin SSOP
15
MB15E03SL
s TYPICAL CHARACTERISTICS
1. fin input sensitivity
Input sensitivity - Input frequency (Prescaler 64/65)
10 Input sensitivity Pfin (dBm) 0 -10 -20 -30 -40 -50 0 500 1000 Input frequency fin (MHz) 1500 2000
,,,,,,,,,,,,,, ,,,,,,,,,,,,,, ,,,,,,,,,,,,,,
SPEC
Ta = +25 C
VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V
2. OSCIN input sensitivity
10
Input sensitivity VOSC (dBm)
0 -10 -20 -30 -40 -50 -60
,,,,, ,,,,,
SPEC
Input sensitivity - Input frequency
Ta = +25 C
VCC = 2.4 V VCC = 3.0 V VCC = 3.6 V 0 50 Input frequency fOSC (MHz) 100
16
MB15E03SL
3. Do output current 1.5 mA mode
VDO - IDO
10.00 Charge pump output current IDO (mA)
Ta = +25 C
VCC = 3.0 V VP = 3.0 V
2.000 /div 0
IOL
IOH
- 10.00
0
.6000/div Charge pump output voltage VDO (V)
4.800
6.0 mA mode
VDO - IDO
Ta = +25 C
10.00 Charge pump output current IDO (mA) IOL 2.000 /div 0
VCC = 3.0 V VP = 3.0 V
IOH
- 10.00
0
.6000/div Charge pump output voltage VDO (V)
4.800
17
MB15E03SL
4. fin input impedance
1 : 297.63 -656.53 100 MHz 2 : 24.523 -185.55 400 MHz 3 : 9.3789 -77.168 800 MHz 4 : 10.188 -33.143 1.2 GHz
1
4
2
3
START 100.000 000 MHz
STOP 1 200.000 000 MHz
5. OSCIN input impedance
1:
9.063 k -3.113 k 3 MHz 3.8225 -4.6557 k 10 MHz 1.5735 -3.2154 k 20 MHz 405.69 -1.8251 k 40 MHz
2:
3: 4 1 3 4: 3
START 3.000 000 MHz
STOP 40.000 000 MHz
18
MB15E03SL
s REFERENCE INFORMATION
S.G.
OSCIN
DO
LPF
fin Spectrum Analyzer
VCO
fVCO = 810.425 MHz KV = 17 MHz/V fr = 25 kHz fOSC = 14.4 MHz exp current: 6.0 mA
* LPF
9.1 k Do 4.2 k 4700 pF 47000 pF 1500 pF VCO
(Continued)
19
MB15E03SL
* PLL Reference Leakage
ATTEN 10 dB RL - 5.0 dBm MKR - 79.83 dB 25.0 kHz
79.8 dBc
Ta = +25C
* RBW
CENTER 810.42500 MHz 1.0 kHz VBW 1.0 kHz
* SWP
SPAN 200.0 kHz 1.00 s
* PLL Phase Noise
ATTEN 10 dB RL - 5.0 dBm MKR - 53.00 dB 2.23 kHz
73.0 dBc/Hz
Ta = +25C
* RBW
CENTER 810.42500 MHz 100 Hz VBW 100 Hz
* SWP
SPAN 20.00 kHz 3.00 s
(Continued)
20
MB15E03SL
(Continued)
PLL Lock Up Time 810.425 MHz 826.4251 kHz Lch Hch 1.40 ms
850.00500 MHz 860.00000 MHz
PLL Lock Up Time 826.425 MHz 810.4251 kHz Hch Lch 1.52 ms
10.00000 Hz/div
10.00000 Hz/div
810.00000 MHz 5.0000000 ms
810.00000 MHz 5.0000000 ms
830.00500 MHz
830.00500 MHz
2.00 KHz/div
2.00 KHz/div
829.99500 MHz 5.0000000 ms
829.99500 MHz 5.0000000 ms
21
MB15E03SL
s APPLICATION EXAMPLE
VP 10 k 12 k 12 k LPF VCO
Output
10 k Lock detect. From a controller
R 16
P 15
LD/fout 14
ZC 13
PS 12
LE 11
Data 10
Clock 9
MB15E03SL
1 OSCIN
2 OSCOUT
3 VP
4 VCC
5 DO
6 GND
7 Xfin
8 fin 1000 pF
1000 pF 1000 pF TCXO 0.1 F 0.1 F
VP:
5.5 V Max
Notes:* SSOP-16 * In case of using a crystal resonator, it is necessary to optimize matching between the crystal and this LSI, and perform detailed system evaluation. It is recommended to consult with a supplier of the crystal resonator. (Reference oscillator circuit provides its own bias, feedback resistor is 100 k (typ).)
22
MB15E03SL
s USAGE PRECAUTIONS
To protect against damage by electrostatic discharge, note the following handling precautions: -Store and transport devices in conductive containers. -Use properly grounded workstations, tools, and equipment. -Turn off power before inserting device into or removing device from a socket. -Protect leads with a conductive sheet when transporting a board-mounted device.
s ORDERING INFORMATION
Part number MB15E03SLPFV1 MB15E03SLPV1 Package 16-pin, Plastic SSOP (FPT-16P-M05) 16-pad, Plastic BCC (LCC-16P-M06) Remarks
23
MB15E03SL
s PACKAGE DIMENSIONS
16-pin, Plastic SSOP (FPT-16P-M05)
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness.
* 5.000.10(.197.004)
16 9
0.170.03 (.007.001)
* 4.400.10
INDEX
6.400.20 (.173.004) (.252.008)
Details of "A" part 1.25 -0.10 .049 -.004 LEAD No.
1 8
+0.20 +.008
(Mounting height)
0.65(.026)
"A" 0.240.08 (.009.003) 0.13(.005)
M
0~8 0.100.10 (Stand off) (.004.004) 0.25(.010)
0.10(.004)
0.500.20 (.020.008) 0.45/0.75 (.018/.030)
C
1999 FUJITSU LIMITED F16013S-3C-5
Dimensions in mm (inches)
(Continued)
24
MB15E03SL
(Continued)
16-pad, Plastic BCC (LCC-16P-M06)
4.550.10 (.179.004)
14 9
0.80(.031)MAX Mounting height 0.400.10 (.016.004) 0.80(.031) REF 0.65(.026) TYP
9
3.40(.134)TYP 0.3250.10 (.013.004)
14
INDEX AREA 3.400.10 (.134.004) 2.45(.096) TYP "A" "B" 1.15(.045) REF
1
6
0.0750.025 (.003.001) (Stand off)
6
1.725(.068) REF
1
Details of "A" part 0.750.10 (.030.004) 0.05(.002)
Details of "B" part 0.600.10 (.024.004)
0.400.10 (.016.004)
0.600.10 (.024.004)
C
1999 FUJITSU LIMITED C16017S-1C-1
Dimensions in mm (inches)
25
MB15E03SL
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0002 (c) FUJITSU LIMITED Printed in Japan

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