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| Order this document by MCF5204/D Communications and Advanced Microprocessor and Memory Consumer Technologies Group Technologies Group MCF5204 Product Brief MCF5204 ColdFireTM Integrated Microprocessor The MCF5204 integrated microprocessor combines a ColdFireTM processor core with several peripheral functions such as timers and serial interface. Designed for cost-sensitive embedded control applications, the ColdFire core delivers enhanced performance while maintaining low system cost. To speed program execution, the on-chip instruction cache and SRAM provide one-cycle access to critical code and data. The MCF5204 processor greatly reduces the time required for system design and implementation by packaging common system functions on chip and providing glueless interfaces to 8- and 16-bit SRAM, ROM, and I/O devices. The revolutionary ColdFire microprocessor architecture gives cost-sensitive, high-volume markets new levels of price and performance. Based on the concept of variable-length RISC technology, ColdFire combines the architectural simplicity of conventional 32-bit RISC with a memory-saving, variable-length instruction set. In defining the ColdFire architecture for embedded processing applications, Motorola incorporated RISC architecture for peak performance and a simplified version of the variable-length instruction set found in the M68000 Family for code density. By using a variable-length instruction set architecture, embedded processor designers using ColdFire RISC processors will enjoy significant system-level advantages over conventional fixed-length RISC architectures. The denser binary code for ColdFire processors consumes less valuable memory than any fixed-length instruction set RISC processor available. This improved code density means more efficient system memory use for a given application, and requires slower, less costly memory to help achieve a target performance level. The integrated peripheral functions provide high performance and flexibility. The serial interface consists of a programmable full duplex UART. The MCF5204 has two 16-bit general-purpose multimode timers, one of which provides a separate input and output signal. For system protection, the processor includes a programmable 16-bit software watchdog timer and several bus monitors. In addition, common system functions such as chip-selects, interrupt control, and IEEE 1149.1 Test (JTAG) support are included. A sophisticated debug interface supports both background-debug mode and real-time trace. This interface is common to all ColdFire-based processors and allows common emulator support across the entire ColdFire Family. ColdFire is a trademark of Motorola. 1. I2C bus is a proprietary Philips interface bus. This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. SEMICONDUCTOR PRODUCT INFORMATION (c) 1996 Motorola, Inc. All Rights Reserved. The primary features of the MCF5204 integrated processor include the following: * ColdFire Processor Core -- Variable-length RISC -- 32-bit internal address bus with up to 4 Mbytes of off-chip linear address space -- 16-bit data bus -- 16 user-visible 32-bit wide registers -- Supervisor / User modes for system protection -- Vector base register to relocate exception-vector table -- Optimized for high-level language constructs -- 13.5 MIPS at 33Mhz * 512-Byte Direct-Mapped Instruction Cache * 512-Byte On-Chip SRAM -- Provides one-cycle access to critical code and data * Universal Synchronous/Asynchronous Receiver/Transmitter (UART) -- Full duplex operation -- UART timer provides baud rate generation based on system clock -- External clock provided via timer TIN pin -- Modem control signals available (CTS, RTS) -- Processor-interrupt capability * Dual 16-Bit General-Purpose Multimode Timers -- 8-bit prescaler -- Timer input and output pins (For Timer 1 only) -- 30ns resolution with 33MHz system clock -- Processor-interrupt capability * System Interface -- Glueless bus interface to 8-, 16- SRAM, ROM, and I/O devices -- 6 programmable chip-select signals -- Programmable wait states and port sizes --System protection * 16-bit software watchdog timer with prescaler * Double bus fault monitor * Bus timeout monitor * Spurious interrupt monitor -- Programmable interrupt controller * Low interrupt latency * 4 external interrupt inputs * Programmable interrupt priority and autovector generator -- IEEE 1149.1 test (JTAG) support -- 8-Bit General-Purpose I/O Interface * System Debug Support -- Real-time trace -- Background debug interface * Fully Static 5.0-Volt Operation * 100 Pin TQFP Package 2 MCF5204 PRODUCT INFORMATION MOTOROLA OVERVIEW Figure 1 is a block diagram of the MCF5204 processor. The paragraphs that follow provide an overview of the device. CLOCK INPUT CLOCK CHIP SELECTS SYSTEM BUS CONTROLLER CHIP SELECTS JTAG INTERFACE JTAG INTERRUPT CONTROLLER INTERRUPT SUPPORT EXTERNAL 512 BYTE ICACHE 512 BYTE SRAM BUS INTERFACE EXTERNAL BUS UART SERIAL INTERFACE TIMERS BDM INTERFACE COLDFIRE CORE TIMER SUPPORT Figure 1. MCF5204 Block Diagram ColdFire Processor Core The ColdFire processor core consists of two independent, decoupled pipeline structures to maximize performance while minimizing core size.The instruction fetch pipeline (IFP) is a two-stage pipeline for prefetching instructions. The prefetched instruction stream is then gated into the two-stage operand execution pipeline (OEP), which decodes the instruction, fetches the required operands and then executes the required function. Because the IFP and OEP pipelines are decoupled by an instruction buffer that serves as a FIFO queue, the IFP can prefetch instructions in advance of their actual use by the OEP, thereby minimizing time stalled waiting for instructions. The OEP is implemented in a two-stage pipeline featuring a traditional RISC datapath with a dual-read-ported register file feeding an arithmetic/logic unit. Instruction Cache The instruction cache improves system performance by providing cached instructions to the execution unit in a single clock. The MCF5204 processor uses a 512-byte, direct-mapped instruction cache to achieve 13.5 MIPS at 33 MHz.The cache is accessed by physical addresses, where each 16-byte line consists of an address tag and a valid bit. The instruction cache also includes a bursting interface for 16- and 8-bit port sizes to quickly fill cache lines. MOTOROLA MCF5204 PRODUCT INFORMATION 3 Internal SRAM The 512-byte on-chip SRAM provides one clock-cycle access for the ColdFire core. This SRAM can store processor stack and critical code or data segments to maximize performance. UART Module The timer internal to the full duplex UART module provides baud-rate generation based on the system clock. Data formats can be 5, 6, 7, or 8 bits with even, odd, or no parity, and as many as two stop bits in 1/16 increments. Four-byte receive buffers and two-byte transmit buffers minimize CPU service calls. The UART module also provides several error-detection and maskable-interrupt capabilities. Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines. Timer Module The timer module includes two general-purpose timers, each of which contains a free-running 16-bit timer. One of the timers provides package pins for use in any of three modes. One mode captures the timer value with an external event. Another mode triggers an external signal or interrupts the CPU when the timer reaches a set value, while a third mode counts external events. Each timer unit has an 8-bit prescaler that allows programming of the clock input frequency, which is derived from the system clock. The programmable timeroutput pin generates either an active-low pulse or toggles the output. System Interface The MCF5204 processor provides a glueless interface to 8-bit and 16-bit port size SRAM, ROM, FLASH and peripheral devices with independent programmable control of the assertion and negation of chip-selects and write-enables. External Bus Interface The bus interface controller transfers information between the ColdFire core and external memory, and peripherals. The external bus interface provides as many as 22 bits of address bus space, a 16-bit data bus, and all associated control signals. This interface implements an extended asynchronous protocol that supports bursting operations. 8-Bit General-Purpose I/O Interface An 8-bit general-purpose programmable I/O port serves as either an input or an output on a bit-by-bit basis. This port is multiplexed with the timer, UART, and upper address pins. Chip-Selects Six programmable chip-select outputs provide signals that enable external memory and peripheral circuits. These signals also interface to 8- or 16- bit ports. The base address, access permissions, wait-state insertion, write protection, automatic termination, and timing wave forms are all programmable with configuration registers. Interrupt Controller. The interrupt controller provides user-programmable control of four external interrupt and four internal peripheral interrupts. Users can program each internal or external interrupt to any one of seven interrupt levels and four priority levels within each of these levels. System Protection. The MCF5204 processor contains a 16-bit software watchdog timer with an 8-bit prescaler. The programmable software watchdog timer provides either a level 7 interrupt or a hardware reset on timeout. The MCF5204 processor also contains a reset status register that indicates the cause of the last reset. IEEE 1149.1 JTAG.To help with system diagnostics and manufacturing testing, the MCF5204 processor includes dedicated user-accessible test logic that complies with the IEEE 1149.1 standard for boundary scan testability, often referred to as Joint Test Action Group, or JTAG. For more information, refer to the IEEE 1149.1 standard. 4 MCF5204 PRODUCT INFORMATION MOTOROLA System Debug Interface The ColdFire processor core debug interface supports real-time trace and background-debug mode. A fourpin background debug mode (BDM) interface provides system debug. The BDM is a proper subset of the BDM interface provided on Motorola's 683XX Family of parts. In real-time trace, four status lines provide information on processor activity in real time (PST pins). A 4-bit wide debug data bus (DDATA) displays operand data, which helps track the machine's dynamic execution path as the change-of-flow instructions execute. Pinout and Package The MCF5204 device is supplied in 16, 25, and 33MHz speeds in a 100-pin plastic thin quad flat pack package with the pinout shown in Figure 2. TCLK DSO/TDO BKPT/TMS DSI/TDI DSCLK/TRST PST[3:0]/HIZ DDATA(3:0) RESET CLOCK/ RESET 6 JTAG PORT DEBUG MODULE COLDFIRE CORE CS[5:0] CHIP SELECTS 512 BYTE ICACHE SYSTEM BUS CONTROLLER IRQ[3:0] BUSW/ATS DTACK WE RE UWE/UDS LWE/LDS 16 4 512 BYTE SRAM INTERRUPT CONTROLLER BUS INTERFACE 22 D[15:0] A[19:0] MTMOD UART SERIAL I/O CLK TIMER2 MODULE TIMER1 MODULE VDD(12) VSS(12) PARALLEL I/O PORT A[[20]/PP0 A[21]/PP1 TIN/PP2 Figure 2. MCF5204 Signal Block Diagram Documentation Additional and detailed information is available from Motorola literature distribution centers. DOCUMENT NUMBER MCF5204UM/AD MCF5200PRM/AD DOCUMENT TITLE MCF5204 User's Manual MCF5200 ColdFire Family Programmer's Reference Manual AVAILABILITY 3Q96 now MOTOROLA MCF5204 PRODUCT INFORMATION TOUT/PP3 TXD/PP4 RXD/PP5 CTS/PP6 RTS/PP7 5 DEVELOPMENT TOOLS AND EVALUATION SYSTEMS For information on third-party development tools support, refer to the High Performance Embedded Systems Source (BR729/D). ColdFire evaluation systems are available. Contact your local Motorola sales office for technical details and additional information on these boards. Visit the Motorola web site at http://www.mot.com/coldfire for additional information on any ColdFire family product. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. LiteratureDistribution Centers: Literature Distribution Centers: USA/EUROPE: Motorola Literature Distribution; P.O. Box85036. Arizona 85036 USA: Motorola Literature Distribution; P.O. Box 20912, Arizona 20912, JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo Milton Keynes, MK14 5BP, England. EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, 141 Japan JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141 Japan. ASIA-PACIFIC: Motorola Seminconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, ASIA-PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong SEMICONDUCTOR PRODUCT INFORMATION |
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