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UTC L8115
LINEAR INTEGRATED CIRCUIT
FET BIAS CONTROLLER WITH POLARISATION SWITCH AND TONE DETECTION
DESCRIPTION
The UTC L8115 is designed to meet the bias requirements of GaAs and HEMT FETs commonly used in satellite receiver LNBs, PMR, cellular telephones etc. with a minimum of external components. With the addition of two capacitors and a resistor the devices provide drain voltage and current control for three external grounded source FETs, generating the regulated negative rail required for FET gate biasing whilst operating from a single supply. This negative bias, at -2.8 volts, can also be used to supply other external circuits. The UTC L8115 includes bias circuits to drive up to three external FETs. A control input to the device selects either one of two FETs as operational, the third FET is permanently active. This feature is normally used as an LNB polarization switch. Also specific to Universal LNB applications is the 22kHz tone detection and logic output feature which is used to enable high and low band frequency switching. Drain current setting of the UTC L8115 is user selectable over the range 0 to 15mA, this is achieved with addition of a single resistor. The UTC L8115 gives 2.2 volts drain whilst.
SSOP-16(150mil)
SSOP-20(150mil)
FEATURES
*Provides bias for GaAs and HEMT FETs. *Drives up to three FETs. *Dynamic FET protection. *Drain current set by external resistor. *Regulated negative rail generator requires only 2 external capacitors. *Choice in drain voltage *Wide supply voltage range *Polarisation switch for LNBs *22KHz tone detection for band switching. *Tone detector ignores unwanted signals *Support fr MIMIC, FET and Bipolar local oscillator devices
APPLICATIONS
*Satellite receiver LNBs *Private mobile radio(PMR) *Cellular telephones
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UTC L8115
PIN CONFIGURATION
LINEAR INTEGRATED CIRCUIT
SSOP-16(150mil)
G1 D12 G2 G3 D3 GND CNB1 CNB2
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
VCC RCAL VPOL FIN LOV HB LB CSUB
SSOP-20(150mil)
G1 D1 G2 D2 G3 D3 GND C NB 1 C NB 2 N/C
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
VCC R C AL VPOL FIN CREC F O UT LO V HB LB C S UB
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage Supply Current Input Voltage Drain Current (per FET)(set by RCAL) Power Dissipation(Ta=25) Operating Temperature Storage Temperature
SYMBOL
Vcc Icc VIN ID SSOP-16(150mil) SSOP-20(150mil) PD Topr Tstg
RATINGS
-0.6 ~ 12 100 25 Continuous 0 ~ 15 500 500 -40 ~ 80 -50 ~ 85
UNIT
V mA V mA mW mW
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PARAMETER
Supply Voltage Supply Current
LINEAR INTEGRATED CIRCUIT
SYMBOL
Vcc Icc
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated, Ta=25, Vcc=5V, ID=10mA, RCAL=33k)
TEST CONDITONS
ID1= ID2 (or ID12)=ID3=0 ID1=0,ID2 (or ID12)= ID3=10mA, VPOL=14V ID2=0,ID1 (or ID12)= ID3=10mA, VPOL=15.5V ID1 and ID3=0, ILB=10mA ID1 and ID3=0, IHB=10mA (Internally generated) ICSUB=0 ICSUB=-200A CG=4.7nF,CD=10nF CG=4.7nF,CD=10nF
MIN.
5
TYP.
8.5 28 28 18 18 -2.8
MAX.
10 15 35 35 25 25 -2.55 -2.4 0.02 0.005 800
UNIT
V mA mA mA mA mA V V Vpkpk Vpkpk kHz
Substrate Voltage Output Noise Drain Voltage Gate Voltage Oscillator Frequency
VSUB
-3.05
END ENG fo
180
330
GATE CHARACTERISTICS
PARAMETER
Output Current Range Output Voltage Gate 1 Off Low High Output Voltage Gate 2 Off Low High Output Voltage Gate 3 Low High
SYMBOL
IGO VG1O VG1L VG1H VG2O VG2L VG2H VG3L VG3H
TEST CONDITONS
MIN.
-30
TYP.
MAX.
2000
UNIT
A V V V V V V V V
ID1=0mA, VPOL=14V, IGO1=-10A ID1=12mA, VPOL=15.5V, IGO1=-10A ID1=8mA, VPOL=15.5V, IGO1=0A ID2=0mA, VPOL=15.5V, IGO2=-10A ID2=12mA, VPOL=14V, IGO2=-10A ID2=8mA, VPOL=14V, IGO2=0A ID3=12mA, IGO3=-10A ID3=8mA, IGO3=0A
-2.5 -2.5 0.4 -2.5 -2.5 0.4 -3.0 0.4
-2.25 -2.25 0.75 -2.25 -2.25 0.75 -2.75 0.75
-2.0 -2.0 1.0 -2.0 -2.0 1.0 -2.0 1.0
DRAIN CHARACTERISTICS
PARAMETER SYMBOL TEST CONDITONS
Set by RCAL Vcc=5 ~ 10V Tj=-40 ~ +80 ID1=10mA,VPOL=15.5V ID2=10mA,VPOL=14V ID3=10mA,VPOL=15.5V Vcc=5 ~ 10V Tj=-40 ~ +80 VD1=0.5V,VPOL=14V VD2=0.5V,VPOL=15.5V 2.0 2.0 2.0
MIN.
8 0
TYP.
10
MAX.
12 15
UNIT
mA mA %/V %/
Current ID Current range IDrng Current Change IDV With Vcc IDT With Tj Drain 1 Change: High VD1 Drain 2 Change: High VD2 Drain 3 Change: High VD3 Voltage Change VDV With Vcc VDT With Tj Leakage Current Drain 1 IL1 * Drain 2 IL2 * * FOR SSOP-20(150mil) package only.
0.5 0.05 2.2 2.2 2.2 0.5 50
2.4 2.4 2.4
V V V %/V ppm
10 10
A A
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UTC L8115
PARAMETER
Filter Amplifier Bias Voltage 5 Input Impedance Amplifier Gain V Threshold 5 Output Stage Lov Volt.Range 6 Lov Bias Current LB Output Low VLBL LB Output High HB Output Low VHBL HB Output High
LINEAR INTEGRATED CIRCUIT
SYMBOL
VOUT Finz AG FVT VLov ILOV
TONE DETECTION CHARACTERISTICS
TEST CONDITONS
IFIN=0 VFIN=100mV p/p VFIN=100mV p/p 100 IL=50mA(LB or HB) VLOV=0 VLOV=0, IL=0 RIb-Csub=1M VLOV=3V, IL=0mA RIb-Gnd=1M VLOV=0, IL=10mA VLOV=3V ,IL=50mA VLOV=0 ,IL=0 Rhb-Csub=1M VLOV=3V, IL=0mA Rhb-Gnd=1M VLOV=0, IL=10mA VLOV=3V, IL=50mA Enabled 6 Enabled 6 Disabled 6 Disabled 6 Disabled 6 Disabled 6 Enabled 6 Enabled 6 -3.05 -0.01 -0.025 2.9 -3.05 -0.01 -0.025 2.9 -2.80 0 0 3.0 -2.80 0 0 3.0 -2.55 0.1 0.025 3.1 -2.55 0.1 0.025 3.1 V V V V V V -0.5 0.02
MIN.
1.75
TYP.
1.95 150 30 170
MAX.
2.15
UNIT
V V/mA mVp/p V A
350 Vcc-1.8 1.0
0.15
VLBH
VHBH
POLARITY SWITCH CHARACTERISTICS
PARAMETER SYMBOL TEST CONDITONS MIN. TYP. MAX. UNIT
VPOL=25V (Applied via RPOL=2k) A Input Current IPOL 10 25 40 Threshold VTPOL 14 14.75 15.5 V VPOL=25V (Applied via RPOL=2k) Voltage VPOL=25V (Applied via RPOL=2k) Switching Speed TSPOL 100 ms NOTES: 1. The negative bias voltages specified are generated on-chip using an internal oscillator. Two external capacitors, CNB and CSUB, of 47nF are required for this purpose. 2. The characteristics are measured using an external reference resistor RCAL of value 33k wired from pins RCAL to ground. 3. Noise voltage is not measured in production. 4. Noise voltage measurement is made with FETs and gate and drain capacitors in place on all outputs.CG,4.7nF,are connected between gate output and ground,CD,10nF,are connected between drain outputs and ground. 5. These parameters are linearly related to Vcc. 6. These parameters are measured using Test Circuit 1
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UTC L8115
TEST CIRCUIT 1
LINEAR INTEGRATED CIRCUIT
G1 V1 D1 5V DC G2 + D2 G3 D3 Gnd Cnb1 Cnb2 CNB N/C 47nF
UTC L8115 SSOP20(150mil) 1 Vcc Rcal Vpol Fin NC NC Lov HB LB Csub CSUB 47nF R1 33k CF1 4.7nF
R2 2k
V2 See Note 1
+ -
Note 1: V2 Characteristics Type: AC source Frequency: 22kHz Voltage: 350mVp/p Enabled 100mVp/p Disabled
Note:Same circuit used for SSOP16(150mil) but with adjusted pinout.
TYPCIAL CHARACTERISTICS
JFET Drain Curretn vs Rcal 16 14 Drain Current (mA) 12 Vsub (V) 10 8 6 4 2 0 0 20 40 60 Rcal (k) 80 100 Vcc=5V Vsub vs External Load Note: Operation with loads>200A is not guaranteed.
0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 0
Vcc=5V 6V 8V 10V
0.2
0.4
0.6
0.8
1.0
External Vsub Load (mA)
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UTC L8115
JFET Drain Voltage vs Drain Current 2.4
LINEAR INTEGRATED CIRCUIT
LB/HB Offset Voltage vs Load Current 4 2 0 -2 -4 -6 -8 0 10 20 30 Load Current (mA) 40 50 VCC=5V, VLOV=0V Ta=70 Ta=25 Ta=-40
2.3
2.2
2.1
Vcc=5V 6V 8V 10V
2
4
6 8 10 Drain Current (mA)
12
14
16
LB/HB Dropout Voltage vs Load Current 2.0 LB/HB Dropout Voltage (V) 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 0 10 20 30 Load Current (mA) 40 50 Ta=25 Ta=70 Vcc=5V Ta=-40
FUNCTIONAL DIAGRAM
+ DN QN GN + 20A CSUB Negative supply Gen. GND ID Sense + RCAL (Sets ID) ID Set Vcc VD set RCAL
LB/HB Offset voltage (mV)
Drain Voltage (V)
+ -
CSUB
CNB1 CNB
CNB2
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UTC L8115
FUNCTIONAL DESCRIPTION
LINEAR INTEGRATED CIRCUIT
The UTC L8115 provides all the bias requirements for external FETs, including the generation of the negative supply required for gate biasing, from the single supply voltage.The diagram above shows a single stage from the UTC series. It contains 3 such stages. The negative rail generator is common to both devices. The drain voltage of the external FET QN is set by the UTC L8115 to its normal operating voltage. This is determined by the on board VD Set reference, the UTC L8115 this is nominally 2.2 volts whilst. The drain current taken by the FET is monitored by the low value resistor ID Sense. The amplifier driving the gateof the FET adjusts the gate voltage of QN so that the drain current taken matches the current called for by an external resistor RCAL. Since the FET is a depletion mode transistor, it is often necessary to drive its gate negative with respect to groundto obtain the required drain current. To provide this capability powered from a single positive supply, the deviceincludes a low current negative supply generator. This generator uses an internal oscillator and two external capacitors, CNB and CSUB. The following schematic shows the function of the VPOL input. Only one of the two external FETs numberd Q1 and Q2 are powered at any one time,their selection is controlled by the input VPOL.This input is designed to be wired to the power input of the LNB via a high value(10k) resistor.With the input voltage of the LNB set at or below 14V,.FET Q2 will be enabled.With the input voltage at or above 15.5V,FET Q1 will be enabled.The disabled FET has its gate driven low and its drain terminal is switched open circuit. It is permissible to commect the drain pins D1 and D2 together if required by the application circuit;this is done internally in the SSOP-16(150mil) version.FET number Q3 is always active regardless of the voltage applied to VPOL.
D1 Q1 G1
Drain Voltage & Current Controller
Enable
+ 14.75V Reference
VPOL Input
20A VSUB
D2 Q2 G2
Drain Voltage & Current Controller
Enable
20A VSUB D3 Q3 G3 20A VSUB
Drain Voltage & Current Controller
Enable
For SSOP-20(150mil) Package
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UTC L8115
Control Input Switch Function Input sense 14 volts 15.5 volts
LINEAR INTEGRATED CIRCUIT
Polarisation Vertical Horizontal FET Q2 FET Q1 Select
For many LNB applications, tone detection for band switching is required. The UTC L8115 includes all the circuitry necessary to detect the presence of a 22kHz tone modulated on the supply input to the LNB. The main elements of the detector are an op-amp, a rectifier/smoother and a comparitor. The op-amp has a pre-set internal feedback resistor so that just a simple RC network wired to the input gives user defined gain and low frequency cut filter characteristics. The RC network components also serve two other purposes. The resistor provides overvoltage protection for the Vpol pin and the capacitor minimises tone interference of the Vpol threshold. The upper frequency roll-off of the op-amp has been set internally at above 100kHz to allow the amplifier to be used with other common tone switch frequencies. The rectifier/smoother/comparitor function is provided by a complex propriety circuit that allows the UTC L8115 to reliably detect wanted tones whilst ignoring low frequency square wave switch box signals, DiSEqCTM bursts and supply switching transients common when using DiSEqC-2TM ready set-top boxes. This is all achieved without the need for any further external components. The threshold of the comparitor is supply dependent, hence the gain of the preceding op-amp must be adjusted in line with supply voltage. See the table
below for recommended values for 22kHz detection, given for a range of supplies.
UTC L8115
+ Enable
Lov Input
LB Output
R2 LNB Input 2k CF1 4.7n
VPOL
+ Enable
HB Output
Fin
+
+ Ref
RECTIFIER COMPARATOR OUTPUT DRIVERS
Ref
FILTER
Table_1 Filter Components 5V Cf 4.7nF Rvpol(R2) 2k Note:Optimised for F(tone)=22kHz
6V 4.7nF 1.8k
Supply Voltage (Vcc) 7V 8V 4.7nF 10nF 1.5k 1.3k
9V 10nF 1.1k
10V 10nF 1.0k
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UTC L8115
APPLICATIONS CIRCUIT
LINEAR INTEGRATED CIRCUIT
The diagrams below show partial application circuits for the UTC series showing all external components required for appropriate biasing. The bias circuits are unconditionally stable over the full temperature range with the associated FETs and gate and drain capacitors in circuit. Capacitors C2 and C4 ensure that residual power supply and substrate generator noise is not allowed to affect other external circuits which may be sensitive to RF interference. They also serve to suppress any potential RF feedthrough between stages via the UTC device. These capacitors are required for all stages used. Values of 10nF and 4.7nF respectively are recommended however this is design dependent and any value between 1nF
and 100nF could be used. The capacitors CNB and CSUB are an integral part of the UTCs negative supply generator. The negative bias voltage is generated on-chip using an internal oscillator. The required value of capacitors CNB and CSUB is 47nF. This generator produces a low current supply of approximately -3 volts. Although this generator is intended purely to bias the external FETs, it can be used to power other external circuits via the CSUB pin. Resistor RCAL sets the drain current at which all external FETs are operated. If any bias control circuit is not required, its related drain and gate connections may be left open circuit without affecting the operation of the remaining bias circuits. The UTC L8115 has been designed to protect the external FETs from adverse operating conditions. With a JFET connected to any bias circuit, the gate output voltage of the bias circuit can not exceed the range -3V to 1V under any conditions, including powerup and powerdown transients. All the bias stages include drain currents limits which work independently in each stage. Should the negative bias generator be shorted or overloaded so that the drain current of the external FETs can no longer be controlled, the drain supply to FETs is shut down to avoid damage to the FETs by excessive drain current.
*L1 C2 10nF * L3 C6 10nF * C1 Q2 Q1 * L2 * C3 C4 10nF G1 D12 G2 G3 * Stripline Elements D3 Gnd Cnb1 Cnb2 CNB 47nF UTC L8115 SSOP16 (150mil) 1 Vcc LNB Downfeed R2 2k Vcc Rcal Vpol Fin Lov HB LB Csub CSUB 47nF R1 33k C1 4.7nF
* C5
SSOP16(150mil) Applications circuit
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UTC L8115
*L1 C2 10nF * C1 Q1 * L2 * C3 C4 10nF G1 D1 G2 D2 G3 D3 Gnd Cnb1 Cnb2 CNB N/C 47nF
LINEAR INTEGRATED CIRCUIT
Vcc UTC L8115 SSOP20(150mil) 1 LNB Downfeed R2 2k Vcc Rcal Vpol Fin NC NC Lov HB LB Csub CSUB 47nF R1
33k
CF1 4.7nF
* Stripline Elements
SSOP20(150mil) Applications circuit
The following block diagram shows the main section of an LNB designed for use with the Astra series of satellites. The UTC L8115 is the core bias and control element of this circuit. The UTC provides the negative rail, FET bias control, polarisation switch control, tone detection and band switching with the minimum of external components. Compared to other discrete component solutions the UTC circuit reduces component count and overall size required.
Single Universal LNB Block Diagram
Vertical Antenna
Gain Stage GaAs/HEMTFET
2
Regulator
Polarity Switch &Tone Detect Input Gain Stage GaAs/HEMTFET ASTRA Universal Band 10.70GHz-12.75 GHz
UTC L8115
Mixer
Gain Stage
3
+
IF down feed 950-2050 MHz - Low Band 1100 - 2150 MHz - High Band
Horizontal Antenna
Band Switch Output
1
Local Osc 1 9.75 GHz - Low Band Gain Stage GaAs/HEMTFET
Local Osc 2 10.6GHz - High Band
Tone detection and band switching is provided on the UTC L8115 devices. The following diagrams describes how this feature operates in an LNB and the external components required. The presence or absence of a 22kHz tone applied to pin FIN enables one of two outputs, LB and HB. A tone present enables HB and tone absent enables
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UTC L8115
LINEAR INTEGRATED CIRCUIT
LB. The LB and HB outputs are designed to be compatible with both MMIC and discrete (bipolar or FET) local oscillator applications, selected by pin LOV. Referring to Figure 1 wiring pin LOV to ground will force LB and HB to switch between -2.6V (disabled) and 0V (enabled). Referring to Figures 2 and 3 wiring pin LOV to a positive voltage source (e.g. a potential divider across VCC and ground set to the required oscillator supply voltage, VOSC) will force the LB and HB outputs to provide the required oscillator supply, VOSC, when enabled and 0V when disabled. Tone Detection Function LOV FIN LB HB GND 22kHz Disabled Enabled Enabled Disabled VOSC 22kHz Disabled Enabled Enabled Disabled Note 1: 0 volts in typical LNB applications but ependent on extenal circuits.
LB -3 volts GND Note 1 Vosc
HB GND -3 volts Vosc Note 1
APPLICATIONS LOCAL OSCILLATOR CIRCUITS
Vcc R2 LNB Downfeed
G1 D1 G2 D2 G3 D3 GND CNB1 CNB2 CNB 47nF N/C
1
UTC L8115
20
2.0k Vcc RCAL VPOL FIN NC NC Lov HB LB Csub CSUB
47nF
R1 33K
CF1 4.7nF
R3 10 R4 10 R6 300k
G2 CHB 100nF G1
Vcc
Local Osc. MMIC
R5 300k
CLB 100n
Figure 1
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UTC L8115
LINEAR INTEGRATED CIRCUIT
Vcc R2 LNB Downfeed
G1 D1 G2 D2 G3 D3 GND CNB1 CNB2 CNB 47nF N/C
1
UTC L8115
20 Vcc RCAL R1 VPOL 33K FIN NC NC Lov HB LB Csub CSUB
47nF
R5 2k
2.0K CF1 4.7nF
10.6GHz Local Osc. R3 10 9.75GHz Local Osc. R4 R6 3k 10 R8 CHB 100n CLB 100n R7
Figure 2
Vcc
R2 2.0K
LNB Downfeed
G1 D1 G2 D2 G3 D3 GND CNB1 CNB2 CNB 47nF N/C
1
UTC L8115
20 Vcc RCAL VPOL FIN NC NC Lov HB LB Csub CSUB
47nF
R5 2k R1 33K CF1 4.7nF
10.6GHz Local Osc. R3 9.75GHz Local Osc. R4 R6 3k 10 R7 Q1 10
R8 Q2 CLB 100n CHB 100n
Figure 3
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UTC L8115
LINEAR INTEGRATED CIRCUIT
UTC assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all UTC products described or contained herein. UTC products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.
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