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74AC174 * 74ACT174 Hex D-Type Flip-Flop with Master Reset
November 1988 Revised October 2000
74AC174 * 74ACT174 Hex D-Type Flip-Flop with Master Reset
General Description
The AC/ACT174 is a high-speed hex D-type flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The device has a Master Reset to simultaneously clear all flipflops.
Features
s ICC reduced by 50% s Outputs source/sink 24 mA s ACT174 has TTL-compatible inputs
Ordering Code:
Order Number 74AC174SC 74AC174SJ 74AC174MTC 74AC174PC 74ACT174SC 74ACT174SJ 74ACT174MTC 74ACT174PC Package Number M16A M16D MTC16 N16E M16A M16D MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names D0-D5 CP MR Q0-Q5 Description Data Inputs Clock Pulse Input Master Reset Input Outputs
FACT is a trademark of Fairchild Semiconductor Corporation.
(c) 2000 Fairchild Semiconductor Corporation
DS009935
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74AC174 * 74ACT174
Functional Description
The AC/ACT174 consists of six edge-triggered D-type flipflops with individual D inputs and Q outputs. The Clock (CP) and Master Reset (MR) are common to all flip-flops. Each D input's state is transferred to the corresponding flipflop's output following the LOW-to-HIGH Clock (CP) transition. A LOW input to the Master Reset (MR) will force all outputs LOW independent of Clock or Data inputs. The AC/ ACT174 is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.
Truth Table
Inputs MR L H H H CP D X H L X Output Q L H L Q

L
X
H = HIGH Voltage Level L = LOW Voltage Level = LOW-to-HIGH Transition X = Immaterial
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74AC174 * 74ACT174
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V V = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) PDIP 140C
-0.5V to +7.0V -20 mA +20 mA -0.5V to VCC + 0.5V -20 mA +20 mA -0.5V to V CC + 0.5V 50 mA 50 mA -65C to +150C
Recommended Operating Conditions
Supply Voltage (VCC) AC ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (V/t) AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (V/t) ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC
-40C to +85C
125 mV/ns
DC Electrical Characteristics for AC
Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum LOW Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN (Note 4) IOLD IOHD ICC (Note 4) Maximum Input Leakage Current Minimum Dynamic Output Current (Note 3) Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 4.0 0.002 0.001 0.001 TA = +25C Typ 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 0.1 TA = -40C to +85C Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 VIN = VIL or VIH 2.46 3.76 4.76 0.1 0.1 0.1 VIN = VIL or VIH 0.44 0.44 0.44 1.0 75 -75 40.0 A mA mA A V IOL = 12 mA IOL = 24 mA IOL = 24 mA (Note 2) VI = VCC or GND VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND V IOUT = 50 A V IOH = -12 mA IOH = -24 mA IOH = -24 mA (Note 2) V IOUT = -50 A V VOUT = 0.1V or VCC - 0.1V V Units Conditions VOUT = 0.1V or VCC - 0.1V
Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
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74AC174 * 74ACT174
DC Electrical Characteristics for ACT
Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIN ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum ICC/Input Minimum Dynamic Output Current (Note 6) Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 5.5 4.0 0.6 0.001 0.001 TA = +25C Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 0.1 TA = -40C to +85C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 1.0 1.5 75 -75 40.0 A mA mA mA A V Units V V V Conditions VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V IOUT = -50 A VIN = VIL or VIH V IOH = -24 mA IOH = -24 mA (Note 5) IOUT = 50 A VIN = VIL or VIH V IOL = 24 mA IOL = 24 mA (Note 5) VI = VCC, GND VI = VCC - 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND
Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for AC
Symbol fMAX tPLH tPHL tPHL Parameter Maximum Clock Frequency Propagation Delay CP to Qn Propagation Delay CP to Qn Propagation Delay MR to Qn
Note 7: Voltage Range 3.3 is 3.3V 0.3V Voltage Range 5.0 is 5.0V 0.5V
VCC (V) (Note 7) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
TA = +25C CL = 50 pF Min 90 100 2.0 1.5 2.0 1.5 2.5 1.5 Typ 100 125 9.0 6.0 8.5 6.0 9.0 7.0 11.5 8.5 11.0 8.0 11.5 9.0 Max
TA = -40C to +85C CL = 50 pF Min 70 100 1.5 1.0 1.5 1.0 2.0 1.5 12.5 9.5 12.0 9.0 12.5 10.5 Max
Units
MHz ns ns ns
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74AC174 * 74ACT174
AC Operating Requirements for AC
Symbol tS tH Parameter Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP tW tW tREC MR Pulse Width, LOW CP Pulse Width Recovery Time MR to CP
Note 8: Voltage Range 3.3 is 3.3V 0.3V Voltage Range 5.0 is 5.0V 0.5V
VCC (V) (Note 8) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
TA = +25C CL = 50 pF Typ 2.5 2.0 1.0 0.5 1.0 1.0 1.0 1.0 0 0 6.5 5.0 3.0 3.0 5.5 5.0 5.5 5.0 2.5 2.0
TA = -40C to +85C CL = 50 pF Guaranteed Minimum 7.0 5.5 3.0 3.0 7.0 5.0 7.0 5.0 2.5 2.0
Units
ns ns
ns ns ns
AC Electrical Characteristics for ACT
Symbol fMAX tPLH tPHL tPHL Maximum Clock Frequency Propagation Delay CP to Qn Propagation Delay CP to Qn Propagation Delay MR to Qn
Note 9: Voltage Range 5.0 is 5.0V 0.5V
Parameter
VCC (V) (Note 9) 5.0 5.0 5.0 5.0
TA = +25C CL = 50 pF Min 165 1.5 1.5 1.5 Typ 200 7.0 7.0 6.5 10.5 10.5 9.5 Max
TA = -40C to +85C CL = 50 pF Min 140 1.5 1.5 1.5 11.5 11.5 11.0 Max
Units
MHz ns ns ns
AC Operating Requirements for ACT
Symbol tS tH Parameter Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP tW tW trec MR Pulse Width, LOW CP Pulse Width, HIGH or LOW Recovery Time MR to CP
Note 10: Voltage Range 5.0 is 5.0V 0.5V
VCC (V) (Note 10) 5.0 5.0 5.0 5.0 5.0
TA = +25C CL = 50 pF Typ 0.5 1.0 1.5 1.5 -1.0
TA = -40C to +85C CL = 50 pF Guaranteed Minimum 1.5 2.0 3.0 3.0 0.5 1.5 2.0 3.5 3.5 0.5
Units
ns ns ns ns ns
Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 85.0 Units pF pF VCC = OPEN VCC = 5.0V Conditions
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74AC174 * 74ACT174
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A
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74AC174 * 74ACT174
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D
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74AC174 * 74ACT174
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16
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74AC174 * 74ACT174 Hex D-Type Flip-Flop with Master Reset
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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