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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853017
QUAD, 1-TO-1 DIFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
FEATURES
* 4 differential LVPECL / ECL 1:1 receivers * 4 differential LVPECL clock input pairs * PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL * Output frequency: >2GHz (typical) * Translates any single ended input signal to LVPECL levels with resistor bias on nPCLKx input * Output skew: TBD * Part-to-part skew: TBD * Propagation delay: 320ps (typical) * LVPECL mode operating voltage supply range: VCC = 2.375V to 5.25V * ECL mode operating voltage supply range: VCC = 0V, VEE = -5.25V to -2.375V * -40C to 85C ambient operating temperature * Pin compatible with MC100LVEL17
GENERAL DESCRIPTION
The ICS853017 is a quad 1-to-1, 2.5V/3.3V/5V differential LVPECL/ECL receiver and a member of HiPerClockSTM the HiperclocksTM family of High Performance Clock Solutions from ICS. The ICS853017 operates with a positive or negative power supply at 2.5V, 3.3V or 5V, and can accept both single-ended and differential inputs. For single-ended operation, an internally generated voltage, which is available on output pin VBB, can be used as a switching bias voltage on the unused input of the differential pair. VBB can also be used to rebias AC coupled inputs.
ICS
BLOCK DIAGRAM
D0 nD0 Q0 nQ0
PIN ASSIGNMENT
VCC D0 nD0 D1 nD1 D2 nD2 D3 nD3 VBB 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 VEE
D1 nD1
Q1 nQ1
D2 nD2
Q2 nQ2
D3 nD3
ICS853017
Q3 nQ3
V BB
20-Lead, 300-MIL SOIC 7.5mm x 12.8mm x 2.3mm body package M Package Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 853017AM www.icst.com/products/hiperclocks.html REV. A APRIL 21, 2004
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853017
QUAD, 1-TO-1 DIFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
Type Power Input Input Input Input Input Input Input Input Power Power Output Output Output Output Pulldown Pullup/ Pulldown Pulldown Pullup/ Pulldown Pulldown Pullup/ Pulldown Pulldown Pullup/ Pulldown Description Core supply pins. Non-inver ting differential clock input. Inver ting differential clock input. VCC/2 default when left floating. Non-inver ting differential clock input. Inver ting differential clock input. VCC/2 default when left floating. Non-inver ting differential clock input. Inver ting differential clock input. VCC/2 default when left floating. Non-inver ting differential clock input. Inver ting differential clock input. VCC/2 default when left floating. Bias Voltage. Negative supply pin. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 20 2 3 4 5 6 7 8 9 10 11 12, 13 14, 15 17, 18 19, 20 Name VCC D0 nD0 D1 nD1 D2 nD2 D3 nD3 VBB VEE nQ3, Q3 nQ2, Q2 nQ1, Q1 nQ0, Q0
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol RPULLDOWN RVCC/2 Parameter Input Pulldown Resistor Pullup/Pulldown Resistors Test Conditions Minimum Typical 75 50 Maximum Units K K
TABLE 3. CLOCK INPUT FUNCTION TABLE
Inputs D0:D3 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nD0:nD3 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 Q0:Q3 LOW HIGH LOW HIGH HIGH LOW Outputs nQ0:nQ3, HIGH LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels".
853017AM
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REV. A APRIL 21, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853017
QUAD, 1-TO-1 DIFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
5.5V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage -5.5V (ECL mode, VCC = 0) -0.5V to VCC + 0.5V 0.5V to VEE - 0.5V 50mA 100mA 0.5mA -65C to 150C 46.2C/W (0 lfpm) to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Character-
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Negative Supply Voltage, VEE Inputs, VI (LVPECL mode) Inputs, VI (ECL mode) Outputs, IO Continuous Current Surge Current VBB Sing/Source, IBB Storage Temperature, TSTG Package Thermal Impedance, JA
(Junction-to-Ambient)
Operating Temperature Range, TA -40C to +85C
istics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 5.25V; VEE = 0V
Symbol VCC IEE Parameter Core Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 3.3 46 Maximum 5.25 Units V mA
TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
Symbol VOH VOL VIH VIL VBB VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage(Single-Ended) Input Low Voltage(Single-Ended) Output Voltage Reference; NOTE 2 Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input D0, D1, D2, D3 High Current nD0, nD1,n D2, nD3 D0, D1, D2, D3 Input Low Current nD0, nD1,n D2, nD3
2.075 1.43 1.86 800 1.2 3.3 150 -10 -150 -10 -150 1.2
Min
-40C Typ
2.275 1.545
Max
Min
25C Typ
2.295 1.52
Max
Min
85C Typ
2.33 1.535
Max
Units
V V V V V
2.075 1.43 1.86 800 3.3 150
2.075 1.43 1.86 800 1.2 3.3 150 -10 -150
mV V A A A
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCC - 2V. NOTE 2: Single-ended input operation is limited. VCC 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for Dx, nDx is VCC + 0.3V.
853017AM
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REV. A APRIL 21, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853017
QUAD, 1-TO-1 DIFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
-40C Min Typ
1.475 0.745 1.275 0.63 800 1.2 2.5 150 -10 -10 1.2 1.275 0.63 800 2.5 150 -10 -150 1.2
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V
Symbol VOH VOL VIH VIL VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage(Single-Ended) Input Low Voltage(Single-Ended) Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 Input D0, D1, D2, D3 High Current nD0, nD1,n D2, nD3 Input Low Current D0, D1, D2, D3 25C Max Min Typ
1.495 0.72 1.275 0.63 800 2.5 150
85C Max Min Typ
1.53 0.735
Max
Units
V V V V
mV
V A A A
-150 -150 nD0, nD1,n D2, nD3 Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for Dx, nDx is VCC + 0.3V.
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 5V; VEE = 0V
Symbol VOH VOL VIH VIL VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage(Single-Ended) Input Low Voltage(Single-Ended) Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 Input D0, D1, D2, D3 High Current nD0, nD1,n D2, nD3 Input Low Current D0, D1, D2, D3
3.775 3.13 800 1.2 5 150 -10 -10 1.2
-40C Min Typ
3.975 3.245 3.775 3.13
25C Max Min Typ
3.995 3.22 3.775 3.13 800 5 150 -10 1.2
85C Max Min Typ
4.03 3.235
Max
Units
V V V V
800 5 150
mV
V A A A
-150 -150 nD0, nD1,n D2, nD3 -150 Input and output parameters var y 1:1 with VCC. VEE can var y +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCCO - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for Dx, nDx is VCC + 0.3V.
853017AM
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REV. A APRIL 21, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853017
QUAD, 1-TO-1 DIFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
-40C Min Typ
-1.025 -1.755 -1.225 -1.87 -1.44 800 VEE+1.2V 0 150 -10 -10 VEE+1.2V -1.225 -1.87 -1.44 800 0 150 -10 -150 VEE+1.2V
TABLE 4C. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V
Symbol VOH VOL VIH VIL VBB VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage(Single-Ended) Input Low Voltage(Single-Ended) Output Voltage Reference; NOTE 2 Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input D0, D1, D2, D3 High Current nD0, nD1,n D2, nD3 Input Low Current D0, D1, D2, D3 25C Max Min Typ
-1.005 -1.78 -1.225 -1.87 -1.44 800 0 150
85C Max Min Typ
-0.97 -1.765
Max
Units
V V V V V mV V A A A
-150 -150 nD0, nD1,n D2, nD3 Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCC - 2V. NOTE 2: Single-ended input operation is limited. VCC 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for Dx, nDx is VCC + 0.3V.
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V
Symbol fMAX tP LH tPHL Parameter Output Frequency Propagation Delay, Low-to-High; NOTE 1 Propagation Delay, High-to-Low; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise/Fall Time 20% to 80% Min Typ >2 320 320 TBD TBD 175
OR
VCC = 2.375V TO 5.25V; VEE = 0V
25C Max Min Typ >2 320 320 TBD TBD 175 Max Min 85C Typ >2 320 320 TBD TBD 175 Max Units GHz ps ps ps ps ps
-40C
tsk(o) tsk(pp)
tR/tF
All parameters tested 1GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
853017AM
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REV. A APRIL 21, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853017
QUAD, 1-TO-1 DIFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
Qx
SCOPE
VCC
nD0:nD3
LVPECL
nQx D0:D3
V
PP
Cross Points
V
CMR
VEE
V EE
-0.375V to -3.25V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx PART 1 Qx nQy PART 2 Qy
nQx Qx nQy Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nD0:nD3 nD0:D3
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
nQ0:nQ3 Q0:Q3
tp
LH
tp
HL
OUTPUT RISE/FALL TIME
853017AM
PROPAGATION DELAY
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REV. A APRIL 21, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853017
QUAD, 1-TO-1 DIFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input
PCLK
V_REF
nPCLK
C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50
125
FOUT FIN
125
Zo = 50 FOUT FIN
Zo = 50 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
Zo = 50 84 84
FIGURE 2A. LVPECL OUTPUT TERMINATION
853017AM
FIGURE 2B. LVPECL OUTPUT TERMINATION
REV. A APRIL 21, 2004
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853017
QUAD, 1-TO-1 DIFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
ground level. The R3 in Figure 3B can be eliminated and the termination is shown in Figure 3C.
TERMINATION
FOR
2.5V LVPECL OUTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
2.5V
VCC=2.5V
2.5V
VCC=2.5V
R1 250
Zo = 50 Ohm
R3 250
Zo = 50 Ohm
+
+
Zo = 50 Ohm
2,5V LVPECL Driv er
Zo = 50 Ohm
2,5V LVPECL Driv er
R1 50
R2 50
R2 62.5
R4 62.5
R3 18
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL Driv er
R1 50
R2 50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
853017AM
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REV. A APRIL 21, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853017
QUAD, 1-TO-1 DIFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
LVPECL CLOCK INPUT INTERFACE
The PCLKx /nPCLKx accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS PCLKx/nPCLKx input driven by the most common driver types. The input interfaces
3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm PCLK
Zo = 60 Ohm
2.5V
3.3V
2.5V
R3 120
SSTL
R2 50
R4 120
PCLK
Zo = 60 Ohm
Zo = 50 Ohm nPCLK HiPerClockS PCLK/nPCLK
nPCLK
HiPerClockS PCLK/nPCLK
R1 120
R2 120
FIGURE 4A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A CML DRIVER
FIGURE 4B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER
3.3V
3.3V
3.3V
3.3V 3.3V
R3 125
R4 125
PCLK
3.3V
Zo = 50 Ohm
LVDS
R5 100
Zo = 50 Ohm
C1
R3 1K
R4 1K
PCLK
C2
Zo = 50 Ohm
nPCLK
LVPECL
R1 84
R2 84
HiPerClockS Input
Zo = 50 Ohm
nPCLK
HiPerClockS PC L K /n PC LK
R1 1K
R2 1K
FIGURE 4C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
3.3V
3.3V
3.3V
3.3V LVPECL
Zo = 50 Ohm
C1
R3 84
R4 84
PCLK
Zo = 50 Ohm
C2
nPCLK
HiPerClockS PCLK/nPCLK
R5 100 - 200
R6 100 - 200
R1 125
R2 125
FIGURE 4E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE
853017AM
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REV. A APRIL 21, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853017
QUAD, 1-TO-1 DIFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER RELIABILITY INFORMATION
TABLE 6.
JAVS. AIR FLOW TABLE FOR 20 LEAD SOIC
by Velocity (Linear Feet per Minute)
JA
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 83.2C/W 46.2C/W
200
65.7C/W 39.7C/W
500
57.5C/W 36.8C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853017 is: 187
853017AM
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REV. A APRIL 21, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853017
QUAD, 1-TO-1 DIFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
20 LEAD SOIC
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 7. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 B C D E e H h L 10.00 0.25 0.40 0 -0.10 2.05 0.33 0.18 12.60 7.40 1.27 BASIC 10.65 0.75 1.27 8 Millimeters Minimum 20 2.65 -2.55 0.51 0.32 13.00 7.60 Maximum
Reference Document: JEDEC Publication 95, MS-013, MO-119 www.icst.com/products/hiperclocks.html
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853017AM
REV. A APRIL 21, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS853017
QUAD, 1-TO-1 DIFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER
Marking ICS853017AM ICS853017AM Package 20 Lead SOIC 20 Lead SOIC on Tape and Reel Count 38 per tube 1000 Temperature -40C to 85C -40C to 85C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS853017AM ICS853017AMT
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 853017AM
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REV. A APRIL 21, 2004

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