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KT3170
LOW POWER DTMF RECEIVER
INTRODUCTION
18-DIP-300A The KT3170 is a complete Dual Tone Multiple Frequency (DTMF) receiver that is fabricated by low power CMOS and the Switched-Capacitor Filter technology. This LSI consists of band split filters, which seperates counting section which verifies the frequency and duration of the received tones before passing the corresponding code to the output bus. It decodes all 16 DTMF tone pairs into a 4bits digital code. The externally required components are minimized by on chip provision of a differential input AMP, clock oscillator and latched three state interface. The on chip clock generator requires only a low cost TV cystal as an external component.
FEATURES
* * * * * * Detects all 16 standard tones. Low power consumption : 15mW (Typ) Single power supply : 5V Uses inexpensive 3.58MHz crystal Three state outputs for microprocessor interface Good quality and performance for using in exchange system * Power down mode/input inhibit
ORDERING INFORMATION
Device KT3170N Package 18-DIP-300A Operating - 25C ~ + 75C
APPLICATIONS
* * * * * * * * * * PABX Central Office Paging Systems Remote Control Credit Card Systems Key Phone System Answering Phone Home Automation System Mobile Radio Remote Data Entry
PIN CONFIGURATION
IN+
1 2 3 4 5 6 7 8 9 KT3170
18 17 16 15 14 13 12 11 10
VDD
IN-
SI/GTO
GS
ESO
VREF
DSO
IIN
Q4
PDN
Q3
OSC1
Q2
OSC2
Q1
GND
OE
Fig. 1
KT3170
LOW POWER DTMF RECEIVER
PIN DESCRIPTION
Pin No 1 2 3 4 5 Symbol IN + IN GS VREF IIN Description Non inverting input of the op amp. Inverting input of the op amp. Gain Select. The output used for gain adjustment of analog input signal with a feedback resistor. Reference Voltage output (VDD/2, Typ) can be used to bias the op amp input of VDD/2. Input inhibit. High input states inhibits the detection of tones. This pin is pulled down internally. Control input for the stand-by power down mode. Power down occurs 6 PDN when the signal on this input is in high states. This pin is pulled down internally. 7, 8 OSC1 OSC2 GND Clock input/output. A inexpensive 3.579545MHz crystal connected between these pins completes internal oscillator. Also, external clock can be used. Ground pin. Output Enable input. Outputs Q1-Q4 are CMOS push pull when OE is 10 OE High and open circuited (High impedance) when disabled by pulling OE low. Internal pull up resistor built in. Three state data output. When enabled by OE, these digital outputs 11 - 14 Q1 - Q4 provide the hexadecimal code corresponding to the last valid tone pair received. Delayed Steering Output. Indicates that valid frequencies have been present for the required guard time, thus constituting a valid signal. 15 DSO Presents a logic high when a received tone pair has been registered and the output latch is updated. Returns to logic low when the voltage on SI/GTO falls below VTH. Early Steering Outputs. Indicates detection of valid tone output a 16 ESO logic high immediately when the digital algorithm detects a recognizable tone pair. Any momentary loss of signal condition will cause ESO to return to low. Steering Input/Guard Time Output. A voltage greater the VTS detected at SI causes the device to register the detected tone pair 17 SI/GTO and update the output latch. A voltage less than VTS frees the device to accept a new tone pair. The GTO output acts to reset the external steering time constant, and its state is a function of ESO and the voltage on SI 18 VDD Power Supply (+5V, Typ)
9
KT3170
LOW POWER DTMF RECEIVER
ABSOLUTE MAXIMUM RATINGS
Characteristics Power Supper Voltage Analog Input Voltage Range Digital Input Voltage Range Output Voltage Range Current On Any Pin Operating Temperature Storage Temperature Symbol VDD VI (A) VI (D) VO II T OPR T STG Value 6 - 0.3 ~ VDD + 0.3 - 0.3 ~ VDD + 0.3 - 0.3 ~ VDD + 0.3 10 - 40 ~ + 85 -60 ~ + 150 Unit V V V V mA C C
ELECTRICAL CHARACTERISTICS
Characteristic Operating Voltage Operating Current Power Dissipation Input Voltage Low Input Voltage High Input Leakage Current Pull Up Current On OE Pin Analog Input Impedance Steering Input Threshold Voltage Output Voltage Low Output Current Output Current VREF Output Voltage VREF Output Resistance Analog Input Offset Voltage Power Supply Rejection Ratio Common Mode Rejection Ratio Open Loop Voltage Gain Open Loop Unit Gain Bandwidth Analog Output Voltage Swing Acceptable Capacitive Load Acceptable Resistive Load Analog Input Common Mode Voltage Range
(VDD = 5V, Ta = 25C, unless otherwise noted) Test Conditions VIN = GND or VDD OE = GND fIN = 1KHz No Load No Load VOL = 0.4V VOH = 4.6V Gain Setting Amp at 1KHz - 3.0V < VIN < 3.0V Gain Setting Amp at 1KHz RL = 100K GS GS No Load Min 4.75 3.5 8 2.2 4.97 1 0.4 2.4 Typ 3.0 15 0.1 7.5 10 2.5 0.8 10 25 60 60 65 1.5 4.5 100 50 3.0 2.8 Max 5.25 9.0 45 1.5 15 2.5 0.03 Unit V mA mW V V A A M V V V mA mA V K mV dB dB dB MHz VP-P pF K VP-P
Symbol VDD IDD PD VIL VIH II (LKG) IPU RI VTH VOL VOH IO (SINK) IO (SOURCE) VO (REF) RO (REF) VIO PSRR CMRR GV BW VO (P-P) CL RL VCM
KT3170
AC ELECTRICAL CHARACTERISTICS
Characteristic Valid Input Signal Range (each tone of composite signal) Dual Tone Twist Accept Acceptable Frequency Deviation Frequency Deviation Reject Third Tone Tolerance Noise Tolerance Dial Tolerance Crystal Clock Frequency Maximum Clock Input Rise Time Maximum Clock Input Fall Time Acceptable Clock Input Duty Cycle Acceptable Capacitive Load Tone Present Detect Time Tone Absent Detect Time Minimum Tone Duration Accept Maximum Tone Duration Reject Acceptable Interdigit Pause Rejectable Interdigit Pause Propagation Delay Time SI to Q Propagation Delay Time SI to DSO Output Data Setup Q to DSO Propagation Delay Time OE to Q (Enable) Propagation Delay Time OE to Q (disable) Notes : 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. TW f fR T3rd TN DT fCK tR (MAX) tF (MAX) DCK CL tDET (P) tDET (A) tTDA (MIN) tTDR (MAX) tIDP (A) tIDP (R) tD (SI-Q) tD (SI-D) tSU tD (QE-Q) EN tD (OE-Q) DIS Symbol VI (VAL)
LOW POWER DTMF RECEIVER
(VDD = 5V, Ta = 25C, fCK = 3.579545MHz) Test Conditions External Clock External Clock External Clock OSC2 PIN User Adjustable User Adjustable User Adjustable User Adjustable OE = High OE = High OE = High RL = 10K, CL = 50pF RL = 10K, CL = 50pF Min -29 3.5% -25 18 3.5759 40 5 0.5 20 20 Typ 10 -16 -12 22 3.5795 50 11 4 8 12 3.4 50 300 Max 1.0 1.5% 2Hz 3.5831 110 110 60 30 14 8.5 40 40 11 16 60 Unit dBm dB dB dB dB MHz nS nS % pF mS mS mS mS mS mS S S S nS nS
Digit sequence consists of all 16 DTMF tones. Tone duration = 40mS, Tone pause = 40mS. Nominal DTMF frequencies are used. Both tones in the composite signal have an equal amplitude. Tone pair is deviated by 1.5% 2Hz. Bandwidth limited (3KHz) Gaussian Noise. The precise dial tone frequencies are (350Hz and 440Hz) 2%. For an error rate of better than 1 in 10000. Referenced to lowest level frequency component in DTMF signal. Minimum signal acceptance level is measured with specitied maximum frequency deviation. This item also applies to a third tone injected onto the power supply. Referenced to Fig. 1 Input DTMF tone level at -28dBm.
LOW POWER DTMF RECEIVER
VCC 1 1 2 100K 3 R2 4 R1 100K 5 0.1F 13 12 8 11 10 VCC X - tal 1
X - tal 2
VCC VCC
VCC
18
R3 C1
18 17 16 15
17
300K
1 1 16 15
LED
b 14 2 2 13 c
VCC f
16 15 R10
10 g
9
87
6
f com a b
2 3 4 5 6 7
HL74HCTLS02
3
LT
g
14
KT3170
14 4 6 7 13 5 12 6 11 7 9 10
4 11 5 10 6 9 7 8 8
HL74LS47
RDO ABI d
a
13 R8 12 R7 c d GND 11 R6 10 R5 9 R4 12 3
KS58006
14
8 9
a d com c dp
45
VCC
1 4 7
2 5 8
3 6 9
*
0
#
Fig. 2
TEST CIRCUIT
KT3170
LTS542R
3
12
R9
KT3170
TIMING DIAGRAM
tT D R
(MAX)
LOW POWER DTMF RECEIVER
tTDA
(MIN)
tI D P
(A)
tI D P
(R)
DTMF #n DTMF INPUT
DTMF #n + 1
DTMF #n + 1
tD E T
(P)
tD E T
(A)
ESO
tPGT
tAGT V
TH
SI/GTO
t SU
DECODED TONE # (n - 1) Q1 - Q4
tD
(SI-D)
DSO
tD
OE
(OE-Q) EN
tD
(OE-Q) DIS
Fig. 3
DIGITAL OUTPUT
Outputs Q1-Q4 are CMOS push pull when enabled (EO = High) and open circuited (high impedance) when disabled by pulling EO = Low. These digital outputs provide the hexadecimal code corresponding to the DTMF signals. The table below describes the hexadecimal. NO 1 2 3 4 5 6 7 8 9 0 * # A B C D ANY Z : High Impedance H : High Logic Level L : Low Logic Level LOW 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 941 HIGH 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 1633 OE H H H H H H H H H H H H H H H H L Q4 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 Z Q3 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 Z Q2 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 Z Q1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Z
FREQUENCY FREQUENCY
KT3170
APPLICATION CIRCUIT
+5V IN+ 0.1uF 100K IN100K SI/GTO 300K V DD 0.1uF
LOW POWER DTMF RECEIVER
10nF C1
100K R1
IN+
GS
ESO
1 2 3 4
+ _
VREF
DSO
INGS 10nF C2 100K R2 R3 37.5K R2 60K R5 100K VREF
IIN
Q4
PDN 3.58MHz OSC1
Q3
Q2
KT3170
OSC2
Q1
GND
OE
All resistors are 1% tolerance All capacitors are 5% tolerance Fig. 4 Single Ended Input Configuration
R3 = R2R5/(R2+R5), VOLTAGE GAIN = R5/R1 2 2 INPUT IMPEDANCE : 2 R1 + (1/wC) All resistors are 1% tolerance All capacitors are 5% tolerance
Fig. 5 Differential Ended Input Configuration
VDD
C
C
SI/GTO
SI/GTO
R1 R2 ESO ESO
R1 R2
tPGT = (R1C) In (VDD/VDD-VTH) tAGT = (RPC) In (VDD/VTST) RP = R1R2/(R1 + R2) (a) Decreasing tAGT (tPGT > tAGT) Fig. 6 Guard Time Adjustment
tPGT = (RPC) In (VDD/VDD-VTH) tAGT = (R1C) In (VDD/VTH) RP = R1R2 (R1 + R2) (a) Decreasing tPGT (tPGT< tAGT)
KT3170
KT3170
30pF OSC1 3.579545MH z OSC2 OSC2 OSC1
T O O S C 1 o f n ex t K T 3 1 7 0
Fig. 7 Oscillator Connection

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