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| Integrated Circuit Systems, Inc. Advance Information M2004-04 Series M0 GND REF_CLK DIF_REF nDIF_REF REF_SEL PST Cx VCC * FREQUENCY TRANSLATION PLL SERIES PIN ASSIGNMENT (9 x 9 mm SMT) GENERAL DESCRIPTION The M2004-04 and its variants are VCSO (Voltage Controlled SAW Oscillator) based clock generator PLLs designed for clock frequency translation and jitter attenuation in a high-speed data communications system. External loop components allow the tailoring of PLL loop response. Includes: a Narrow Bandwidth control input pin (NBW Pin), a Loss of Lock (LOL) output, a Protection Switch Trigger (PST) input, and an external capacitor connection (Cx). Variants of the device add Hitless Switching with Phase Build-out (HS/PBO). FEATURES * Ideal for OC-48/192 data clock * Integrated SAW (surface acoustic wave) delay line * VCSO frequency from 300 to 700MHz (Specify VCSO center frequency at time of order) LOL M2 M3 M4 M5 VCC DNC DNC DNC 27 26 25 24 23 22 21 20 19 28 29 30 31 32 33 34 35 36 M2004-X4 (Top View) 18 17 16 15 14 13 12 11 10 MR NBW nFOUT FOUT GND N1 N0 VCC GND * Low phase jitter of < 0.5ps rms, typical (12kHz to 20MHz or 50kHz to 80MHz) * Pin-selectable configuration of divider ratios * Loss of Lock (LOL) output, Narrow Bandwidth input (NBW Pin), Protection Switch Trigger (PST) input, and an external capacitor connection (Cx) * Hitless Switching with Phase Build-out (HS/PBO) added to the M2004-14 and M2004-24 to ensure SONET/SDH MTIE and TDEV compliance during reference clock reselection * Differential LVPECL output * Reference clock inputs support differential LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL * Industrial temperature available * Single 3.3V power supply * Small 9 x 9 mm SMT (surface mount) package Figure 1: Pin Assignment Example Input / Output Frequency Combinations Input Clock VCSO ** Output (MHz) Freq (MHz) Freq (MHz) 19.44 38.80 77.76 155.52 25.00 625.00 622.08 77.76 155.52 311.04 622.08 156.25 Gigabit Ethernet OC-12 / 48 /192 Application Table 1: Example Input / Output Frequency Combinations * Series consists of parts numbered M2004-04, -14, and -24. ** Specify VCSO center frequency at time of order. SIMPLIFIED BLOCK DIAGRAM M2004-X4 DIF_REF nDIF_REF REF_CLK REF_SEL 0 1 M Divider N Divider FOUT nFOUT Loop Filter VCSO PST Cx 5 M5:2,M0 Figure 2: Simplified Block Diagram M2004-04 Series AI Rev 1.3 M2004-04 Series Frequency Translation PLL Series GND GND GND OP_IN nOP_OUT nVC VC OP_OUT nOP_IN 2 N1:0 MR 1 2 3 4 5 6 7 8 9 Revised 03Sep2003 Integrated Circuit Systems, Inc. Communications Modules w w w. i c s t . c o m tel (508) 852-5400 |
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