View MC74VHCT138A_287817.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
3-to-8 Line Decoder
The MC74VHCT138A is an advanced high speed CMOS 3-to-8 decoder fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. When the device is enabled, three Binary Select inputs (A0 - A2) determine which one of the outputs (Y0 - Y7) will go Low. When enable input E3 is held Low or either E2 or E1 is held High, decoding function is inhibited and all outputs go high. E3, E2, and E1 inputs are provided to ease cascade connection and for use as an address decoder for memory systems. The VHCT inputs are compatible with TTL levels. This device can be used as a level converter for interfacing 3.3V to 5.0V, because they have full 5V CMOS level output swings. The VHCT138A input structures provide protection when voltages between 0V and 5.5V are applied, regardless of the supply voltage. The output structures also provide protection when VCC = 0V. These input and output structures help prevent device destruction caused by supply voltage - input/output voltage mismatch, battery backup, hot insertion, etc. * * * * * * * * * * High Speed: tPD = 7.6ns (Typ) at VCC = 5V Low Power Dissipation: ICC = 4A (Max) at TA = 25C TTL-Compatible Inputs: VIL = 0.8V; VIH = 2.0V Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for 4.5V to 5.5V Operating Range Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300mA ESD Performance: HBM > 2000V; Machine Model > 200V Chip Complexity: 122 FETs or 30.5 Equivalent Gates
MC74VHCT138A
D SUFFIX 16-LEAD SOIC PACKAGE CASE 751B-05
DT SUFFIX 16-LEAD TSSOP PACKAGE CASE 948F-01
M SUFFIX 16-LEAD SOIC EIAJ PACKAGE CASE 966-01 ORDERING INFORMATION MC74VHCTXXXAD MC74VHCTXXXADT MC74VHCTXXXAM SOIC TSSOP SOIC EIAJ
PIN ASSIGNMENT
A0 A1 A2 E1 E2 E3 Y7 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6
FUNCTION TABLE
Inputs E3 X X L H H H H H H H H E2 X H X L L L L L L L L H X X L L L L L L L L X X X L L L L H H H H X X X L L H H L L H H X X X L H L H L H L H H H H L H H H H H H H H H H H L H H H H H H H H H H H L H H H H H Outputs A0 SELECT INPUTS A1 A2 H H H H H H L H H H H H H H H H H H L H H H H H H H H H H H L H H H H H H H H H H H L H H H H H H H H H H H L ENABLE INPUTS E3 E2 E1 6 5 4 15 1 2 3 E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y0 14 Y1 13 Y2 12 Y3 11 Y4 10 Y5 9 Y6 7 Y7
ACTIVE-LOW OUTPUTS
LOGIC DIAGRAM
H = high level (steady state); L = low level (steady state); X = don't care
6/97
(c) Motorola, Inc. 1997
1
REV 0
MC74VHCT138A
EXPANDED LOGIC DIAGRAM
15
Y0
14
Y1
A0
1
13
Y2
A1
2
12
Y3
11 A2 3 10 E2 E1 5 4 9
Y4
Y5
Y6
7
Y7
E3
6
MOTOROLA
2
VHC Data - Advanced CMOS Logic DL203 -- Rev 1
I I II I I I I I II II I II I I I I II I II I I I I I I I I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I I I II II I I I II II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I II II I I I I I II I I I I I I I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I II I I I I I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIII I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII I I I II I I IIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII I III I I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII III III I I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III III I I II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIII III II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Derating -- SOIC Packages: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C
II I I I I I IIIIIIIIIIIIIIIIIIIIIII I I I I I I IIIIIIII I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII II I I I I I I III IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS*
Symbol VCC Vout Tstg ICC IOK Iout Vin PD IIK Storage Temperature Power Dissipation in Still Air, DC Supply Current, VCC and GND Pins DC Output Current, per Pin Output Diode Current (VOUT < GND; VOUT > VCC)IIIIII 20 mA Input Diode Current DC Output Voltage DC Input Voltage DC Supply Voltage Parameter SOIC Packages TSSOP Package VCC = 0 High or Low State - 0.5 to + 7.0 - 0.5 to VCC + 0.5 - 65 to + 150 - 0.5 to + 7.0 - 0.5 to + 7.0 Value - 20 75 25 500 450 Unit mW mA mA mA
VHC Data - Advanced CMOS Logic DL203 -- Rev 1
DC ELECTRICAL CHARACTERISTICS
RECOMMENDED OPERATING CONDITIONS
Symbol
Symbol S bl
VCC
IOPD
Vout
ICCT
VOH
tr, tf
VOL
Vin
ICC
VIH
TA
VIL
Iin
Input Rise and Fall Time
Operating Temperature
DC Output Voltage
DC Input Voltage
DC Supply Voltage
Output Leakage Current
Quiescent Supply Current
Maximum Quiescent Supply Current
Maximum Input Leakage Current
Maximum Low-Level Output Voltage Vin = VIH or VIL
Minimum High-Level Output Voltage Vin = VIH or VIL
Maximum Low-Level Input Voltage
Minimum High-Level Input Voltage
Parameter P
Parameter
VOUT = 5.5V
Per Input: VIN = 3.4V Other Input: VCC or GND
Vin = VCC or GND
Vin = 5.5 V or GND
Test C di i T Conditions
VCC =5.0V 0.5V
VCC = 0 High or Low State
IOH = - 50A
IOH = - 8mA
IOL = 50A
IOL = 8mA
0 to 5.5
4.5 to 5.5
4.5 to 5.5
VCC V
3 5.5 5.5 4.5 4.5 4.5 4.5 0 - 40 Min 4.5 0 0 0 0 5.5 VCC + 85 Max 3.94 Min 5.5 5.5 4.4 2.0 20 ns/V Unit TA = 25C
_C
_C
V
V
V
V
V
V
Typ
0.0
4.5
0.1
1.35
0.36
Max
0.5
4.0
0.1
0.8
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open.
TA = - 40 to 85C
3.80
Min
4.4
2.0
MC74VHCT138A
v
1.0
1.50
20.0
0.44
Max
5.0
0.1
0.8
MOTOROLA
v
Unit Ui
mA A A V V V V
A
MC74VHCT138A
II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II II I I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I II II I II II I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
Symbol S bl tPLH, tPHL tPLH, tPHL tPLH, tPHL Cin Parameter P TA = 25C Typ 7.6 8.1 6.6 7.1 7.0 7.5 4 TA = - 40 to 85C Min 1.0 1.0 1.0 1.0 1.0 1.0 Max Test C di i T Conditions Min Max Unit Ui ns ns ns Maximum Propagation Delay, A to Y Maximum Propagation Delay, E3 to Y Maximum Propagation Delay, E2 or E1 to Y Maximum Input Capacitance VCC = 5.0 0.5V VCC = 5.0 0.5V VCC = 5.0 0.5V CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF 10.4 11.4 12.0 13.0 10.5 11.5 9.1 10.1 9.6 10.6 10 11.0 12.0 10 pF Typical @ 25C, VCC = 5.0V CPD Power Dissipation C P Di i i Capacitance (N i (Note NO TAG) pF F 49 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
SWITCHING WAVEFORMS
VALID A tPLH Y 1.5V 1.5V GND tPHL VOH VOL Y VALID 3V E3 tPHL 1.5V 1.5V GND tPLH VOH VOL 3V
Figure 1.
Figure 2.
3V E2 or E1 1.5V GND tPHL Y 1.5V VOL tPLH VOH
Figure 3.
TEST CIRCUIT
TEST POINT OUTPUT DEVICE UNDER TEST
CL*
* Includes all probe and jig capacitance
Figure 4. Test Circuit
MOTOROLA
4
VHC Data - Advanced CMOS Logic DL203 -- Rev 1
MC74VHCT138A
OUTLINE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
-A -
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 6.20 5.80 0.50 0.25 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019
-B -
1 8
P 8 PL 0.25 (0.010)
M
B
M
G F
K C -T SEATING -
PLANE
R X 45
M D 16 PL 0.25 (0.010)
M
J
T
B
S
A
S
DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948F-01 ISSUE O
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16
2X
L/2
9
J1 B -U-
L
PIN 1 IDENT. 1 8
SECTION N-N J
N 0.25 (0.010) 0.15 (0.006) T U
S
A -V- N F DETAIL E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
M
DIM A B C D F G H J J1 K K1 L M
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
VHC Data - Advanced CMOS Logic DL203 -- Rev 1
5
EE CC EE CC
-W-
MOTOROLA
MC74VHCT138A
OUTLINE DIMENSIONS
M SUFFIX PLASTIC SOIC EIAJ PACKAGE CASE 966-01 ISSUE O
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018).
16
9
LE Q1 E HE M_ L DETAIL P
1
8
Z D e A VIEW P
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
DIM A A1 b c D E e HE L LE M Q1 Z
MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.78
INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.031
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 303-675-2140 or 1-800-441-2447 JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. 81-3-5487-8488
MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, - US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 INTERNET: http://motorola.com/sps
MOTOROLA
6
MC74VHCT138A/D VHC Data - Advanced CMOS Logic DL203 -- Rev 1

▲Up To Search▲

Price & Availability of MC74VHCT138A

	To Download MC74VHCT138A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .