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February 1999
PBD 3517/1 Stepper Motor Drive Circuit
Description
PBD 3517/1 is a bipolar, monolithic, integrated circuit, intended to drive a stepper motor in a unipolar, bilevel way. One PBD 3517/1 and a minimum of external components form a complete control and drive unit for LS-TTL- or microprocessor-controlled stepper motor system for currents up to 500mA. The driver is suited for applications requiring least-posssible RFI. Motor performance can be increased by operating in a bilevel drive mode. This means that a high voltage pulse is applied to the motor winding at the beginning of a step, in order to give a rapid rise of current.
Key Features
* Complete driver and phase logic on chip * 2 x 350 mA continuous-output current * Half- and full-step mode generation * LS-TTL-compatible inputs * Bilevel drive mode for high step rates * Voltage-doubling drive possibilities * Half-step position-indication output * Minimal RFI * 16-pin plastic DIP package or 16 pin small outline wide body
VCC
VSS
PQR
LB
STEP PB2
INH OA OB
PA2 PA1
GND
16-pin plastic DIP 16-pin SO (wide body)
Figure 1. Block diagram. 1
P
B
HSM
PB
PB1
D
35
17
DIR
Phase Logic
PA
P B
RC
Mono F-F
LA
D
/1
35 17
/1
PBD 3517/1
PBD 3517/1
Maximum Ratings
Parameter Pin No. Symbol Min Max Unit
Voltage Logic supply Second supply Logic input Current Phase output Second-level output Logic input The zero output Temperature Operating junction temperature Storage temperature
16 15 6, 7, 10, 11 1, 2, 4, 5 13, 14 6, 7, 10, 11 8, 9
VCC VSS VI IP IL II I TJ TS PD PD
0 0 -0.3 0 -500 -10
7 45 6 500 0 6
V V V mA mA mA mA C C W W
-40 -55
+150 +150 1.6 1.3
Power Dissipation (Package Data) Power dissipation at TA = 25C, DIP package. Note 2. Power dissipation, SO package. Note 3.
Recommended Operating Conditions
Parameter Symbol Min Typ Max Unit
Logic supply voltage Second-level supply voltage Phase output current Second-level output current Operating junction temperature Set-up time Step-pulse duration
VCC VSS IP IL TJ ts tp
4.75 10 0 -350 -20 400 800
5
5.25 40 350 0 +125
V V mA mA C ns ns
ISS
tr
ICC
tf
PBD 3517/1
VCC 16 VSS 15 VLCE Sat
VI HSM or DIR t STEP
PQR
RC 12
Mono F-F
13
LA
IL
14 VSS VCC STEP DIR II IIL IIH HSM INH OA VI VIL VIH VOCE Sat 3 OB 7 6 10 11 9 8
LB
ILL
Phase Logic
PA
1 PB2 PB1 PA2 PA1 IP IPL VL
PB
2 5 4
IP
t
VPCE Sat GND VP
ts
tp td
t
Figure 2. Definition of symbols. 2
Figure 3. Timing diagram.
PBD 3517/1
Electrical Characteristics
Electrical characteristics at TA = +25C, VCC = +5.0 V, VMM = +40 V, VSS = +40 V unless otherwise specified.
Ref. Parameter Symbol Fig. Conditions Min Typ Max Unit
Supply current
ICC
2 2
INH = LOW INH = HIGH
45 12
60
mA mA
Phase outputs Saturation voltage Leakage current Turn on, turn off
VPCE Sat IPL td td VLCE Sat ILL tOn VIH VIL IIL IIH VOCE Sat
4 2 3 3
IP = 350 mA VP = 0 V +70C +125C
0.85 500 3 6
V A s s V A s V V A A V
Second-level outputs Saturation voltage Leakage current On time Logic inputs Voltage level, HIGH Voltage level, LOW Input current, low Input current, high Logic outputs Saturation voltage
4 2 11
IL = -350 mA VL = 0 V (note 4)
2.0 -500 220 260 300
2 2 2 2
2.0 0.8 VI = 0.4 V VI = 2.4 V IO = 1.6 mA -400 20
5
0.4
Notes 1. All voltages are with respect to ground. Current are positive into, negative out of specified terminal. 2 Derates at 12,8 mW/C above +25C. 3. Derates at 10.4 mW/C above +25C. 4. RT = 47 k, CT = 10 nF.
VLCE sat [V]
2.5
Allowable power dissipation [W]
2.5
0.5
Output Current [A]
2.0
TA= +25 C
2.0
0.4
TA= +25 C
1.5
1.5
0.3
1.0
1.0
0.2
0,5
0,5
0.1
0
0
0.1
0.2
0.3
0.4
0.5
0
IL [A]
0
50
100
150
0
0
0.2
0.4
0.6
0.8
1.0
Ambient temrature [C]
Output Voltage [V]
Figure 4. Typical phase output saturation voltage vs. output current.
Figure 5. Typical second level saturation voltage vs output current.
Figure
3
PBD 3517/1
Diagrams
How to use the diagrams: 1.
10 -2
Output Current [A]
10
1
Output Pulse Width [s] TA= +25 C
10 -1
8
TA= +25 C
6
10 -3
Rt
=
1
0M
R
t= t= t=
0 10 10 1k
k
What is the maximum motor current in the application? * The ambient temperature sets the maximum allowable power dissipation in the IC, which relates to the motor currents and the duty cycle of the bilevel function. For PBD 3517/1, without any measures taken to reduce the chip temperature via heatsinks, the power dissipation vs. temperature follows the curve in figure 4. * Figures 9 and 10 give the relationship between motor currents and their dissipations. The sum of these power dissipations must never exceed the previously-established value, or life expectancy will be drastically shortened. * When no bilevel or voltage doubling is utilized, the maximum motor current can be found directly in figure 9.
k
4
10 -4
R
2
R
10 -5
0
10 -6
0
0.2
0.4
0.6
0.8
1.0
0.01
0.1
1
10
100
1000
Output Voltage [V]
Ct Capacitance [nF]
Figure 7. Typical IO vs. VOCE Sat. "Zero output" saturation.
Figure 8. Typical tOn vs. CT/RT. Output pulse width vs. capacitance/resistance.
Output Pulse Width [s]
1 10 -1
10 0%
Output Current [A]
0.5
(II = 0)
TA= +25 C
Du 50 %
0.4
TA= +25 C
10 -2
10
%
tyc
yk
le
0.3
10 -3
1%
0.2
25 %
10 -4
2.
0.1
How to choose timing components. * Figure 7 shows the relationship between CT, RT, and tOn. Care must be taken to keep the tOn time short, otherwise the current in the winding will rise to a value many times the rated current, causing an overheated IC or motor.
10 -5
0.
1%
10 -6
0
0.001
0.01
0.1
1
10
100
0
0.2
0.4
0.6
0.8
1.0
fs Step frequency [kHz]
Power Dissipation [W]
Figure 9. Typical tOn vs. fs/dc. Output pulse width vs. step frequency/duty cycle.
Figure 10. Typical PDP vs. IP. Power dissipation without second-level supply (includes 2 active outputs = FULL STEP).
3.
What is the maximum tOn pulse-width at a given frequency? * Figure 8 shows the relationship between duty cycle, pulse width, and step frequency. Check specifications for the valid operating area.
Output Current [A]
-0.5
(Ip = 0)
Motor Current [mA]
-0.4
TA= +25 C
10%
-0.3
50%
100%
350
Normal Bilevel Bilevel without time limit
4.
Figures 4, 5 and 6 show typical saturation voltages vs. output current levels for different output transistors. Shaded areas represent operating conditions outside the safe operating area.
-0.2
5.
-0.1
0
0
0.2
0.4
0.6
0.8
1.0
tON
Time
Power Dissipation [W]
Figure 11. Typical PDI vs. II. Power dissipation in the bilevel pulse when raising to the II value. One active output. 4
Figure 12 . Motor Current 1p.
PBD 3517/1
PB2 1 PB1 2 GND 3 PA1 4 P A2 5 DIR 6 STEP 7 OB 8
16 VCC 15 VSS 14 LB
PB2 1 PB1 2 GND 3 PA1 4 P A2 5 DIR 6
16 VCC 15 VSS
PBD 3517/1N
13 LA 12 RC 11 INH 10 HSM 9 OA
PBD 13 LA 3517/1SO 12 RC
11 INH 10 HSM 9 OA
14 LB
STEP 7 OB 8
Figure 13. Pin configuration.
Pin Description
DIP SO-pack. Symbol Description
1 2 3 4 5 6 7 8 9 10
1 2 3 4 5 6 7 8 9 10
PB2 PB1 GND PA1 PA2 DIR STEP OB OA HSM
Phase output 2, phase B. Open collector output capable of sinking max 500 mA. Phase output 1, phase B. Open collector output capable of sinking max 500 mA. Ground and negative supply for both VCC and VSS. Phase output 1, phase A. Phase output 2, phase A. Direction input. Determines in which rotational direction steps will be taken. Stepping pulse. One step is generated for each negative edge of the step signal. Zero current half step position indication output for phase B. Zero current half step position indication output for phase A. Half-step mode. Determines whether the motor will be operated in half or full-step mot. When pulled low, one step pulse will correspond to a half step of the motor.
11 12 13 14 15 16
11 12 13 14 15 16
INH RC LA LB VSS VCC
A high level on the inhibit input turns all phase output off. Bilevel pulse timing pin. Pulse time is approximately ton = 0.55 * RT * CT Second level (bilevel) output, phase A. Second level (bilevel) output, Phase B. Second level supply voltage, +10 to +40 V. Logic supply voltage, nominally +5 V.
5
PBD 3517/1
Functional Description
The circuit, PBD 3517/1, is a high perform-ance motor driver, intended to drive a stepper motor in a unipolar, bilevel way. Bilevel means that during the first time after a phase shift, the voltage across the motor is increased to a second voltage supply, VSS, in order to obtain a more-rapid rise of current, see figure 11. The current starts to rise toward a value which is many times greater than the rated winding current. This compensates for the loss in drive current and loss of torque due to the back emf of the motor. After a short time, tOn, set by the monostable, the bilevel output is switched off and the winding current flows from the VMM supply, which is chosen for rated winding current. How long this time must be to give any increase in performance is determined by VSS voltage and motor data, the L/R time-constant. In a low-voltage system, where high motor performance is needed, it is also possible to double the motor voltage by adding a few external components, see figure 14. The time the circuit applies the higher voltage to the motor is controlled by a monostable flip-flop and determined by the timing components RT and CT. The circuit can also drive a motor in traditional unipolar way. An inhibit input (INH) is used to switch off the current completely. STEP -- Stepping pulse One step is generated for each negative edge of the STEP signal. In half-step mode, two pulses will be required to move one full step. Notice the set up time, ts, of DIR and HSM signals. These signals must be latched during the negative edge of STEP, see timing diagram, figure 3. DIR -- Direction DIR determines in which direction steps will be taken. Actual direction depends on motor and motor connections. DIR can be changed at any time, but not simultaneously with STEP, see timing diagram, figure 3. HSM determines whether the motor will be controlled in full-step or half-step mode. When pulled low, a step-pulse will correspond to a half step of the motor. HSM can be changed at any time, but not simultaneously with STEP, see timing diagram, figure 3.
Logic inputs
All inputs are LS-TTL compatible. If any of the logic inputs are left open, the circuit will accept it as a HIGH level. PBD 3517/1 contains all phase logic necessary to control the motor in a proper way.
VSS VMM + 5V
+ + +
D3
PBD 3517/1
C5
VSS 15
C3
VCC
C4
D2
D1
VCC
16
R11
PQR
RC 12
R10
CMOS, TTL-LS Input / Output-Device
Mono F-F
13
LA
R9
STEP CW / CCW HALF / FULL STEP NORMAL /INHIBIT (Optional Sensor)
R8
RT C T
STEP DIR HSM INH OA OB 7 6 10 11 9 8
14
LB
MOTOR
Phase Logic
PA
1 PB2 PB1 PA2 PA1
D3-D6
2 5 4
PB
3
GND
GND
D3-D6 are UF 4001 or BYV 27 trr < 100 ns GND (VMM,VSS)
GND (VCC)
Figure 14. Typical application.
VMM
+ 5V
+ +
R1 C4
VSS 15
PBD 3517/1
C3
VCC
D1
VCC
16
R10
PQR
Q1
RC 12
CMOS, TTL-LS Input / Output-Device
Mono F-F
13
LA
C1
+
R9
STEP CW / CCW HALF / FULL STEP NORMAL /INHIBIT (Optional Sensor)
R8
RT CT
STEP DIR HSM INH OA OB 7 6 10 11 9 8
14
LB
Q3 R2
Phase Logic
PA
1 PB2 PB1 PA2 PA1
Equal to Phase A R4
1/2 MOTOR R12 Q5 Q6 R13
PB
2 5 4
R5
3 GND
GND
GND (VCC) GND (VMM,VSS)
Figure 15. Voltage doubling with external transistors.
6
PBD 3517/1
INH -- Inhibit
Purpose of external components
For figures 14 and 15. Note that "Larger than ..." is normally the vice versa of "Smaller than ... ."
Component Purpose D1, D2 Passes low power to motor and prevents high power from shorting through low power supply Inductive current supressor Value I f = 1A 1N4001, UF4001 Larger than value Smaller than value Increases price Decreases max current capability
A HIGH level on the INH input,turns off all phase outputs to reduce current consumption.
Reset
An internal Power-On Reset circuit connected to Vcc resets the phase logic and inhibits the outputs during power up, to prevent false stepping.
D3 ... D6
I f = 1A trr = 100nS e.g. BYV27 UF4001 RGPP10G RGPP30D 2
Increases price
Decreases current turn-off capability Speeds up turnoff time.
Slows down turnoff time. Voltage at anode might exceed voltage breakdown Slows down Q1's turn-on and Q4's turn-off time. Slows down Q1's turn-off and Q4's turn-on time. Decreases ext. transistor IC max. Lowers 3517 power dissipation.
Output Stages
The output stage consists of four opencollector transistors. The second highvoltage supply contains Darlington transistors.
R1
Base drive current limitter
R = 20ohm P = R1
( (
Vmm
R1 + R2 Vmm
) )
Speeds up Q1's turn-on and Q4's turn-off time. Speeds up Q1's turn-off and Q4's turn-on time. Increases ext. transistor IC max. Increases 3517 power dissipation.
Phase Outputs
The phase outputs are connected directly to the motor as shown in figure 14.
R2, R3
Base discharge resistor R = 240ohm 2 P = R1
R1 + R2
R4 ... R7
External transistor base V - be ce mm V - V R= driver V be I4 R12 2 P > (I 4) * R4 Check hfe.
Bilevel Technique
The bilevel pulse generator consists of two monostables with a common RC network. The internal phase logic generates a trigger pulse every time the phase changes state. The pulse triggers its own monostable which turns on the output transistors for a precise period of time: tOn = 0.55 * CT * RT. See pulse diagrams, figures 16 through 20.
()
R8, R9
OA, OB pull-up resistors
R = 5ohm @ pull-up voltage = 5V. P= 2 (V CC) R
Increases noise sensitivity, worse logic-level definition
Increases noise immunity, better logic-level definition.
Less stress on OA, Stress on OA, OB OB output output transistors transistors. Increases motor current.
R10, R11
V Limit max. motor CESat Decreases motor mm-VMotor -V current. current. Resistors may R = I Motor max be omitted. (Check motor specifications first.) 15W Slows down external transistor turn-off time. Lowers 3517 power dissipation
Bipolar Phase Logic Output
Speeds up external transistor turn-off time. Increases 3517 power dissipation
Vbe R12 ... R15 External transistor base R= discharge. I12
P > Vbe* I12
RT, CT
Sets L and LB on time R = 47kohm, C = 10nf A when triggered by P < 250mW STEP. Stores the doubling voltage. C = 100 F V 45V C
Increases on time. Decreases on time.
C1, C2
Increases effective Decreases on-time during effective on-time voltage doubling during voltage doubling. Increases price, better filtering, decreases risk of IC breakdown Decreases price, more compact solution.
C3 ... C5
Filtering of supplyC 10 F voltage ripple and takeup of energy feedback from D3 ... D6
The OA and OB outputs are generated from the phase logic and inform an external device if the A phase or the B phase current is internally inhibited. These outputs are intended to support if it is legal to correctly go from a half-step mode to a full-step mode without loosing positional information. The PBD 3517/1 can act as a controller IC for 2 driver ICs, the PBL 3770A. Use PA1 and PB1 for phase control, and OA and OB for I0 and I1 control of current turn-off.
Applications Information
Risk for capacitor breakdown. Decreases max Im during voltage doubling.
V ,V or V Rated >V cc Increases price mm ss Q1, Q2 Activation transistor of voltage doubling. IC as motor requires. Increases price.
Logic inputs If any of the logic inputs are left open, the circuit will treat it as a high-level input. Unused inputs should be connected to proper voltage levels in order to get the highest noise immunity. Phase outputs 7
Q3, Q4
Charging of voltage doubling capacitor
I C=
(Vmm - Vf -VCE ) * C1
(
1 - 0.55 * RT * CT fStep
)
Q5 ... Q8
Motor current drive transistor.
IC as motor requires. PNP power trans.
Increases max Decreases max current capability. current capability.
PBD 3517/1
Phase outputs use a current-sinking method to drive the windings in a unipolar way. A common resistor in the center tap will limit the maximum motor current. Fast free-wheeling diodes must be used to protect output transistors from inductive spikes. Alternative solutions are shown in figures 21 through 25 on pages 6 - 10. Series diodes in VMM supply, prevent VSS voltage from shorting through the VMM power supply. However, these may be omitted if no bilevel is used. The VSS pin must not be connected to a lower voltage than VMM, but can be left unconnected. Zero outputs OA and OB, "zero A" and "zero B," are open-collector outputs, which go high when the corresponding phase output is inhibited by the half-step-mode circuitry. A pull-up resistor should be used and connected to a suitable supply voltage (5 kohms for 5V logic). See "Bipolar phase logic output." Interference To avoid interference problems, a good idea is to route separate ground leads to each power supply, where the only common point is at the 3517/1's GND pin. Decoupling of VSS and VMM will improve performance. A 5 kohm pull-up resistor at logic inputs will improve level definitions, especially when driven by open-collector outputs.
OB LB PB1 PB2 PA1 PA2 LA OA L P P P P P P L
DIR INH HSM STEP OB LB PB1 PB2 PA1 PA2 LA OA
H L H P L P P P P P P L
Figure 16. Full-step mode, forward. 4-step sequence. Gray-code +90 phase shift.
DIR INH HSM STEP H L H P
Figure 17. Full-step mode, reverse. 4-step sequence. Gray-code -90 phase shift.
DIR INH HSM STEP OB LB PB1 PB2 PA1 PA2 LA OA H L L P
C
P P P P P P P P
Figure 18. Half-step mode, forward. 8-step sequence.
DIR INH HSM STEP OB LB PB1 PB2 PA1 PA2 LA OA L L L P
C
Input and Output Signals for Different Drive Modes
The pulse diagrams, figures 16 through 20, show the necessary input signals and the resulting output signals for each drive mode. On the left side are the input and output signals, the next column shows the state of each signal at the cursor position marked "C." STEP is shown with a 50% duty cycle, but can, of course, be with any duty cycle, as long as pulse time (tp) is within specifications. PA and PB are displayed with low level, showing current sinking. LA and LB are displayed with high level, showing current sourcing.
P P P P P P P P
Figure 19. Half-step mode, reverse. 8-step sequence.
DIR INH HSM STEP OB LB PB1 PB2 PA1 PA2 LA OA L H L P
C
P P H H H H P P
Figure 20. Half-step mode, inhibit. 8
PBD 3517/1
RExt
i
R
VZ
Figure 21. Diode turn-off circuit.
Figure 22. Resistance turn-off circuit.
Figure 23. Zener diode turn-off circuit.
7.
To change actual motor rotation direction, exchange motor connections at PA1 and PA2 (or PB1 and PB2). Half-stepping. in the half-step mode, the power input to the motor alternates between one or two phase windings. In half-step mode, motor resonances are reduced. In a twophase motor, the electrical phase shift between the windings is 90 degrees. The torque developed is the vector sum of the two windings energized. Therefore, when only one winding is energized, which is the case in half-step mode for every second step, the torque of the motor is reduced by approximately 30%. This causes a torque ripple. Ramping. Every drive system has inertia which must be considered in the drive scheme. The rotor and load inertia plays a big role at higher speeds. Unlike the DC motor, the stepper motor is a synchronous motor and does not change speed due to load variations. Examination of typical stepper motors' torque versus speed curves indicates a sharp torque drop-off for the start-stop without error curve. The reason for this is that the torque requirements increase by the cube of the speed change. As it can be seen, for good motor performance, controlled acceleration and deceleration should be considered.
8.
V1
CS
V2
0V Power supply
Figure 24. Power return turn-off circuit.
Figure 25. Power return turn-off circuit for bilevel . necessary to connect in series with center tap. This changes the L/R time constant. 5. Never use LA or LB for continuous output at high currents. LA and LB ontime can be altered by changing the RC net. An alternative is to trigger the mono-flip-flop by taking a STEP and then externally pulling the RC pin (12) low (0V) for the desired ontime. Avoid VMM and VSS power supplies with serial diodes (without filter capacitor) and/or common ground with VCC. The common place for ground should be as close as possible to the IC's ground pin (pin 3). 9.
User Hints
1. 2. Never disconnect ICs or PC-boards when power is supplied. If second supply is not used, disconnect and leave open VSS, LA, LB, and RC. Preferably replace the VMM supply diodes (D1, D2) with a straight connection. Remember that excessive voltages might be generated by the motor, even though clamping diodes are used. Choice of motor. Choose a motor that is rated for the current you need to establish desired torque. A high supply voltage will gain better stepping performance. If the motor is not specified for the VMM voltage, a current limiting resistor will be
3.
6.
4.
9
PBD 3517/1
Common Fault Conditions
* VMM supply not connected, or VMM supply not connected through diodes. * The inhibit input not pulled low or floating. Inhibit is active high. * A bipolar motor without a center tap is used. Exchange motor for unipolar version. Connect according to figure 14. * External transistors connected without proper base-current supply resistor. * Insufficient filtering capacitors used. * Current restrictions exceeded. * LA and LB used for continuous output at high currents. Use the RC network to set a proper duty cycle according to specifications, see figures 6 through 11. * A common ground wire is used for all three power supplies. If possible, use separate ground leads for each supply to minimize power interference.
Drive Circuits
If high performance is to be achieved from a stepper motor, the phase must be energized rapidly when turned on and also de-energize rapidly when turned off. In other words, the phase current must increase/decrease rapidly at phase shift.
Zener diode T O C (figure 23) Relatively high VZ gives: -- -- Relatively fast current decay Energy lost mainly in VZ
-- Potential cooling problems Power return T O C for unipolar drive (figure 24) Relatively high VZ gives: -- -- -- -- -- Relatively fast current decay Energy returned to power supply Only small energy losses Winding leakage flux must be considered Potential cooling problems
Phase Turn-off Considerations
When the winding current is turned off the induced high voltage spike will damage the drive circuits if not properly suppressed. Different turn-off circuits are used; e. g. : Diode turn-off circuit (figure 21) -- Slow current decay -- -- Energy lost mainly in winding resistance Potential cooling problems.
Power return to T O C for bilevel drive (figure 25) -- -- -- -- Very fast current decay Energy returned to power supply Only small energy losses Winding leakage flux must be considered
Resistance T O C (figure 22) -- -- -- Somewhat faster current decay Energy lost mainly in R-Ext Potential cooling problems
Ordering Information
Package Part No.
DIP Tube SO Tube SO Tape & Reel
PBD 3517/1NS PBD 3517/1SOS PBD 3517/1SOT
Information given in this data sheet is believed to be accurate and reliable. However no responsibility is assumed for the consequences of its use nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Ericsson Components. These products are sold only according to Ericsson Components' general conditions of sale, unless otherwise confirmed in writing.
Specifications subject to change without notice. 1522-PBD 3517/1 Uen Rev. C (c) Ericsson Components AB 1999
Ericsson Components AB SE-164 81 Kista-Stockholm, Sweden Telephone: +46 8 757 50 00 10

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