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INTEGRATED CIRCUITS
SA7026 1.3GHz low voltage fractional-N dual frequency synthesizer
Product specification Supersedes data of 1999 Apr 16 1999 Nov 04
Philips Semiconductors
Philips Semiconductors
Product specification
1.3GHz low voltage fractional-N dual synthesizer
SA7026
GENERAL DESCRIPTION
The SA7026 BICMOS device integrates programmable dividers, charge pumps and a phase comparator to implement a phase-locked loop. The device is designed to operate from 3 NiCd cells, in pocket phones, with low current and nominal 3 V supplies. The synthesizer operates at VCO input frequencies up to 1.3 GHz. The synthesizer has fully programmable main, auxiliary and reference dividers. All divider ratios are supplied via a 3-wire serial programming bus. Separate power and ground pins are provided to the analog and digital circuits. The ground leads should be externally short-circuited to prevent large currents flowing across the die and thus causing damage. VDDCP must be greater than or equal to VDD. The charge pump current (gain) is set by an external resistance at RSET pin. Passive loop filters could be used; the charge pump operates within a wide voltage compliance range to provide a wider tuning range.
LOCK TEST VDD GND RFin+ RFin- GNDCP PHP PHI 1 2 3 4 5 6 7 8 9 20 PON 19 STROBE 18 DATA 17 CLOCK 16 REFin+ 15 REFin- 14 RSET 13 VDDCP 12 AUXin 11 PHA
GNDCP 10
SR01649
Figure 1. Pin Configuration
FEATURES
APPLICATIONS
* Low phase noise * Low power * Fully programmable main and auxiliary dividers * Normal & Integral charge pumps outputs * Fast Locking Adaptive mode design * Internal fractional spurious compensation * Hardware and software power down * Split supply for VDD and VDDCP
QUICK REFERENCE DATA
SYMBOL VDD VDDCP IDDCP+IDD IDDCP+IDD fVCO fAUX fREF fPC Tamb PARAMETER Supply voltage Analog supply voltage Total supply current Total supply current in power-down mode Input frequency Input frequency Crystal reference input frequency Maximum phase comparator frequency Operating ambient temperature
* 350 to 1300 MHz wireless equipment * Cellular phones (all standards) * WLAN * Portable battery-powered radio equipment.
CONDITIONS
MIN. 2.7
TYP. - - 7.5 1 - - -
MAX. 5.5 5.5 8.8 - 1300 550 40 4
UNIT V V mA A MHz MHz MHz MHz C
VDDCP w VDD Main and Aux. on
2.7 - - 350 10 5 - -40
-
+85
ORDERING INFORMATION
PACKAGE TYPE NUMBER NAME SA7026DH TSSOP20 DESCRIPTION Plastic thin shrink small outline package; 20 leads; body width 4.4 mm VERSION SOT360-1
1999 Nov 04
2
853-2159 22635
Philips Semiconductors
Product specification
1.3GHz low voltage fractional-N dual synthesizer
SA7026
VDD 3 17 CLOCK DATA 18 2-BIT SHIFT REGISTER 22-BIT SHIFT REGISTER PUMP CURRENT SETTING PUMP BIAS
VDDCP 13
STROBE
19
ADDRESS DECODER
CONTROL LATCH
14
RSET
LOAD SIGNALS LATCH 5 RFin+ RFin- 6 MAIN DIVIDER PHASE DETECTOR 8 PHP
COMP
AMP SM LATCH 16 REFin+ REFin- 15 SA 1 LOCK REFERENCE DIVIDER 2 2 22 9 PHI
LATCH AUXin 12 AUX DIVIDER AMP TEST 2 4 GND
PHASE DETECTOR
11
PHA
20 7, 10 GNDCP
PON
SR01496
Figure 2. Block Diagram
PINNING
SYMBOL LOCK TEST VDD GND RFin+ RFin- GNDCP PHP PHI GNDCP PIN 1 2 3 4 5 6 7 8 9 10 DESCRIPTION Lock detect output Test (should be either grounded or connected to VDD) Digital supply Digital ground RF input to main divider RF input to main divider Charge pump ground Main normal charge pump Main integral charge pump Charge pump ground SYMBOL PHA AUXin VDDCP RSET REFin- REFin+ CLOCK DATA STROBE PON PIN 11 12 13 14 15 16 17 18 19 20 DESCRIPTION Auxiliary charge pump output Input to auxiliary divider Charge pump supply voltage External resistor from this pin to ground sets the charge pump current Reference input Reference input Programming bus clock input Programming bus data input Programming bus enable input Power down control
1999 Nov 04
3
Philips Semiconductors
Product specification
1.3GHz low voltage fractional-N dual synthesizer
SA7026
Limiting values
SYMBOL VDD VDDCP VDDCP-VDD Vn Vn VGND Tstg Tamb Tj Digital supply voltage Analog supply voltage Difference in voltage between VDDCP and VDD (VDDCP VDD) Voltage at pins 1, 2, 5, 6, 12, 15 to 20 Voltage at pin 8, 9, 11 Difference in voltage between GNDCP and GND (these pins should be connected together) Storage temperature Operating ambient temperature Maximum junction temperature PARAMETER -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -55 -40 MIN. +5.5 +5.5 +2.8 VDD + 0.3 VDDCP + 0.3 +0.3 +125 +85 150 MAX. V V V V V V _C _C _C UNIT
Handling
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices.
Thermal characteristics
SYMBOL Rth j-a PARAMETER Thermal resistance from junction to ambient in free air VALUE 135 UNIT K/W
1999 Nov 04
4
Philips Semiconductors
Product specification
1.3GHz low voltage fractional-N dual synthesizer
SA7026
CHARACTERISTICS
VDDCP = VDD = +3.0V, Tamb = +25C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supply; pins 3, 13 VDD VDDCP IDDTotal IStandby Digital supply voltage Analog supply voltage Synthesizer operational total supply current Total supply current in power-down mode VDDCP w VDD VDD = +3.0V (with main and aux on) logic levels 0 or VDD 2.7 2.7 - - - - 7.5 1 5.5 5.5 8.8 - V V mA
RFin main divider input; pins 5, 6 fVCO VRFin(rms) VCO input frequency AC-coupled input signal level Rin (external) = Rs = 50; single-ended drive; max. limit is indicative @ 500 to 1300 MHz fVCO = 1.2 GHz fVCO = 1.2 GHz 350 -18 - - 1300 0 MHz dBm
ZIRFin CIRFin Nmain fPCmax
Input impedance (real part) Typical pin input capacitance Main divider ratio Maximum loop comparison frequency
- - 512
300 1 - -
- - 65535 4
pF
indicative, not tested
-
MHz
AUX reference divider input; pin 12 fAUXin VAUXin ZAUXin CAUXin NAUX Input frequency range AC-coupled AC coupled input signal level Input impedance (real part) Typical pin input capacitance Auxiliary division ratio Rin (external) = RS = 50; ( ) max. limit is indicative fVCO = 500 MHz fVCO = 500 MHz 20 -18 80 - - 128 - - - 3.9 1 - 550 0 632 - - 16383 MHz dBm mVPP k pF
Reference divider input; pins 15, 16 fREFin VRFin ZREFin CREFin RREF Input frequency range from TCXO AC-coupled input signal level Input impedance (real part) Typical pin input capacitance Reference division ratio single-ended drive; max. limit is indicative fREF = 20 MHz fREF = 20 MHz SA = SM = "000" 5 360 - - 4 - - 10 1 - 40 1300 - - 1023 MHz mVPP k pF
Charge pump current setting resistor input; pin 14 RSET VSET External resistor from pin to ground Regulated voltage at pin RSET = 7.5 k 6 - 7.5 1.25 15 - k V
Charge pump outputs (including fractional compensation pump); pins 8, 9, 11; RSET = 7.5 k, FC = 80 ICP IMATCH IZOUT ILPH VPH Charge pump current ratio to ISET1 Sink-to-source current matching Output current variation versus VPH Charge pump off leakage current Charge pump voltage compliance
2
Current gain = IPH/ISET VPH = 1/2 VDDCP VPH in compliance range VPH = 1/2 VDDCP
-15 -10 -10 -10 0.7 -
+15 +10 +10 +10 VDDCP-0.8
% % % nA V
1999 Nov 04
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Philips Semiconductors
Product specification
1.3GHz low voltage fractional-N dual synthesizer
SA7026
CHARACTERISTICS (continued)
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Phase noise (condition RSET = 7.5 k, CP = 00) Synthesizer's contribution to close-in phase noise of 900 MHz RF signal at 1 kHz offset. GSM fREF = 13MHz, TCXO, fCOMP = 1MHz indicative, not tested TDMA fREF = 19.44MHz, TCXO, fCOMP = 240kHz indicative, not tested - -85 - dBc/Hz - -90 - dBc/Hz
L(f)
Synthesizer's contribution to close-in phase noise of 800 MHz RF signal at 1 kHz offset.
Interface logic input signal levels; pins 2, 17, 18, 19, 20 VIH VIL ILEAK HIGH level input voltage LOW level input voltage Input leakage current logic 1 or logic 0 0.7*VDD -0.3 -0.5 - - - VDD+0.3 0.3*VDD +0.5 V V A
Lock detect output signal (in push/pull mode); pin 1 VOL VOH NOTES: V SET 1. ISET = R bias current for charge pumps. SET 2. The relative output current variation is defined as: DI OUT (I 2-I 1) + 2. ; with V 1 + 0.7V, V 2 + V DDCP -0.8V (See Figure 3.) I(I 2 ) I 1)I I OUT LOW level output voltage HIGH level output voltage Isink = 2 mA Isource = -2 mA - VDD-0.4 - - 0.4 - V V
CURRENT
IZOUT
I2
I1
V1
V2
VPH
I2
I1
SR00602
Figure 3. Relative Output Current Variation
1999 Nov 04
6
Philips Semiconductors
Product specification
1.3GHz low voltage fractional-N dual synthesizer
SA7026
FUNCTIONAL DESCRIPTION Main Fractional-N divider
The RFin inputs drive a pre-amplifier to provide the clock to the first divider stage. For single ended operation, the signal should be fed to one of the inputs while the other one is AC grounded. The pre-amplifier has a high input impedance, dominated by pin and pad capacitance. The circuit operates with signal levels from -18 dBm to 0 dBm, and at frequencies as high as 1.3 GHz. The divider consists of a fully programmable bipolar prescaler followed by a CMOS counter. Total divide ratios range from 512 to 65536. At the completion of a main divider cycle, a main divider output pulse is generated which will drive the main phase comparator. Also, the fractional accumulator is incremented by the value of NF. The accumulator works with modulo Q set by FMOD. When the accumulator overflows, the overall division ratio N will be increased by 1 to N + 1, the average division ratio over Q main divider cycles (either 5 or 8) will be NF Nfrac + N ) Q The output of the main divider will be modulated with a fractional phase ripple. The phase ripple is proportional to the contents of the fractional accumulator and is nulled by the fractional compensation charge pump. The reloading of a new main divider ratio is synchronized to the state of the main divider to avoid introducing a phase disturbance.
Auxiliary divider
The AUXin input drives a pre-amplifier to provide the clock to the first divider stage. The pre-amplifier has a high input impedance, dominated by pin and pad capacitance. The circuit operates with signal levels from -18dBm to 0 dBm (80 to 636 mVpp), and at frequencies as high as 550 MHz. The divider consists of a fully programmable bipolar prescaler followed by a CMOS counter. Total divide ratios ranges from 128 to 16383.
Reference divider
The reference divider consists of a divider with programmable values between 4 and 1023 followed by a three bit binary counter. The 3 bit SM (SA) register (see figure 4) determines which of the 5 output pulses are selected as the main (auxiliary) phase detector input.
Phase detector (see Figure 5)
The reference and main (aux) divider outputs are connected to a phase/frequency detector that controls the charge pump. The pump current is set by an external resistor in conjunction with control bits CP0 and CP1 in the C-word (see Charge Pump table). The dead zone (caused by finite time taken to switch the current sources on or off) is cancelled by forcing the pumps ON for a minimum time at every cycle (backlash time) providing improved linearity.
SM="000" SM="001" SM="010" SM="011" SM="100" REFERENCE INPUT TO MAIN PHASE DETECTOR
DIVIDE BY R
/2
/2
/2
/2
SA="100" SA="011" SA="010" SA="001" SA="000"
TO AUXILIARY PHASE DETECTOR
SR01415
Figure 4. Reference Divider
1999 Nov 04
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Philips Semiconductors
Product specification
1.3GHz low voltage fractional-N dual synthesizer
SA7026
VCC
"1" D fREF REF DIVIDER R CLK R Q
P
P-TYPE CHARGE PUMP
"1" AUX/MAIN DIVIDER X D CLK Q N R
IPH
N-TYPE CHARGE PUMP
GND
fREF
R
X
P
N
IPH
SR01451
Figure 5. Phase Detector Structure with Timing
1999 Nov 04
8
Philips Semiconductors
Product specification
1.3GHz low voltage fractional-N dual synthesizer
SA7026
Main Output Charge Pumps and Fractional Compensation Currents (see Figure 6)
The main charge pumps on pins PHP and PHI are driven by the main phase detector and the charge pump current values are determined by the current at pin RSET in conjunction with bits CP0, CP1 in the C-word (see table of charge pump ratios). The fractional compensation is derived from the current at RSET, the contents of the fractional accumulator FRD and by the program value of the FDAC. The timing for the fractional compensation is derived from the main divider. The main charge pumps will enter speed up mode after the A-word is set and strobe goes High. When strobe goes Low, charge pump will exit speed up mode.
The compensation is done by sourcing a small current, ICOMP, see Figure 7, that is proportional to the fractional error phase. For proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the fractional charge pump ripple. The width of the fractional compensation pulse is fixed to 128 VCO cycles, the amplitude is proportional to the fractional accumulator value and is adjusted by FDAC values (bits FC7-0 in the B-word). The fractional compensation current is derived from the main charge pump in that it follows all the current scaling through external resistor setting, RSET, programming or speed-up operation. For a given charge pump, ICOMP = ( IPUMP / 128 ) * ( FDAC / 5*128) * FRD FRD is the fractional accumulator value. The target values for FDAC are: 128 for FMOD = 1 (modulo 5) and 80 for FMOD = 0 (modulo 8).
Principle of Fractional Compensation
The fractional compensation is designed into the circuit as a means of reducing or eliminating fractional spurs that are caused by the fractional phase ripple of the main divider. If ICOMP is the compensation current and IPUMP is the pump current, then for each charge pump: IPUMP_TOTAL = IPUMP + ICOMP.
REFERENCE R MAIN M DIVIDE RATIO N N N+1 N N+1
DETECTOR OUTPUT
2
4
1
3
0
ACCUMULATOR FRACTIONAL COMPENSATION CURRENT PULSE WIDTH MODULATION OUTPUT ON PUMP PULSE LEVEL MODULATION
mA
A
SR01416
NOTE: For a proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the charge pump ripple output.
Figure 6. Waveforms for NF = 2 Modulo 5 fraction = 2/5
fRF
MAIN DIVIDER
FRACTIONAL ACCUMULATOR ICOMP IPUMP
fREF
LOOP FILTER & VCO
SR01800
Figure 7. Current Injection Concept
1999 Nov 04
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Philips Semiconductors
Product specification
1.3GHz low voltage fractional-N dual synthesizer
SA7026
Auxiliary Output Charge Pumps
The auxiliary charge pump on pin PHA are driven by the auxiliary phase detector and PHP, PHI are driven by the main phase detector. The current value is determined by the external resistor attached to pin RSET. Main and auxiliary charge pump currents CP1 0 0 1 1 CP0 0 1 0 1 IPHA 1.5xlSET 0.5xlSET 1.5xlSET 0.5xlSET IPHP 3xISET 1xlSET 3xlSET 1xlSET IPHP-SU 15xlSET 5xlSET 15xlSET 5xlSET IPHI 36xlSET 12xlSET 0 0
NOTES 1. ISET = VSET/RSET: bias current for charge pumps. 2. CP1 is used to disable the PHI pump, IPHP-SU is the total current at pin PHP during speed up condition.
Lock Detect
The output LOCK maintains a logic `1' when the auxiliary phase detector ANDed with the main phase detector indicates a lock condition. The lock condition for the main and auxiliary synthesizers is defined as a phase difference of less than "1 period of the frequency at the input REFin+, -. One counter can fulfill the lock condition when the other counter is powered down. Out of lock (logic '0') is indicated when both counters are powered down.
Power-down mode
The power-down signal can be either hardware (PON) or software (PD). The PON signal is exclusively ORed with the PD bits in B-word. If PON = 0, then the part is powered up when PD = 1. PON can be used to invert the polarity of the software bit PD. When the synthesizer is reactivated after power-down, the main and reference dividers are synchronized to avoid possibility of random phase errors on power-up.
1999 Nov 04
10
Philips Semiconductors
Product specification
1.3GHz low voltage fractional-N dual synthesizer
SA7026
Serial programming bus
The serial input is a 3-wire input (CLOCK, STROBE, DATA) to program all counter divide ratios, fractional compensation DAC, selection and enable bits. The programming data is structured into 24 bit words; each word includes 2 or 3 address bits. Figure 8 shows the timing diagram of the serial input. When the STROBE goes active HIGH, the clock is disabled and the data in the shift register remains unchanged. Depending on the address bits, the
data is latched into different working registers or temporary registers. In order to fully program the synthesizer, 3 words must be sent: C, B, and A. Table 1 shows the format and the contents of each word. The D word is normally used for testing purposes. When sending the B-word, data bits FC7-0 for the fractional compensation DAC are not loaded immediately. Instead they are stored in temporary registers. Only when the A-word is loaded, these temporary registers are loaded together with the main divider ratio.
Serial bus timing characteristics. See Figure 8.
VDD = VDDCP =+3.0V; Tamb = +25C unless otherwise specified. SYMBOL Serial programming clock; CLK tr tf Tcy Input rise time Input fall time Clock period - - 100 10 10 - 40 40 - ns ns ns PARAMETER MIN. TYP. MAX. UNIT
Enable programming; STROBE tSTART tW tSU;E Delay to rising clock edge Minimum inactive pulse width Enable set-up time to next clock edge 40 1/fCOMP 20 - - - - - - ns ns ns
Register serial input data; DATA tSU;DAT tHD;DAT Input data to clock set-up time Input data to clock hold time 20 20 - - - - ns ns
Application information
tSU;DAT Tcy tHD;DAT tr tf tSU;E
CLK
DATA
ADDRESS
MSB
LSB
STROBE tw tSTART
SR01417
Figure 8. Serial Bus Timing Diagram
1999 Nov 04
11
Philips Semiconductors
Product specification
1.3GHz low voltage fractional-N dual synthesizer
SA7026
Data format Table 1. Format of programmed data
Last In p23 p22 MSB p21 p20 Serial Programming Format ../.. ../.. p1 First In LSB p0
Table 2. A word, length 24 bits
Last In Address
0 0
MSB fmod
FM 0
LSB
First In Spare
Fractional-N
NF2 0 NF1 1 NF0 0
Main Divider ratio
N15 0 N14 0 N13 1 N12 0 N11 0 N10 0 N9 1 N8 0 N7 0 N6 0 N5 1 N4 1 N3 0 N2 0 N1 0 N0 0 0
SK1
SK2 0
Default A word select
Fixed to 00. FM 0 = modulo 8, 1 = modulo 5. NF2..0 Fractional N Increment values 000 to 111. N0..N15, Main divider values 512 to 65535 allowed for divider ratio.
Fractional Modulus select Fractional-N Increment N-Divider
Table 3. B word, length 24 bits
Address
0 1 R9 0 R8 0 R7 0
Reference Divider
R6 1 R5 0 R4 1 R3 0 R2 0 R1 0 R0 1
Lock
L1 0 L0 0 Main 1
PD
Aux 1 FC7 0 1
Fractional Compensation DAC
FC6 FC5 0 FC4 1 FC3 0 FC2 0 FC1 0 FC0 0
Default B word select R-Divider
Fixed to 01 R0..R9, Reference divider values 4 to 1023 allowed for divider ration. L1 L0 0 0 Combined main, aux. lock detect signal present at the LOCK pin (push/pull). 0 1 Combined main, aux, lock detect signal present at the LOCK pin (open drain). 1 0 Main lock detect signal present at the LOCK pin (push/pull). 1 1 Auxiliary loop lock detect signal present at the LOCK pin (push/pull). When auxiliary loop and main loop are in power down mode, the lock indicator is low. Main = 1: power to N-divider, reference divider, main charge pumps, Main = 0 to power down. Aux = 1: power to Aux divider, reference divider, aux charge pump, Aux = 0 to power down. FC7..0 Fractional Compensation charge pump current DAC, values 0 to 255.
Lock detect output
Power down Fractional Compensation
Table 4. C word, length 24 bits
Address
1 0 A13 0 A12 0 A11 0 A10 0 A9 0
Auxiliary Divider
A8 1 A7 1 A6 1 A5 0 A4 0 A3 1 A2 0 A1 1 A0 0 1
CP
CP1 CP0 1 SM2 0
SM
SM1 0 SM0 0 SA2 0
SA
SA1 0 SA0 0
Default C word select A-Divider
Fixed to 10 A0..A13, Auxiliary divider values 128 to 16383 allowed for divider ratio. CP1, CP0: Charge pump current ratio, see table of charge pump currents. SM comparison divider select for main phase detector. SA Comparison divider select for auxiliary phase detector.
Charge pump current Ratio Main comparison select Aux comparison select
Table 5. D word, length 24 bits
Address
1 1 0 - 0
Synthesizer Test Bits
- 0 - 0 - 0 - 0 Tspu 0 - 0 - 0 - 0 - 0 - 0 - 0
Synthesizer Test Bits
- 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0
Default
Tspu: Speed up = 1
Forces the main charge pumps in speed-up mode all the time. NOTE: All test bits must be set to 0 for normal operation.
1999 Nov 04
12
Philips Semiconductors
Product specification
1.3GHz low voltage fractional-N dual synthesizer
SA7026
TYPICAL PERFORMANCE CHARACTERISTICS
3000 2000 ISET = 165.33 mA 1000 ICP (uA) 0 Icp (uA) ISET = 103.33 mA ISET = 51.67 mA ISET = 51.67 mA ISET = 103.33 mA ISET = 165.33 mA ISET = 206.67 mA 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 COMPLIANCE VOLTAGE (V) ISET = 206.67 mA 2500 2000 1500 1000 500 0 -500 -1000 -1500 -2000 -2500 0 0.25 0.5 0.75 COMPLIANCE VOLTAGE (V) 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 +85_C +25_C -40_C
-1000 -2000 -3000
SR01855
SR01856
Figure 9. PHI Charge Pump vs. ISET (CP = 01; Temp = 25_C)
Figure 10. PHI Charge Pump Output vs. Temperature (CP = 01; VDD = 3.0 V; ISET = 165.33 mA)
8000 6000 4000 2000 Icp (uA) 0 -2000 -4000 -6000 -8000 0 0.25 0.5 0.75 1 ISET = 51.67 mA ISET = 103.33 mA ISET = 165.33 mA ISET = 206.67 mA
ISET = 206.67 mA ISET = 165.33 mA ISET = 103.33 mA ISET = 51.67 mA Icp (uA)
8000 6000 4000 2000 0 -2000 -4000 -6000 -8000 +85_C +25_C -40_C
1.25 1.5 1.75
2
2.25 2.5 2.75
3
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 COMPLIANCE VOLTAGE (V)
COMPLIANCE VOLTAGE (V)
SR01857
SR01858
Figure 11. PHI Charge Pump vs. ISET (CP = 00; TEMP = 25_C)
Figure 12. PHI Charge Pump Output vs. Temperature (CP = 00; VDD = 3.0 V; ISET = 165.33 mA)
800 600 400 Icp (uA) 200 0 -200 -400 -600 -800 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 COMPLIANCE VOLTAGE (V) ISET = 51.67 mA ISET = 103.33 mA ISET = 165.33 mA ISET = 206.67 mA ISET = 206.67 mA ISET = 165.33 mA ISET = 103.33 mA Icp (uA) ISET = 51.67 mA
600 400 200 0 -200 -400 -600 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 COMPLIANCE VOLTAGE (V) +85_C +25_C -40_C
SR01859
SR01860
Figure 13. PHP Charge Pump Output vs. ISET (CP = 10; Temp = 25_C)
Figure 14. PHP Charge Pump Output vs. Temperature (CP = 10; VDD = 3.0 V; ISET = 165.33 mA)
1999 Nov 04
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Philips Semiconductors
Product specification
1.3GHz low voltage fractional-N dual synthesizer
SA7026
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
250 200 150 100 Icp (uA) 50 0 -50 -100 -150 -200 -250 0
ISET = 51.67 mA ISET = 103.33 mA ISET = 165.33 mA ISET = 206.67 mA ISET = 206.67 mA ISET = 165.33 mA ISET = 103.33 mA ISET = 51.67 mA
200 150 100 50 Icp (uA) 0 -50 -100 -150 -200 +85_C +25_C -40_C
0.25 0.5 0.75
1
1.25 1.5 1.75
2
2.25 2.5 2.75
3
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 COMPLIANCE VOLTAGE (V)
COMPLIANCE VOLTAGE (V)
SR01861
SR01862
Figure 15. PHP Charge Pump Output vs. ISET (CP = 11; Temp = 25_C)
Figure 16. PHP Charge Pump Output vs. Temperature (CP = 11; VDD = 3.0 V; ISET = 165.33 mA)
1500 1000 500 Icp (uA) 0 -500 -1000
ISET = 206.67 mA ISET = 206.67 mA ISET = 165.33 mA
1000 800 600 400 Icp (uA) 200 0 -200 -400 -600 -800 -1000 0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2 2.25 2.5 2.75 3 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 COMPLIANCE VOLTAGE (V) COMPLIANCE VOLTAGE (V)
ISET = 103.33 mA ISET = 51.67 mA ISET = 51.67 mA ISET = 103.33 mA ISET = 165.33 mA
+85_C +25_C -40_C
-1500
SR01863
SR01864
Figure 17. PHP-SU Charge Pump Output vs. ISET (CP = 01; Temp = 25_C)
Figure 18. PHP-SU Charge Pump Output vs. Temperature (CP = 01; VDD = 3.0 V; ISET = 165.33 mA)
3500 2500 1500 500 0 -500
ISET = 51.67 mA
ISET = 206.67 mA ISET = 165.33 mA ISET = 103.33 mA
3000 2000 1000 Icp (uA) 0 -1000 -2000 -3000 +85_C +25_C -40_C
ISET = 51.67 mA
Icp (uA)
-1500 -2500 -3500 0 0.25 0.5
ISET = 103.33 mA ISET = 165.33 mA ISET = 206.67 mA
0.75
1
1.25
1.5
1.75
2
2.25 2.5
2.75
3
0
0.25 0.5 0.75
1
1.25 1.5 1.75
2
2.25 2.5 2.75
3
3.25 3.5
COMPLIANCE VOLTAGE (V)
COMPLIANCE VOLTAGE (V)
SR01870
SR01865
Figure 19. PHP-SU Charge Pump Output vs. ISET (CP = 00; Temp = 25_C)
Figure 20. PHP-SU Charge Pump Output vs. Temperature (CP = 00; VDD = 3.0 V; ISET = 165.33 mA)
1999 Nov 04
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Philips Semiconductors
Product specification
1.3GHz low voltage fractional-N dual synthesizer
SA7026
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
150 100 50 Icp (uA) 0 -50 -100
ISET = 206.67 mA ISET = 206.67 mA ISET = 165.33 mA ISET = 51.67 mA ISET = 51.67 mA ISET = 103.33 mA ISET = 165.33 mA
100 80 60 40 Icp (uA) 20 0 -20 -40 -60 -80 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 -100 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 COMPLIANCE VOLTAGE (V) +85_C +25_C -40_C
ISET = 103.33 mA
-150 0 0.25 0.5 0.75
COMPLIANCE VOLTAGE (V)
SR01866
SR01867
Figure 21. PHA Charge Pump Output vs. ISET (CP = 11; Temp = 25_C)
Figure 22. PHA Charge Pump Output vs. Temperature (CP = 11; VDD = 3.0 V; ISET = 165.33 mA)
400 300 200 100 Icp (uA) 0 -100 -200 -300 -400 0
ISET = 51.67 mA ISET = 103.33 mA ISET = 165.33 mA ISET = 206.67 mA ISET = 206.67 mA ISET = 165.33 mA ISET = 103.33 mA
300 200 100 Icp (uA) 0 -100 -200 -300 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 +85_C +25_C -40_C
ISET = 51.67 mA
0.25 0.5 0.75
COMPLIANCE VOLTAGE (V)
COMPLIANCE VOLTAGE (V)
SR01869
SR01868
Figure 23. PHA Charge Pump Output vs. ISET (CP = 10; Temp = 25_C)
Figure 24. PHA Charge Pump Output vs. Temperature (CP = 10; VDD = 3.0 V; ISET = 165.33 mA)
0
MINIMUM SIGNAL INPUT LEVEL (dBm)
-5 -10 -15 -20 -25 -30 -35 -40 -45 -50 0 200 400
MINIMUM SIGNAL INPUT LEVEL (dBm)
0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -40_C +25_C +85_C
VDD = 5.00 V VDD = 3.75 V VDD = 3.00 V VDD = 2.70 V
600
800
1000
1200
1400
1600
1800
0
200
400
600
800
1000 1200 1400 1600 1800 2000
FREQUENCY (MHz)
FREQUENCY (MHz)
SR01924
SR01925
Figure 25. Main Divider Input Sensitivity vs. Frequency and Supply Voltage (Temp = 25_C)
Figure 26. Main Divider Input Sensitivity vs. Frequency and Temperature (VDD = 3.00 V)
1999 Nov 04
15
Philips Semiconductors
Product specification
1.3GHz low voltage fractional-N dual synthesizer
SA7026
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
MINIMUM SIGNAL POWER LEVEL (dBm) MINIMUM SIGNAL POWER LEVEL (dBm) 0 -5 -10 -15 -20 -25 -30 -35 0 40 80 120 160 200 240 280 320 360 400 440 480 520 560 600 FREQUENCY (MHz) VDD = 5.00 V VDD = 3.75 V VDD = 3.00 V VDD = 2.70 V 0 -5 -10 -15 -20 -25 -30 -35 -40 0 40 80 120 160 200 240 280 320 360 400 440 480 520 560 600 640 FREQUENCY (MHz) +85_C +25_C -40_C
SR01926
SR01927
Figure 27. Auxiliary Divider Input Sensitivity vs. Frequency and Supply Voltage (Temp = 25_C)
Figure 28. Auxiliary Divider Input Sensitivity vs. Frequency and Temperature (VDD = 3.00 V)
MINIMUM SIGNAL POWER LEVEL (dBm)
MINIMUM SIGNAL POWER LEVEL (dBm)
0.00 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 VDD = 5.00 V VDD = 3.75 V VDD = 3.00 V VDD = 2.70 V
0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 Temp = -40_C Temp = +85_C Temp = +25_C
FREQUENCY (MHz)
FREQUENCY (MHz)
SR01890
SR01891
Figure 29. Reference Divider Input Sensitivity vs. Frequency and Supply Voltage (Temp = 25_C)
Figure 30. Reference Divider Input Sensitivity vs. Frequency and Temperature (VDD = 3.00 V)
10.5 10 9.5 I TOTAL (mA) 9 8.5 8 7.5 7 6.5 2 2.5 3 3.5 4 4.5 5 5.5 6 +85_C +25_C -40_C
SUPPLY VOLTAGE (V)
SR01928
Figure 31. Current Supply Over VDD
1999 Nov 04
16
Philips Semiconductors
Product specification
1.3GHz low voltage dual fractional-N frequency synthesizer
SA7026
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
1999 Nov 04
17
Philips Semiconductors
Product specification
1.3GHz low voltage dual fractional-N frequency synthesizer
SA7026
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Date of release: 11-99 Document order number: 9397 750 06566
Philips Semiconductors
1999 Nov 04 18

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