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74LVT162244 * 74LVTH162244 Low Voltage 16-Bit Buffer/Line Driver with 3-STATE Outputs and 25 Series Resistors in the Outputs
March 1999 Revised June 2002
74LVT162244 * 74LVTH162244 Low Voltage 16-Bit Buffer/Line Driver with 3-STATE Outputs and 25 Series Resistors in the Outputs
General Description
The LVT162244 and LVTH162244 contain sixteen noninverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is nibble controlled. Individual 3-STATE control inputs can be shorted together for 8-bit or 16-bit operation. The LVT162244 and LVTH162244 are designed with equivalent 25 series resistance in both the HIGH and LOW states of the output. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters. The LVTH162244 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These buffers and line drivers are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT162244 and LVTH162244 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation.
Features
s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pullup resistors to hold unused inputs (74LVTH162244), also available without bushold feature (74LVT162244). s Live insertion/extraction permitted s Power Up/Power Down high impedance provides glitchfree bus loading s Outputs include equivalent series resistance of 25 to make external termination resistors unnecessary and reduce overshoot and undershoot s Functionally compatible with the 74 series 162244 s Latch-up performance exceeds 500 mA s ESD performance: Human-body model > 2000V Machine model > 200V Charged-device > 1000V s Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Ordering Code:
Order Number 74LVT162244G (Note 1)(Note 2) 74LVT162244MEA (Note 2) 74LVT162244MTD (Note 2) 74LVTH162244G (Note 1)(Note 2) 74LVTH162244MEA 74LVTH162244MEX 74LVTH162244MTD 74LVTH162244MTX Package Number BGA54A MS48A MTD48 BGA54A MS48A MS48A MTD48 MTD48 Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [Tube] 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [Tape and Reel] 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [Tube] 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [Tape and Reel]
Note 1: Ordering code "G" indicates Trays. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
(c) 2002 Fairchild Semiconductor Corporation
DS012445
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74LVT162244 * 74LVTH162244
Logic Symbol
Pin Descriptions
Pin Names OEn I0-I15 O0-O15 NC Description Output Enable Inputs (Active LOW) Inputs Outputs No Connect
Connection Diagrams
Pin Assignment for SSOP and TSSOP
FBGA Pin Assignments
1 A B C D E F G H J O0 O2 O4 O6 O8 O10 O12 O14 O15 2 NC O1 O3 O5 O7 O9 O11 O13 NC 3 OE1 NC VCC GND GND GND VCC NC OE4 4 OE2 NC VCC GND GND GND VCC NC OE3 5 NC I1 I3 I5 I7 I9 I11 I13 NC 6 I0 I2 I4 I6 I8 I10 I12 I14 I15
Truth Table
Inputs OE1 L L H OE2 L L H OE3 L Pin Assignment for FBGA L H OE4 L L H
H = HIGH Voltage Level Z = High Impedance
Outputs I0-I3 L H X I4-I7 L H X I8-I11 L H X I12-I15 L H X
L = LOW Voltage Level X = Immaterial
O0-O3 L H Z O4-O7 L H Z O8-O11 L H Z O12-O15 L H Z
(Top Thru View)
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74LVT162244 * 74LVTH162244
Functional Description
The LVT162244 and LVTH162244 contain sixteen non-inverting buffers with 3-STATE outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation.
Logic Diagram
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74LVT162244 * 74LVTH162244
Absolute Maximum Ratings(Note 3)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in 3-STATE Output in HIGH or LOW State (Note 4) VI < GND VO < GND VO > VCC VO > VCC Output at HIGH State Output at LOW State V mA mA mA mA mA
-0.5 to +4.6 -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -50 -50
64 128
64 128 -65 to +150
C
Recommended Operating Conditions
Symbol VCC VI IOH IOL TA Supply Voltage Input Voltage HIGH-Level Output Current LOW-Level Output Current Free Air Operating Temperature Input Edge Rate, VIN = 0.8V-2.0V, VCC = 3.0V Parameter Min 2.7 0 Max 3.6 5.5 Units V V mA mA
-12
12
-40
0
+85
10
C
ns/V
t/V
Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 4: IO Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Symbol VIK VIH VIL VOH VOL II(HOLD) (Note 5) II(OD) (Note 5) II Bushold Input Over-Drive Current to Change State Input Current Control Pins Data Pins IOFF IPU/PD IOZL IOZH IOZH+ ICCH ICCL ICCZ Power Off Leakage Current Power Up/Down 3-STATE Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current Power Supply Current Power Supply Current Power Supply Current Parameter Input Clamp Diode Voltage Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Bushold Input Minimum Drive VCC (V) 2.7 2.7-3.6 2.7-3.6 2.7-3.6 3.0 2.7 3.0 3.0 3.0 3.6 3.6 3.6 0 0-1.5V 3.6 3.6 3.6 3.6 3.6 3.6 75 -75 500 -500 10 1 -5 1 100 100 -5 5 10 0.19 5 0.19 A A A A A mA mA mA A VCC-0.2 2.0 0.2 0.8 2.0 0.8 TA = -40C to +85C Min Max -1.2 Units V V V V V A A Conditions II = -18 mA VO 0.1V or VO VCC - 0.1V IOH = -100 A IOH = -12 mA IOL = 100 A IOL = 12 mA VI = 0.8V VI = 2.0V (Note 6) (Note 7) VI = 5.5V VI = 0V or VCC VI = 0V VI = VCC 0V VI or VO 5.5V VO = 0.5V to 3.0V VI = GND or VCC VO = 0.5V VO = 3.0V VCC < VO 5.5V Outputs HIGH Outputs LOW Outputs Disabled
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74LVT162244 * 74LVTH162244
DC Electrical Characteristics
Symbol ICCZ+ ICC Parameter Power Supply Current Increase in Power Supply Current (Note 8)
Note 5: Applies to bushold versions only (74LVTH162244).
(Continued)
VCC (V) 3.6 3.6 TA = -40C to +85C Min Max 0.19 0.2 mA mA VCC VO 5.5V, Outputs Disabled One Input at VCC - 0.6V Other Inputs at VCC or GND
Units
Conditions
Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Dynamic Switching Characteristics
Symbol VOLP VOLV Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL VCC (V) 3.3 3.3
(Note 9)
TA = 25C Conditions Max Units V V CL = 50 pF, RL = 500 (Note 10) (Note 10)
Min
Typ 0.8 -0.8
Note 9: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 10: Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
TA = -40C to +85C, CL = 50 pF, RL = 500 Symbol Parameter VCC = 3.3V 0.3V Min tPLH tPHL tPZH tPZL tPHZ tPLZ tOSHL tOSLH Output to Output Skew (Note 11) Output Disable Time Output Enable Time Propagation Delay Data to Output 1.4 1.2 1.2 1.4 2.0 1.5 Max 4.0 3.7 5.1 5.4 5.0 5.0 1.0 Min 1.4 1.2 1.2 1.4 2.0 1.5 VCC = 2.7V Max 4.8 4.1 6.5 6.9 5.4 5.4 1.0 Units
ns ns ns ns
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance
Symbol CIN COUT
(Note 12)
Parameter Conditions VCC = 0V, VI = 0V or VCC VCC = 3.0V, VO = 0V or VCC Typical 4 8 Units pF pF
Input Capacitance Output Capacitance
Note 12: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
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74LVT162244 * 74LVTH162244
Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A
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74LVT162244 * 74LVTH162244
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A
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74LVT162244 * 74LVTH162244 Low Voltage 16-Bit Buffer/Line Driver with 3-STATE Outputs and 25 Series Resistors in the Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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