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RELEASED REFERENCE DESIGN PMC-2000185 ISSUE 2
PM5315 SPECTRA-2488
SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
PM5315
SPECTRA-2488
SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
REFERENCE DESIGN
RELEASED ISSUE 2: MARCH 2001
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RELEASED REFERENCE DESIGN PMC-2000185 ISSUE 2
PM5315 SPECTRA-2488
SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
REVISION HISTORY Issue No. 1 2 Issue Date June 2000 March 2001 Details of Change Document created. Document revised to reflect changes made to schematic for revision of reference design. The following changes were made to the schematic: * LEDs 4, 5, and 6 on page 17 no longer connect to the CPLD (U7). These LEDS now connect to test points.
The circuitry associated with pins 23 and 24 of the Triquint TQ8106s devices has been modified to include a 1N4148 diode, 1.5K resistor, and a 2.0 K resistor. These components are necessary to prevent the CDR PLL in TQ8106 from locking up. * * * * Updated configuration register description Added manufactures to BOM Updated figures 1,2, and 7 Updated CPLD Block Diagram
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SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
CONTENTS 1 2 3 4 5 6 7 DEFINITIONS .......................................................................................... 1 FEATURES .............................................................................................. 2 APPLICATIONS ....................................................................................... 3 REFERENCES......................................................................................... 4 APPLICATION EXAMPLES ..................................................................... 5 BLOCK DIAGRAM ................................................................................... 7 FUNCTIONAL DESCRIPTION................................................................. 8 7.1 7.2 7.3 7.4 7.5 PM5315 SPECTRA-2488.............................................................. 8 PM5310 TBS ................................................................................. 9 SERIAL LVDS TELECOMBUS INTERFACE............................... 10 QUAD 622 MBPS LINE INTERFACE.......................................... 10 CPLD........................................................................................... 13 7.5.1 CPCI INTERFACE ............................................................ 14 7.5.2 CONFIGURATION AND STATUS REGISTERS............... 14 7.6 7.7 CLOCKS...................................................................................... 17 COMPACTPCI INTERFACE........................................................ 18 7.7.1 INTERFACE AND BRIDGE HARDWARE......................... 18 7.7.2 HOT SWAP FEATURES................................................... 19 7.8 7.9 8 POWER....................................................................................... 21 MECHANICAL FORM FACTOR .................................................. 22
TABLE IMPLEMENTATION DESCRIPTION .......................................... 24 8.1 ROOT DRAWING........................................................................ 24
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PM5315 SPECTRA-2488
SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 9 10 11
OPTICS BLOCK.......................................................................... 24 SERDES BLOCK ........................................................................ 24 SPECTRA 2488 BLOCK ............................................................. 25 TBS BLOCK ................................................................................ 26 SYSTEM INTERFACE BLOCK ................................................... 27 CPLD BLOCK.............................................................................. 27 CPCI BLOCK............................................................................... 27 POWER BLOCK ......................................................................... 28
SCHEMATICS........................................................................................ 30 BILL OF MATERIALS............................................................................. 31 LAYOUT ................................................................................................. 36
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SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
LIST OF FIGURES FIGURE 1 - ADD/DROP MUX WITH SPECTRA-2488...................................... 5 FIGURE 2 - MULTISERVICE STS 12 X 4 ADM WITH TSE .............................. 6 FIGURE 3 - SPECTRA-2488 WITH TBS QUAD OC-12 BLOCK DIAGRAM..... 7 FIGURE 4 - 622 MBS LINE INTERFACE ........................................................ 10 FIGURE 5 - TQ8106 TO SPECTRA-2488 RX INPUT TIMING DIAGRAM .......11 FIGURE 6 - SPECTRA-2488 TO TQ8106 TX INPUT TIMING DIAGRAM....... 12 FIGURE 7 - CPLD FUNCTIONAL BLOCK DIAGRAM..................................... 13 FIGURE 8 - CPCI BLOCK DIAGRAM. ............................................................ 18 FIGURE 9 - CPCI HOT SWAP CIRCUIT......................................................... 19
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PM5315 SPECTRA-2488
SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
LIST OF TABLES TABLE 1: TQ8106 TO SPECTRA-2488 RX INPUT TIMING..............................11 TABLE 2: SPECTRA-2488 RX INPUT TIMING SPECS. ...................................11 TABLE 3: SPECTRA-2488 TO TQ8106 TX INPUT TIMING ............................. 12 TABLE 4: TQ8106 TX INPUT TIMING SPECS................................................. 12 TABLE 5: ADDRESS BIT ALLOCATION........................................................... 14 TABLE 6: TQ8106 LOOP-BACK MODES......................................................... 15 TABLE 7: SYSTEM CLOCK TRUTH TABLE .................................................... 15 TABLE 8: CARD MAXIMUM ESTIMATED POWER CONSUMPTION ............. 21 TABLE 9: WORKING AND PROTECT HS3 CONNECTOR PINOUT (J6) ........ 22 TABLE 10: AUXILIARY HS3 CONNECTOR PINOUT (J5)................................ 22 TABLE 11 : MAJOR COMPONENTS LIST ....................................................... 31
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SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
LIST OF REGISTERS CPLD CONFIGURATION REGISTER 0X00..................................................... 14 CPLD CONFIGURATION REGISTER 0X01..................................................... 16
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SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
1
DEFINITIONS ADM SERDES CHESS CPLD LVDS RWSEL xCMP Add Drop Multiplexer Serializer/Deserializer Channelizer Engine for SONET/SDH Complex Programmable Logic Device Low Voltage Differential Signals Read Working Link Select Grouped Connection Memory Page signals
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PM5315 SPECTRA-2488
SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
2
FEATURES * * Provides four OC-12 rate 622.08 Mbits/s SONET/SDH physical layer channels. On the system side, provides four working 777.76 Mbps LVDS serial telecombus (STCB) links, four protect 777.76 Mbps LVDS STCB links, and four auxiliary 777.76 Mbps LVDS STCB links. System side interface connects through TBS Serializer device to SONET/SDH cross connect devices (eg. TSE). External system timing sources for multiple line-card applications, or local timing generation for stand-alone evaluation. Transmit line side timing can use either on board 77.76 MHz clock as reference or recovered clock as reference (Loop-Timing) System and line side loopback modes for diagnostics. CompactPCI interface allows the user to control and monitor the SPECTRA2488 and on board CPLD.
* * * * *
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PM5315 SPECTRA-2488
SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
3
APPLICATIONS * * * SONET/SDH Multiservice ADMs SONET/SDH Cross Connects SONET/SDH Terminal Multiplexers
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PM5315 SPECTRA-2488
SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
4
REFERENCES * * * * * * * * * * * Bell Communications Research - GR-253-CORE "SONET Transport Systems: Common Generic Criteria", Issue 2 Revision 2, January 1999. Bell Communications Research - GR-436-CORE "Digital Network Synchronization Plan", Issue 1 Revision 1, June 1996. IEEE - P1596.3 "Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI)", November 1995 PLX Technology PCI9054 PCI Bridge Device, Data Sheet, Issue 1, January, 1999. PMC-1990821, PM5315 SPECTRA-2488 SONET/SDH Payload Extractor/Aligner Data Sheet, Issue 2, June, 2000. PMC-1991257, PM5310 Telecombus Serializer Data Sheet, Issue 4, September, 2000. PCI Industrial Computers Manufacturers Group (PICMG), "CompactPCI Specification 2.0 R 2.1", Wakefield MA, September 1997. TriQuint Seminconductor, Inc., TQ8106 SONET/SDH Transceiver Data Sheet, Revision 0.3.A, July 1998. PMC-2000299, "777.6 MHz LVDS Serial Telecombus Design Considerations", Issue 1, March 2000 PMC-1991797, CHESS Users Guide, Issue 2, May 2000. PMC-2000021,CHESS Reference Design Hardware Manual, Issue 1, Dec 2000
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PM5315 SPECTRA-2488
SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
5
APPLICATION EXAMPLES The following example () demonstrates an implementation of a small NorthSouth (STS-12 x 4) Add/Drop Multiplexer, using the SPECTRA-2488 With TBS Quad OC-12 Line Card and the S/UNI MACH48 Card (PMC-2000207). Aside from the serializing and backplane driving functions, the TBS can provide STS-1 switching and with use of its auxiliary port, drop/ add traffic to the S/UNIMACH48 where ATM/POS processing can be done.
Figure 1
- Add/Drop MUX With SPECTRA-2488, TBS and S/UNI MACH48.
SPECTRA-2488 With TBS Quad OC-12 Line Card Telecombus LVDS x4 S/UNI MACH48 Card
OC-12 x 4
PM5315 SPECTRA-2488
PM5310 TBS
PM7390 S/UNI MACH48
LVDS x4 LVDS x4
LVDS x4
Telecombus OC-12 x 4 PM5315 SPECTRA-2488 PM5310 TBS LVDS x4 PM7390 S/UNI MACH48
SPECTRA-2488 With TBS Quad OC-12 Line Card
S/UNI MACH48 Card
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RELEASED REFERENCE DESIGN PMC-2000185 ISSUE 2
PM5315 SPECTRA-2488
SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
Figure 3 below shows an example of a multiservice Add/Drop Multiplexer (ADM). The SPECTRA-2488 With TBS Quad OC-12 Line Cards provide line-side interface to the SONET OC-12 x 4 traffic. The TSE Fabric Cards (PMC1991247) route the different traffic types the SONET line may contain such as POS, voice, or video, to the appropriate service cards. In this way, the TSE decouples line-side PHY devices of SONET rings from multi-service system cards. Figure 3 - Multiservice STS 12 x 4 ADM With TSE
SPECTRA-2488 With TBS Quad OC-12 Line Card Telecombus OC-12 x4 PM5315 SPECTRA-2488 PM5310 TBS LVDS x4 TSE Fabric Card LVDS x4 S/UNI MACH48 Card
PM7390 S/UNI MACH48
LVDS x4
LVDS x4
LVDS x4 LVDS x4
LVDS x4 Telecombus OC-12 x4 PM5315 SPECTRA-2488 PM5310 TBS LVDS x4 TSE Fabric Card
SPECTRA-2488 With TBS Quad OC-12 Line Card
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PM5315 SPECTRA-2488
SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
6
BLOCK DIAGRAM Figure 4 - SPECTRA-2488 With TBS Quad OC-12 Block Diagram
PM5315 SPECTRA-2488 DD DJ0J1 DPL DDP DALARM
SD1 TQ8106 DXD[7:0] 8
Drop Side Telecom Bus 32 4 4 4 4
System Telecom Bus ID IJ0J1 IPL IDP IPAIS 8 8
RD1[7:0]
TWRK+/TPROT+/TJ0FP
OC-12 Optics
MXD[7:0]
8 CLK_OUT FB_IN
TD1[7:0] TDCLK1 TCLK1
60pin HS3 Connector (Working and Protect)
TXBC REFCKE
CLK_IN PLL
AD AJ0J1 APL ADP APAIS
SD2 TQ8106 DXD[7:0] 8 RD2[7:0]
Add Side Telecom Bus 32 4 4 4 4 4
RWRK+/OD OJ0J1 OPL ODP OPAIS PM5310 TBS RPROT+/-
8 8
OC-12 Optics
MXD[7:0]
8 CLK_OUT FB_IN
TD2[7:0] TDCLK2 TCLK2 A<13:0> D<15:0> RDB WRB RESETB CSB INTB CSB1 INTB1 RDB WRB RESETB DCK ACK DCMP ACMP DJ0REF DCK ACK DCMP ACMP DJ0REF CSB2 INTB2 SYSCLK OCMP RJ0FP RWSEL XCMP FP RWSEL SYSCK1 SYSCK2 SD4 A<11:0> D<15:0> RDB WRB RESETB CSB INTB SYSCLK OCMP RJ0FP RWSEL TAUX+/RAUX+/8
TXBC REFCKE
CLK_IN PLL
8
60pin HS3 Connector (Auxillary)
SD3 TQ8106 DXD[7:0] 8 RD3[7:0]
OC-12 Optics
MXD[7:0]
8 CLK_OUT FB_IN
TD3[7:0] TDCLK3 TCLK3
TXBC REFCKE
CLK_IN PLL
TQ8106 DXD[7:0]
8
CPLD RD4[7:0] D<7:0> LA<17:14> TD4[7:0]
PLX 9054 PCI Bridge LD<15:0> LA<19:2> AD<31:0> C/BE<3:0> PCI BUS CONTROL
OC-12 Optics
MXD[7:0]
8 CLK_OUT FB_IN
TDCLK4 TCLK4
CONTROL LHOLD LHOLDA L_ADSB L_READYB L_WRB L_RSTOB L_INTB L_CLK 1.8V 3.3V 5V
CONTROL LHOLD LHOLDA L_ADSB L_READYB L_WRB L_RSTOB L_INTB L_CLK 3.3V 5V
TXBC REFCKE Ext. Ref 77.76 MHz Ref. Osc.
CLK_IN PLL
CPCI J1
RESET\
Power
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PM5315 SPECTRA-2488
SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
7
FUNCTIONAL DESCRIPTION The QUAD OC-12 Reference Design receives 622Mbps serial data via the Siemens V23826-H18-C363 622 Mbps single mode fiber optic transceivers. Each incoming STS-12 data signal is fed into a TQ8106 Serdes, which recovers clock and data and outputs the data in parallel (8 bit byte serial) format at 77.76MHz to the SPECTRA-2488. The SPECTRA-2488 terminates the transport and path overhead of each of the incoming STS-12 streams. The STS-12 frames are transmitted to the system side via four 8 bit byte serial Telecombus interfaces operating at 77.76MHz. The byte serial Telecombus interface connects seamlessly to the TBS device which takes the four input 77.76MHz byte serial data streams and serializes them for output onto the system backplane. The system side data stream is 8B/10B encoded LVDS at 777.6MHz. Frames received at the system side are processed similarly (but in reverse) and are output on the line side OC-12 channels at 622Mbps.
7.1
PM5315 SPECTRA-2488 The PM5315 SONET/SDH PAYLOAD EXTRACTOR ALIGNER (SPECTRA2488) is capable of terminating the transport and path overhead of a single STS48 (STM-16/AU4-4c/AU4/AU3/TU3), a single STS-48c (STM-16/AU4-16c), a quad STS-12 (STM-4/ AU4/AU3/TU3) or a quad STS-12c (STM-4-4c) data stream at 2488 Mbit/sec. The SPECTRA-2488 implements significant functions for a SONET/SDH compliant line interface. For this reference design, the SPECTRA-2488 is operating in quad STS12/STM-4 mode. The device transmits four independent OC-12 SONET/SDH frames via four 8 bit serial interfaces at 77.76MHz. The SPECTRA-2488 formats the SONET section, line and path or the SDH regenerator section, multiplexer section, and high order path overhead. It performs framing pattern insertion (A1, A2), scrambling, section and line alarm insertion, and section and line BIPs (B1, B2) calculation as required to allow performance monitoring at the far end. Line remote error indicators (M1) are optionally inserted. A 16 or 64 byte section trace (J0) message may be inserted. In addition, the SPECTRA-2488 generates the transmit payload pointers (H1, H2), creates and inserts the path BIPs (B3), optionally inserts a 16 or 64 byte path trace message (J1), and optionally inserts the path status byte (G1). As well as basic processing of the transmit SONET/SDH overhead, the SPECTRA-2488 provides convenient access to all overhead bytes, which are inserted serially on lower rate interfaces, allowing
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SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
additional external sourcing of overhead, if desired. The SPE is inserted from the 32 bit Telecom ADD bus operating at 77.76MHz. The SPECTRA-2488 receives SONET/SDH frames via four 8 bit serial interfaces at 77.76MHz. The device terminates the SONET section, line and path or the SDH regenerator section, multiplexer section and line alarm conditions, and monitors section and line BIPs (B1, B2), accumulating error counts at each level for performance monitoring. A 16 or 64 byte section trace (J0) message may be buffered and compared against an expected message. In addition, the SPECTRA-2488 interprets the received payload, monitors and accumulates path Remote Error Indications (REIs), accumulates and compares the 16 or 64 byte path trace (J1) message against an expected result and extracts the SPE. The SPE is made available on the 32 bit Telecom DROP bus operating at 77.76MHz. The SPECTRA-2488 is implemented in low power 1.8V CMOS core logic with 3.3V CMOS/TTL compatible digital I/O. It is packaged in a 520 pin SBGA. 7.2 PM5310 TBS The TBS implements conversion between byte-serial parallel Telecombus and bit serial 8B/10B encoded serial Telecombus formats. The TBS can be used to connect SONET/SDH framer devices (e.g. PM5315 SPECTRA-2488) to ATM/POS processors (PM7390 S/UNI MACH48) or to SONET/SDH crossconnects (PM5372 TSE). It can also be used to connect SONET/SDH tributary unit processors (PM5363 TUPP+622) to PDH mapper devices (PM8315 TEMUX). On the ingress side, the TBS converts an incoming parallel Telecombus stream to a set of three serial LVDS Telecombus links (3 sets of 4 links called working, protect and auxiliary). Most users will use one of the three ports as the main port for grooming to the TSE switch fabric or connecting to a layer 2 processing card. The second port may be used for connecting to a redundant fabric or layer 2 processing card. The incoming parallel streams can carry a single STS-48/STM16 stream or four STS-12/STM-4 streams that share a common clock. Incoming data is encoded into an extended set of 8B/10B characters and transferred onto three independent sets of 777.6Mbps LVDS serial links. Transport and payload frame boundaries, pointer justification events and alarm conditions are marked by 8B/10B control characters. A pseudo random bit sequence (PRBS) generator 23 18 is provided to monitor the incoming payload for the X +X +1 pattern. The PRBS processor is configurable to handle all legal mixes of STS-1/AU3, STS3c/AU4, STS-12c/AU4-4c and STS-48c/AU4-16c in the incoming Telecombus stream. A time-slot interchange block is provided to allow arbitrary mapping of streams on the incoming parallel Telecombus to each of the three sets of LVDS serial Telecombus links at STS-1/AU-3 granularity. Multi-cast is also supported.
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SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
In the egress direction, the TBS connects three independent sets of four 777.6 Mbps serial LVDS Telecombus links to an outgoing parallel Telecombus stream. Each link contains a constituent STS-12/STM-4 of an STS-48/STM-16 stream. Bytes on the links are carried as 8B/10B characters. The TBS decodes the characters into Telecombus data and control signals. A PRBS processor is provided to monitor the decoded payload for the X23+X18+1 pattern. The PRBS processor is configurable to handle all legal mixes of STS-1/AU3, STS-3c/AU4, STS-12c/AU4-4c and STS-48c/AU4-16c in the LVDS links. The TBS is implemented in low power 1.8V CMOS core logic with 3.3V CMOS/TTL compatible digital I/O. It is packaged in a 352 pin UBGA. 7.3 Serial LVDS Telecombus Interface The Telecombus interface on the SPECTRA-2488 With TBS OC-48 Reference Design Card supports four STS-12/STM-4 serial 777.6 Mbps LVDS links (8B/10B encoded). The Telecom bus signals comprise the majority of the signals on the system interface connector. The complete connector pinout is shown below in Table 9 and Table 9. 7.4 Quad 622 Mbps Line Interface Figure 5 below outlines the functionality of the Quad 622 Mbps Serial Line Interface on the SPECTRA-2488 with TBS Quad OC-12 Line Card. Figure 5 - 622 Mbs Line Interface
TQ8106 DXD[7:0]
8 RD[7:0]
RXBC
RDCLK
V23826-H18-C363 RXDP RXDN SD OC-12 8 TXDP TXDN TXDP TXDN RXDP RXDN SD PM5315 SPECTRA-2488
TD[7:0]
77.76 MHz LVPECL Reference Osc.
PI6C2502 REFCKE P/N CLK_IN 77.76 MHz PLL CLK_OUT TDCLK FB_IN TCLK
EXT. REF
TTL/ LVPECL Translator
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SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
The TQ8106 Transceiver performs serialization, deserialization and clock and data recovery for a single OC-12 channel. The device takes a single serial STS12 PECL input stream, recovers clock and data and outputs it on an 8 bit byte serial bus. In the transmit direction, the TQ8106 takes incoming byte serial data at 77.76MHz and bit serializes it for transmission over optical fiber at 622.08 MBps. Parallel data from the TQ8106 SERDES is clocked out of the device on the falling edge of the recovered clock, RXBC. The SPECTRA-2488 will use the rising edge of RXBC to clock the data in. See Figure 6 for timing diagrams and Table 1 and Table 2 for timing parameters. Figure 6 - TQ8106 to SPECTRA-2488 Rx Input Timing Diagram
RXBC A DXD[7:0] B C
Table 1: TQ8106 to SPECTRA-2488 Rx Input Timing Description A B C RXBC falling edge to DXD[7:0] valid DXD[7:0] Set-up time to RXBC rising edge DXD[7:0] Hold time to RXBC rising edge Min 500 5.43 6.93 Max 1000 5.93 7.43 Units ps ns ns
Table 2: SPECTRA-2488 Rx Input Timing Specs. Description RD1-4[7:0] Set-up time to RDCLK1-4 rising edge RD1-4[7:0] Hold time to RDCLK1-4 rising edge Min 2 0 Max Units ns ns
The outgoing parallel data from the SPECTRA-2488 is clocked out of the device on the rising edge of TCLK and clocked into the TQ8106 using the rising edge of TXBC + 270 degrees. The delay between the TDCLK input of the SPECTRA and the TCLK output of the SPETCRA is not specified and therefore the
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PM5315 SPECTRA-2488
SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
relationship between the SPECTRA TX data TD[7:0] and the TQ8106 TX input clock TXBC would unknown. The 77.76 MHz PLL ensures that TCLK and TXBC are in phase. With the TXBC now phase locked to the TXLCK the timing between the TXBC and the SPECTRA TX data can be determined. See Figure 7 for timing diagram and Table 3 and Table 4 for timing parameters. Figure 7 - SPECTRA-2488 to TQ8106 TX Input Timing Diagram
TXBC A MXD[7:0] B TXBC_270 C
Table 3: SPECTRA-2488 to TQ8106 Tx Input Timing Description A B C TXBC rising edge to MXD[7:0] valid MXD[7:0] Set-up time to TXBC rising edge MXD[7:0] Hold time to TXBC rising edge 1 2.65 4.21 Min Max 7 8.65 10.21 Units ns ns ns
Table 4: TQ8106 TX Input Timing Specs. Description MXD[7:0] Set-up time to TXBC rising edge MXD[7:0] Hold time to TXBC rising edge Min 600 600 Max Units ps ps
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PM5315 SPECTRA-2488
SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
7.5
CPLD The main function of the CPLD is to implement the glue logic and address decoding for interfacing the cPCI bus to the SPECTRA-2488 and TBS devices. Additionally, the 77.76MHz system clocks distributed via the backplane are buffered and output to the Telecombus clocks on the SPECTRA-2488 and to the SYSCLK input on the TBS. Overhead signals from the SPECTRA-2488 device have been routed to the CPLD for future design considerations. R/W registers have been included in the CPLD for TBS and SPECTRA interrupt status as well as 77.76 MHz system clock control. Figure 8 - CPLD Functional Block Diagram
L_ADSB L_WRB LHOLD LHOLDA L_READYB
RDB
Micro Interface Control
WRB L_CLK
CSB2
CSB1
LA[17:14]
Registers
LD[7:0]
Divide By N
LOCAL_OSC
M U X 2
SYSCLK1 SYSCLK2 INTB_SPECTRA INTB_TBS XCMP DCMP ACMP TCMP OCMP FP DJ0REF RJ0FP_TBS
M U X 1
SYSCLK
L_INTB
LED[5:1] Chess Control L E D S
INTB1
INTB2
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PM5315 SPECTRA-2488
SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
7.5.1 cPCI Interface The interface to the cPCI interface chip can be summarized as follows: added signaling (LHOLD, LHOLDA#, ADS#, READY#) not support by the microprocessor interface and decoding for interface signals (RDB, WRB and CSB). Timing for the signals to the SPECTRA-2488 and TBS devices are achieved using counts of SYSCLK. 7.5.1.1 Address Space Allocation of Card The LA<32:2> address space is allocated according to Table 5. Table 5: Address Bit Allocation LA<32:2> bits 14:2 15:2 12:2 13:2 17:16 32:18 Offset 0x0000 0x0000 0x4000 0x4000 0x8000 Function SPECTRA-2488 Normal Registers SPECTRA-2488 Test Registers TBS Normal Registers TBS Test Registers CPLD Configuration Register Unused bits
7.5.2 Configuration and Status Registers The CPLD provides a register for control of system clock MUX1, MUX2, and interrupt status register. ALL registers are R/W registers. CPLD Configuration Register 0x00: CONFIG_REG (LA[17:16]=10) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Type R/W R/W R/W R/W R/W Function unused LED_3 Fpenable MUX2[1] MUX2[0] Default 0 0 0 0 0
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SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
Bit 2 Bit 1 Bit 0 LBM[1:0]
R/W R/W R/W
MUX1 LBM[1] LBM[0]
0 0 0
The LBM[1:0] bits select the loop-back modes for the TQ8106 device as show below in Table 6: Table 6: TQ8106 Loop-back Modes LBM[1:0] 00 01 10 11 MUX1 The MUX1 bit controls the CPLD MUX1. This bit selects the source for the 77.76Mhz system clock. When MUX1=0 the output of MUX2 is selected. When MUX1=1 the logical XOR of SYSCLK1 and SYSCLK2 is selected. See Table 7. MUX2[1:0] The MUX2[1:0] bits control the CPLD MUX2. These bits combine with MUX1 select the source for the 77.76 MHz system clock. When MUX2[1:0]=00 or 11 the output of MUX2 is the 77.76 MHz clock from the on board oscillator. When MUX2[1:0]=01 the output of MUX2 is SYSCLK1 from backplane, and when MUX2[1:0]=10 the output of MUX2 is SYSCLK2 from the backplane. See Table 7. Table 7: System Clock Truth Table MUX1 0 0 0 0 1 MUX[1:0] 00 01 10 11 XX System clock On board oscillator SYSCLK1 SYSCLK2 On board oscillator SYSCLK1 xor SYSCLK2 System clock Loopback Normal Equipment Facility
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SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
CPLD Configuration Register 0x01: CMP_REG (LA[17:16]=11) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PGMDCMP: The PGMDCMP bit is the alternative programmable source for the DCMP signal. DCMP Selection: DCMP_SEL determines the source of the DCMP signal. When DCMP_SEL = `0', the XCMP signal is the source, otherwise, PGMDCMP is the source. PGMACMP: The PGMACMP bit is the alternative programmable source for the ACMP signal. ACMP Selection: ACMP_SEL determines the source of the ACMP signal. When ACMP_SEL = `0', the XCMP signal is the source, otherwise, PGMACMP is the source. PGMTCMP: The PGMTCMP bit is the alternative programmable source for the TCMP signal. TCMP Selection: TCMP_SEL determines the source of the TCMP signal. When TCMP_SEL = `0', the XCMP signal is the source, otherwise, PGMTCMP is the source. Type R/W R/W R/W R/W R/W R/W R/W R/W Function OCMP selection PGMOCMP TCMP selection PGMTCMP ACMP selection PGMACMP DCMP selection PGMDCMP Default 0 0 0 0 0 0 0 0
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SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
PGMTCMP: The PGMTCMP bit is the alternative programmable source for the TCMP signal. OCMP Selection: OCMP_SEL determines the source of the OCMP signal. When OCMP_SEL = `0', the XCMP signal is the source, otherwise, PGMOCMP is the source. 7.6 Clocks The 77.76 MHz system clock signal for the TBS and ACK and DCK Telecom bus clocks for the SPECTRA-2488 can be configured in two ways. The clock is supplied from an on-board 77.76 MHz HCMOS crystal oscillator or from the backplane. This clock source should have a frequency stability of 100 ppm. The 77.76 MHz reference clock for the MAXIM 3880 deserializer can be supplied by an on board LVPECL crystal oscillator or from the front panel through a SMA connector. This clock should be from a low phase noise source with a frequency stability 20 ppm.
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SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
7.7
CompactPCI Interface The microprocessor interface provides read/write access to normal and test mode registers as described within the SPECTRA-2488 and TBS Data Sheet. This design connects a CompactPCI bus to this microprocessor interface. A block diagram of the cPCI interface and bridge is shown below in Figure 9. Figure 9
LA<31..2> LD<31..0> CONTROL
- cPCI Block Diagram.
LA<31..2> LD<31..0> CONTROL AD<31:0> C/BE<3:0> CONTROL
CPCI J1
LOCAL BUS
PLX 9054 PCI BRIDGE
RESET\
PCI BUS
+12V -12V +5V +3.3V
EEPROM
7.7.1
Interface and Bridge Hardware The PCI9054 is a 3.3V/5V compliant PCI v2.2 32-bit, 33MHz Bus Master Interface Controller, that provides flexible local bus configurations and Hot Swap capability. The 32 bit multiplexed address/data bus and associated control lines connect directly from the CPCI J1 connector to the PLC PCI9054 bridge device. The bus and control lines are terminated with 10 ohm stub resistance that should be placed close to the J1 connector pins. For this reference design the PCI 9054 operates with a 32-bit non-multiplexed bus (C-mode) on the local bus side. Address lines LA<31...2> provide 32-bit word addressing. The lower two bits of the address lines are used for 16 or 8 bit
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EECS EESK EEDI/O
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SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
byte access but are unused in this application. The CPLD (Section 7.5.1) implements the local bus glue logic. A serial EEPROM is required for device configuration after reset or upon powerup. PLX recommends Fairchild Semiconductor the 93CSX6L family serial EEPROMs. The PCI9054 can also be configured by an on board microprocessor/controller if desired. 7.7.2 Hot Swap Features The Hot Swap Controller is used to allow a board to be safely inserted or removed from a live cPCI slot. External N-channel MOSFETS control the 3.3V and 5V supplies, while the +12V and -12V supplies are controlled with on-chip switches. The supply voltages are ramped up at a programmable rate. The hot swap controller is implemented using the Linear Technology LTC1643L. A typical cPCI Hot Swap circuit is shown below in Figure 10. Note that only the hot swap controller is implemented in the power block. Additional Hot Swap circuitry including the precharge circuitry for the cPCI bus is included in the CompactPCI block. Figure 10 - cPCI Hot Swap Circuit
0.01 +5V_PCI +3.3V_PCI 0.005 R1 R3 V(I/O) CompactPCI Connector R6 1.2k R7 2k 3Vin 3Vsense GATE 3Vout 5Vin 5Vsense 5Vout 12Vin VEEin ON# V(I/O) 12V HEALTHYB 0.1uF GND 0.1uF R8 2k PWRGD# GND TIMER 0.01uF FAULT# 12Vout VEEout 12V 500mA -12V 100mA 10 100 R5 Q1 IRF7413 R2 R4 Q1 IRF7413
5V 5A 3.3V 7.6A
10
+12V_PCI -12V_PCI BD_SELB
LT1643L
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SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
The 3.3V, 5V, +12V, and -12V power supplies are generated from the medium length power pins on the PCI connector (+5V_PCI, +3.3V_PCI, etc). The long power pins which make the first connections are used to generate a 1V precharge voltage on the cPCI bus pins. In the circuit above, the 3.3V and 5V power supplies are controlled by the Nchannel pass transistors Q1 and Q2. Internal circuitry controls the +/-12V rails. R1 and R2 control overcurrent conditions. R5 and C1 provide current control loop compensation. R3 and R4 prevent high frequency oscillations in the pass transistors. Finally, the 12V Zener diode protects against power surges on the -12V rail. During an insertion and power-up sequence, the BD_SEL# pin is the final pin to connect to the board. This pin is connected to the ON# pin of the Hot Swap Controller. When the ON# pin is pulled low, the pass transistors are turned on by pulling the GATE pin high, and the current in each pass transistor rises at a rate of dv/dt = 50A/C1, until reaching the preset limit. If there is a high load capacitance, the rate of increase will be controlled by this value. Once the supply voltages stabilize the PWRGD# signal is pulled low. The current limit for the 5V and 3.3V supplies is set by the sense resistors R1 and R2 in Figure 10 above, and is governed by the following equation:
I lim = 53mV / Rsense
In the circuit shown above, the 3.3V current limit will be 10.6A, and the 5V limit will be 7.6A. Upon removal, the /ON pin will be pulled high, and the GATE pin on the pass transistors is pulled low to prevent load currents on the 3.3V and 5V rails from instantaneously going to zero and glitching the power supply. The /PWRGD pin is pulled high if any of the supply voltages moves below its threshold. Refer to the LT1643 datasheets for additional operation and applications information.
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PM5315 SPECTRA-2488
SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
7.8
Power The SPECTRA-2488 With TBS Quad OC-12 reference design requires 5V, 3.3V and 1.8V supplies. Power on 3.3V and 5V is distributed via the cPCI backplane from a centralized power supply. A 1.8V switching regulator has been implemented to lower the supply current requirements in the system to meet cPCI specifications and reduce overall power dissipation. Table 8: Card Maximum Estimated Power Consumption
PART SUPPLY
1.8 1.8
CURRENT
2163mA 1535 mA 3698mA
QUANTITY
1 1
POWER
3893 mW 2763 mW 6656 mW
SPECTRA-2488 TBS 1.8V MAX TOTAL SPECTRA-2488 TBS V23826-H18-C363 TQ8106 PI6C2502 PI49FCT3805 MB3100H OSCILATOR XC9572XL PLX9054 3.3V MAX TOTAL TQ8106 MC100EL14 MC100ELT22 PECL OSC. 5.0V MAX TOTAL
3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3
682 mA 365 mA 920 mA 64 mA 400mA 25 mA 90 mA 50 mA 250 mA 2846mA
1 1 4 1 4 1 1 1 1
2251 mW 1205 mW 3036 mW 211 mW 1320 mW 82.5mW 297mW 165mW 825 mW 9393mW
5.0 5.0 5.0 5.0
1292 mA 42 mA 22 mA 85 mA 1441 mA
4 1 1 1
6460 mW 210 mW 110 mW 425 mW 7205mW
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SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
7.9
Mechanical Form Factor This board is based on the cPCI 6U (233.35mm by 160mm) board size. The J1 connections have standard cPCI pinouts carrying 32 standard cPCI signals. The other connectors implemented in this reference design are the AMP Z-Pack HS3 60 Mbps pin connectors. These connectors are used to connect the 777.6 Mbps LVDS and control signals to the backplane. Note that the columns of the connector are separated by ground planes. Column 10 of the HS3 connector does not have ground shielding on it's outer side, therefore low speed signals are placed in this column. The pin assignments are made in the low-noise configuration as specified by AMP. Table 9 and Table 10 on the following page outlines the HS3 pinout. Table 9: Working and Protect HS3 Connector Pinout (J6)
Column 1 2 3 4 5 6 7 8 9 10A GND GND GND GND GND GND GND GND GND GND B SYSCLK1P RPPROT4 RPPROT3 RPPROT2 RPPROT1 RPWRK4 RPWRK3 RPWRK2 RPWRK1 TJ0FP_OUT C SYSCLK1N RNPROT4 RNPROT3 RNPROT2 RNPROT1 RNWRK4 RNWRK3 RNWRK2 RNWRK1 RJ0FP_IN D SYSCLK2P TPPROT4 TPPROT 3 TPPROT2 TPPROT1 TPWRK4 TPWRK3 TPWRK2 TPWRK1 RWSEL_IN E SYSCLK2N TNPROT4 TNPROT3 TNPROT2 TNPROT1 TNWRK4 TNWRK3 TNWRK2 TNWRK1 XCMP_IN F GND GND GND GND GND GND GND GND GND GND
Table 10: Auxiliary HS3 Connector Pinout (J5) Column 1 A GND B GND C GND D GND E GND F GND
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SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
Column 2 3 4 5 6 7 8 9 10
A GND GND GND GND GND GND GND GND GND
B GND GND GND GND GND GND GND GND GND
C GND GND GND GND GND GND GND GND GND
D TNAUX4 TNAUX3 TNAUX2 TNAUX1 GND RNAUX4 RNAUX3 RNAUX2 RNAUX1
E TPAUX4 TPAUX3 TPAUX2 TPAUX1 GND RPAUX4 RPAUX3 RPAUX2 RPAUX1
F GND GND GND GND GND GND GND GND GND
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SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
8
TABLE IMPLEMENTATION DESCRIPTION This section describes the hardware implementation of the SPECTRA-2488 With TBS Quad OC-12 Line Card Reference Design
8.1
Root Drawing (Schematic Page 1) This sheet shows the interconnection between the functional blocks of the design. The design is comprised of eight functional blocks: OPTICS_BLOCK, SERDES_BLOCK, SPECTRA_2488_BLOCK, TBS_BLOCK, CPLD_BLOCK, SYSTEM_INTERFACE_BLOCK, CPCI_BLOCK, and POWER_BLOCK
8.2
Optics Block (Schematic Page 2) This page shows the four fiber optic transceivers and their associated circuitry. The four Seimens V23826-H18-C363 Optical Data Links (ODLs) provides the optical to electrical (O/E) function for the SPECTRA-2488 device. The V23826H18-C363 transceiver is a 3.3V LVPECL device in a 1 x 9-pin package with a duplex SC receptacle. The PECL signals connect to the TQ8106 SERDES using differential, 50 controlled impedance signal lines. The transmit signals are terminated at the ODL with an internal 100 resistor. The transceivers have internal 390 pull-down resistors on the receive outputs as well as AC coupling capacitors on both transmit and receive interfaces. The signal detect (SD) signal is a 3.3 V TTL level signal and can interface directly to the SD input of the SPECTRA-2488. Ferrite beads and their associated 0.1 F bypass capacitors should be located as close as possible to the power pins of the fiber optic module. The 4.7 F bulk decoupling capacitors can be located conveniently around the optical modules.
8.3
SERDES Block (Schematic Pages 3, 4, 5, 6) The SERDES_BLOCK contains four Triqint TQ8106 8 bit OC-12 Serializer Deserializer chips, four 77.76 MHz PLLs, and power circuitry. Schematic page 3 shows the TQ8106 Serializer deserializer, 77.76 MHz PECL clock source Y1, 100ELT22 PECL clock buffer, power supply circuitry and the connections to the SPECTRA_2488 Block. PECL oscillator Y1 provides a 77.76 MHz reference clock for the TQ8106 CSU. The MC100EL buffers the 77.76 MHz PECL clock and distributes it to the other three TQ8106s. The MC100ELT22 provides TTL/PECL conversion for an external reference source. The Pericom PI6C2502 and its' associated components provide a 77.76 MHz PLL that is
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locked to the 77.76 MHz clock (TXBC) from the TQ8106 parallel interface and the TDCLK clock from the SPECTRA-2488 TX line side interface. This circuit ensures that the timing requirements between the TQ8106 and the SPECTRA2488 are met. The parallel input TX data to the TQ8106 (MXD[7:0]) is clocked into the device with respect to its' output clock TXBC. The parallel data bus signals should be routed such that they are less than four inches in length and the difference from trace to trace is less than .5 inches. The resistors attached to pins 72 and 73 can be configured to adjust the phase of the TXBC clock in 90 degree increments to ensure setup and hold times are met. All 0.1 F bypass capacitors should be placed as close as possible to the power pins as well as 10 F bulk capacitors located conveniently around the device. 100 differential and Thevenin terminations should be located as close to the input pins of the TQ8106 and the MC100EL14 devices as possible. 50 Thevenin terminations should be located as close as possible to input pin and have a 0.1 F bypass capacitor associated with it. Analog loop filters connected to pins FP1, FP2, CDRFP1, and CDRFP2 should have a good ground plane directly below them. Sheets 4, 5, and 6 are the same as sheet 3 except they have no PECL clock source, PECL clock buffer and TTL to PECL converter. 8.4 SPECTRA 2488 Block (Schematic Pages 7, 8, 9, 10, 11) The SPECTRA_2488_BLOCK shows the SPECTRA-2488 signals and power circuitry. Schematic page 7 contains the line interface section of the SPECTRA-2488 device. This interface consists of 32 TX data signals (TD4-1[7:0]), 32 RX data signals (RD4-1[7:0]), and their respective clocks (RCLK[4:1], RDCLK[4:1]). These signals are clocked at 77.76 MHz and should be 65 Ohm controlled impedance traces. Note although no source terminations have been shown, If trace lengths cannot be kept under 4 inches, it is recommended that 51 source terminations be used. Schematic page 8 contains power block section of the SPECTRA-2488 device. The power block shows all of the power and ground pins for the SPECTRA-2488 device. It is required that the 3.3 VDC I/O be powered before or at the same time as the 1.8 VDC core supply to prevent damage to the ESD protection structures within the SPECTRA-2488 device. The 1.8 V (RAVDL[3:0], TAVDL[3:0]) and 3.3 V (RAVDH[3:0], TAVDH[3:0]) analog power supplies are filtered with a RC network attached to each pin. Digital power pins have 0.1 F bypass capacitors placed as close as possible to the pins as well as 10 F bulk capacitors located conveniently around the device.
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SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
Schematic page 9 shows the SPECTRA-2488 incoming and outgoing Telecom Bus signals. These signals are clocked at 77.76 MHz and should be 65 Ohm controlled impedance traces. Note although no source terminations have been shown, If trace lengths cannot be kept under 4 inches, it is recommended that 51 source terminations be used. Schematic page 10 contains the SPECTRA-2488 Overhead, Ring Control Port, and Alarm signals. Some of the signals have been connected to the CPLD for future design considerations. The Ring Control Port signals have been connected to a 16 pin header (J2) for access when APS is implemented. Schematic page 11 contains the micro interface of the SPECTRA-2488 device. JTAG is not implemented in this design and the pins are left unconnected. Internal JTAG pull-up resistors maintain appropriate level. 8.5 TBS Block (Schematic Pages 12, 13, 14,15, 16) The TBS_BLOCK shows the TBS signals and power circuitry. Schematic page 12 contains S-TCB signaling and CHESS system signaling of the TBS device. The S-TCB signals connect directly to the HS3 connector and system backplane with 50 ohm controlled impedance lines. No end terminations are needed as all receive channels are internally 100 differentially terminated. Schematic page 13 contains the incoming and outgoing parallel Telecombus signals of the TBS device. All OPAIS<1..4>, OTV5<1..4>, OTPL<1..4>, OTAIS<1..4>, OCOUT<1..4>, and IPAIS<1..4>, ITV5<1..4>, ITPL<1..4> and ITAIS<1..4> signals are routed to a header. Schematic page 14 contains the micro interface of the TBS device. JTAG is not implemented in this design and the pins are left unconnected. Internal JTAG pull-up resistors maintain appropriate signal state. Schematic page 15 contains the power section of the TBS device. The digital 1.8V pins and 3.3V pins are connected to the supplies generated in the Power Block. All 3.3 V and the 1.8 V supply pins are decoupled with 0.1 F capacitors. The 1.8 V (AVDL[5:0]) and 3.3 V (AVDH[6:0]) analog power supplies are filtered with a RC network attached to each pin. The supply to the CSU_AVDH pin is passed through an RC filter to provide a clean voltage to the pin. The RES and RESK pins are externally attached via a 3.16 k resistor.
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8.6
System Interface Block (Schematic Page 16) The System Interface Block contains the AMP HS3 connectors for connection to the system backplane. The transmit and receive differential pairs are grouped together on the connector. The top HS3 connector contains the LVDS working and protect differential signals and the differential SYSCLK signals from a timing card. The bottom connector is used strictly for the LVDS auxiliary channels and has space for additional signals. This connector is optional and can be populated depending on the application requirements. All of the LVDS signal traces and the differential SYSCLK traces are 50 controlled impedance lines. More detailed information regarding layout of 777.76 MHz LVDS signals can be found in the "777.6 MHz LVDS DESIGN CONSIDERATIONS" document (PMC2000299 ).
8.7
CPLD Block (Schematic Page 17) The CPLD Block shows the signal connections of the Xilinx XC9572XL CPLD. The CPLD is used for address decoding, microprocessor access control, signal conversion, and clock distribution. Additionally, ring control and alarm signaling are connected for host processor access. The PECL differential clock signals, SYSCLK1(P,N) and SYSCLK2(P,N), are translated into single-ended TTL signals using the Motorola MC100EPT23 device. A 77.76 MHz local oscillator signal is also input to the CPLD for use in standalone testing or other configurations where a timing card is not available. Through software control, the CPLD can select which of the clock sources is to be used and the Pericom 49FCT3805 clock driver device is used to buffer this signal to the TBS (SYSCLK) and SPECTRA-2488 (ACK and DCK) devices. The Maxim MAX811T power supply monitor device with reset provides manual reset capability with a push-button switch attached to the master reset input. The Motorola MC74HC244 driver/buffer chip is used to drive the Lumex LXH5147 LED arrays. The microprocessor interrupt lines are routed to the LED's for device interrupt status. A header provides an interface to the CPLD JTAG pins for programming via an Xchecker cable. The CPLD code is currently under development and will be available at a future date.
8.8
CPCI Block (Schematic Pages 18, 19) The CPCI_BLOCK shows the PLX 9054 signal and power circuitry connections.
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The PCI9054 is a 3.3V/5V compliant PCI v2.2 32-bit, 33MHz Bus Master Interface Controller, that provides flexible local bus configurations and Hot Swap capability. The 32 bit multiplexed address/data bus and associated control lines connect directly from the CPCI J1 connector to the PLC PCI9054 interface device. The bus and control lines are terminated with 10 ohm stub resistance that should be placed close to the J1 connector pins. The PCI 9054 operates with a 32-bit non-multiplexed bus (C-mode) on the local bus side. Address lines LA<31...2> provide 32 bit word addressing. The lower two bits of the address lines are used for 16 or 8 bit byte access but are unused in this application. A serial EEPROM is required for device configuration after reset or upon powerup. The Fairchild Semiconductor NM93CS46 serial EEPROM is used to program the 9054. The Compact PCI specification outlines a number of layout requirements for the cPCI design. These include: * * * * * 8.9 All 10 ohm stub termination resistors must be placed within 0.6" of the J1 pins, All PCI signal traces must be less than 1.5" except P_CLK, P_CLK trace must be 2.5" +/- 0.1", CPCI bus traces impedance is 65 , 39 ohm stub resistor on REQ# should be placed near its source on the PCI9054.
Power Block (Schematic Page 20) The Power Block shows the power signal connections, the hot-swap controller, and voltage regulator for 1.8V requirements. The Power Block provides stable voltage supplies delivered over the CompactPCI backplane from a centralized power supply. Voltage levels of +5V, +3.3V, +12V, -12V and a regulated 1.8V are provided. All 3.3V power requirements for the board are sourced directly from the hot swap control circuitry. A switching regulator module is used to provide the 1.8V supply
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PM5315 SPECTRA-2488
SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
for digital pins of the SPECTRA-2488 and TBS devices. A 182 resistor at its output draws 10 mA to ensure stability in all load conditions.
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SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
9
SCHEMATICS
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30
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
PAGE 2 OPTICS_BLOCK
PAGE 3 - PAGE 6 SERDES_BLOCK
PAGE 7 - PAGE 11 SPECTRA_2488_BLOCK
PAGE 12 - PAGE 15 TBS_BLOCK
H PAGE 16 SYS_INTERFACE_BLOCK TJ0FP
TXD1P TXD1N RXD1P RXD1N SD1 TXD2P TXD2N RXD2P RXD2N SD2 G TXD3P TXD3N RXD3P RXD3N SD3 TXD4P TXD4N RXD4P RXD4N SD4
TXD1P TXD1N RXD1P RXD1N TXD2P TXD2N RXD2P RXD2N TXD3P TXD3N RXD3P RXD3N TXD4P TXD4N RXD4P RXD4N
TXD1P TXD1N RXD1P RXD1N TXD2P TXD2N RXD2P RXD2N TXD3P TXD3N RXD3P RXD3N TXD4P TXD4N RXD4P RXD4N
RD1<7..0> RD2<7..0> RD3<7..0> RD4<7..0> RDCLK1 RDCLK2 RDCLK3 RDCLK4 TD1<7..0> TD2<7..0> TD3<7..0> TD4<7..0> TCLK1 TCLK2 TCLK3 TCLK4 TDCLK1 TDCLK2 TDCLK3 TDCLK4
RD1<7..0> RD2<7..0> RD3<7..0> RD4<7..0> RDCLK1 RDCLK2 RDCLK3 RDCLK4 TD1<7..0> TD2<7..0> TD3<7..0> TD4<7..0> TCLK1 TCLK2 TCLK3 TCLK4 TDCLK1 TDCLK2 TDCLK3 TDCLK4
RD1<7..0> RD2<7..0> RD3<7..0> RD4<7..0> RDCLK1 RDCLK2 RDCLK3 RDCLK4 TD1<7..0> TD2<7..0> TD3<7..0> TD4<7..0> TCLK1 TCLK2 TCLK3 TCLK4 TDCLK1 TDCLK2 TDCLK3 TDCLK4
DROP_D<31..0> DJ0J1<4..1> DPL<4..1> DDP<4..1> IPAIS<4..1>
DROP_D<31..0> DJ0J1<4..1> DPL<4..1> DDP<4..1> IPAIS<4..1>
TJ0FP DROP_D<31..0> DJ0J1<4..1> DPL<4..1> DDP<4..1> IPAIS<4..1>
TJ0FP
TAUX<8..1> RAUX<8..1>
TAUX<8..1> RAUX<8..1>
TAUX<8..1> RAUX<8..1> G
ADD_D<31..0> AJ0J1<4..1> APL<4..1> ADP<4..1> APAIS<4..1>
ADD_D<31..0> AJ0J1<4..1> APL<4..1> ADP<4..1> APAIS<4..1>
ADD_D<31..0> AJ0J1<4..1> APL<4..1> ADP<4..1> APAIS<4..1>
TWRK<8..1> RWRK<8..1>
TWRK<8..1> RWRK<8..1>
TWRK<8..1> RWRK<8..1>
TPROT<8..1> RESETB RDB WRB RESETB RDB WRB RPROT<8..1> RESETB RDB WRB CSB_TBS INTB_TBS LD<31..0> LA<31..2> RWSEL_TBS RJ0FP_TBS OCMP_TBS TCMP_TBS SYSCLK
TPROT<8..1> RPROT<8..1>
TPROT<8..1> RPROT<8..1>
F
RESETB
RWSEL_TBS RJ0FP_TBS OCMP_TBS TCMP_TBS SYSCLK
SYSCLK1P SYSCLK1N SYSCLK2P SYSCLK2N XCMP FP RWSEL
F
LBM<1..0> MMS
LA<31..2> LD<31..0> PAGE 17 CPLD_BLOCK PAGE 18 - PAGE 19 CPCI_BLOCK LD<31..0> SYSCLK TCMP_TBS OCMP_TBS RJ0FP_TBS RWSEL_TBS SYSCLK1P SYSCLK1N SYSCLK2P SYSCLK2N XCMP FP RWSEL LD<31..0> LA<31..2> LHOLD LHOLDA L_ADSB L_READYB L_WRB SYSCLK1P SYSCLK1N SYSCLK2P SYSCLK2N XCMP FP RWSEL D SALM<4..1> RSLDCLK RSLD RLDCLK RLD LD<31..0> LA<31..2> LHOLD LHOLDA L_ADSB L_READYB L_WRB LHOLD LHOLDA L_ADSB L_READYB L_WRB L_USERI L_USERO L_RSTOB L_INTB L_CLK LA<31..2> E
E
SD1 SD2 SD3 SD4
INTB_TBS CSB_TBS WRB RDB RESETB CSB_SPECTRA INTB_SPECTRA TCLK1 PGMTCLK PGMRCLK RCLK<4..1>
CSB_SPECTRA INTB_SPECTRA TCLK1 PGMTCLK PGMRCLK RCLK<4..1> D SALM<4..1> RSLDCLK RSLD RLDCLK RLD
CSB_SPECTRA INTB_SPECTRA TCLK1 PGMTCLK PGMRCLK RCLK<4..1> SALM<4..1> RSLDCLK RSLD RLDCLK RLD
TSLDCLK TSLD TLDCLK TLD C DCMP ACMP DJ0REF DCK ACK
TSLDCLK TSLD TLDCLK TLD DCMP ACMP DJ0REF DCK ACK
TSLDCLK TSLD TLDCLK TLD DCMP ACMP DJ0REF DCK ACK
L_RSTOB L_INTB L_CLK
L_RSTOB L_INTB L_CLK
C
POWER_BLOCK 5V_PCI 3_3V_PCI 12V_PCI VEE_PCI BD_SELB HEALTHYB VIO_PCI
5V_PCI 3_3V_PCI 12V_PCI VEE_PCI BD_SELB HEALTHYB VIO_PCI B LBM<1..0> MMS PWROK_1_8V PAGE 20 PWROK_1_8V
5V_PCI 3_3V_PCI 12V_PCI VEE_PCI BD_SELB HEALTHYB VIO_PCI B PWROK
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-2000185 DOCUMENT ISSUE NUMBER: 2 DRAWING: TITLE=SPECTRA_2488_4XOC12_R2_ROOT ABBREV=SPECTRA_2488_4XOC12_R2_ROOT LAST_MODIFIED=Mon Dec 4 12:19:52 2000 10 9 8 7 6 5 4 3 TITLE: SPECTRA 2488 4XOC12 REF DESIGN ROOT_DRAWING ENGINEER: MK 2 ISSUE DATE: 00/02/03 REVISION NUMBER: 2 PAGE:1 1 OF 20 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
3.3 V
1.0UH 4.7UF 0.1UF 4.7UF 0.1UF L1 C144 1.0UH L3 4.7UF 0.1UF 4.7UF 0.1UF 4.7UF C212 C213 C115 C117 C36 C38 1.0UH L5 C113 1.0UH L6 C118
3.3 V
C19
4.7UF
G
G
6
5
6
3E2>
TXD1P\I
8 7
U8
4E1>
2 3 4
TXD2P\I
8 7
U12
3E2>
TXD1N\I
VCCTX VCCRX TXD+ 3.3V RXD+ TXDRXDV23826-H18-C363 SD TXGND RXGND
9 1
RXD1P\I RXD1N\I
7D9< SD1\I
3E2< 3E2< 4E1>
TXD2N\I
VCCTX VCCRX TXD+ 3.3V RXD+ TXDRXDV23826-H18-C363 SD TXGND RXGND
9 1
5
2 3 4
RXD2P\I RXD2N\I
7D9< SD2\I
4E1< 4E1<
F
F
E E
3.3 V
1.0UH 4.7UF 0.1UF 4.7UF 0.1UF L2 C112 C30 1.0UH L4 4.7UF 0.1UF 4.7UF 0.1UF 4.7UF C116 C232 C37 1.0UH L7 C114 1.0UH
3.3 V
D
C29
D
L8 C119 4.7UF
C31
6
5
C35
6
5E1>
TXD3P\I
8 7
U9
6E1>
2 3 4
TXD4P\I
8 7
U21
C
5E1>
TXD3N\I
VCCTX VCCRX TXD+ 3.3V RXD+ TXDRXDV23826-H18-C363 SD TXGND RXGND
9 1
RXD3P\I RXD3N\I SD3\I 7E9<
5E1< 5E1< 6E1>
TXD4N\I
VCCTX VCCRX TXD+ 3.3V RXD+ TXDRXDV23826-H18-C363 SD TXGND RXGND
9 1
5
2 3 4
RXD4P\I RXD4N\I
7F9< SD4\I
6E1< 6E1<
C
B
B
PMC-Sierra, Inc.
A DRAWING TITLE=OPTICS_BLOCK ABBREV=OPTICS_BLOCK LAST_MODIFIED=Fri Dec 10 9 8 7 6 5 4 DOCUMENT NUMBER: PMC-2000185 DOCUMENT ISSUE NUMBER: 2 TITLE: SPECTRA 2488 4XOC12 REF DESIGN OPTICS_BLOCK 8 15:52:41 2000 3 ENGINEER: MK 2 ISSUE DATE: 00/02/03 REVISION NUMBER: 2 PAGE:2 1 OF 20 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
5V
330
5V
330
330
330 R122
7D4<
R40
R41
5V Y1
0.1UF C298 14 7
18
20
R118
R120
8 1
R177 R178
0 0
0.1UF
C297
VCC2
VCC1
SOIC U13 G
7D4>
GND
OUTN
Q4 Q4 Q3 Q3
9 10 7 8 5 6 3 4 1 2 12
R135
OSC_PECL PWR OUTP
SOIC U6
330
TDCLK1\I
330
77.76MHZ TCLK1\I
8 5
20 PPM 3.3 V
19 330 330
CLK_IN CLK_OUT FB_IN FB_OUT PI6C2502 AVCC VCC AGND GND
3 2
5V
5V
REFCKEP4 REFCKEN4 REFCKEP3 REFCKEN3 REFCKEP2 REFCKEN2 REFCKEP1 REFCKEN1
6F1< 6F1< 5E1< 5E1< 4F1< 4F1<
G
10 R159 0.01UF
CDRAVDD1
4.7UF C141
AVDD1
0.01UF 4.7UF C147
10 R168
EN SCLK CLK CLK VBB
11
Q2 Q2 Q1 Q1 Q0 Q0 VEE SEL
MC100EL14
R173 100 16 15 14 13
J10 RIGHT_ANGLE
2
7 4
R180
C98
5
3
SMB
4 1
50 OHMS
49.9 R37
7 6
4 3
CDRAVDD1 F
5V 5V
100ELT22
R119 330 R121 330 R130 330 R163 330
SOIC U23 Q0 __ _ Q0 __ _ D1 Q1 Q1 D0
0.1UF
R183
C34
3.3 V
1 6
C32
1 2
0 0
R175 R176
3.3 V
39PF
4.7UF
C40
1.5K
R170
3.3 V
F
1 2
3.3 V
R87 330 330 R73 100 4.7K R7 4.7K R9 100 R6 100 R8 R88
TQFP U14
C33
27 50 63 74 97
29 33 37 41 45 55 85 89
28
96
26 49 75
3.3 V
2.0K R174
CDRAVDD
69 70 71 86
CKSRC[2] CKSRC[1] CKSRC[0] TXBC PH[1] PH[0] MXD[7] MXD[6] MXD[5] MXD[4] MXD[3] MXD[2] MXD[1] MXD[0] LBM[1] LBM[0] DXD[7] DXD[6] DXD[5] DXD[4] DXD[3] DXD[2] DXD[1] DXD[0] NOE NRESET RXBC FRPWR LOS CLRLOS LOR SDHCK SONETCK OC3 FP1 FP2 MMS DGND1 DGND2 DGND3 DGND4 DGND5 DGND6 DGND7 DGND8 AGND GND1 GND2 GND3 GND4 GND5 GND6
E
7D4>
72 73
TD1<7..0>\I
7 6 5 4 3 2 1 0 84 83 82 81 80 79 78 77 60 62 48 46 44 42 40 38 36 34 64 66 30 53 56 58 92 90 88 67 95 94 68
R171
220
17D8> 7D9<
LBM<1..0>\I
1 0
R21
4.7K
330
82.5
82.5
330
R35
D
17C10> 7D9<
330
7 6 5 4 3 2 1 0
R59
RD1<7..0>\I
R22
R20
5V
R36
130
R13
130
R71
C24
TQ8106
0.1UF
220
R172
CDRFP1 CDRFP2 REFCKT REFCKEP REFCKEN TXCKP TXCKN TXDP TXDN RXCKP RXCKN RXDP RXDN NSOL OOF DXSYNC NCDREN RLOCK
23 24 98 0.1UF C153 6 5 9 8 49.9 R169 49.9 R164 12 11 17 18 15 14 21 54 32 1 TP25 100 59 1 TP26
N14148W
SVDD1 SVDD2 SVDD3
VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8
VDD1 VDD2 VDD3 VDD4 VDD5
AVDD
680
R61
D4
50 OHMS 50 OHMS 50 OHMS 50 OHMS
5V
TXD1P\I TXD1N\I RXD1P\I RXD1N\I
2G10< 2F10< 2F7> 2F7>
E
D
RESETB\I RDCLK1\I
330 330 R10 R11 330 R12
TP3 TP4 TP5 TP6
1 1 1 1
PLACE TERMINATION NETWORKS CLOSE TO RESPECTIVE INPUTS
CDRGND
17D8>
MMS\I
C
330PF
301
R18
DVPP1 DVPP2 DVPP3 DVPP4 DVPP5 DVPP6
VNN1 VNN2
VPP1 VPP2
31 35 39 43 47 57 87 91
25 52 61 65 76 99
93
51
1 22
3 20
C28
0.33UF
AVDD1
C149
4 7 10 13 16 19
5V
C
B
B
5V
3.3 V
5V
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
10UF
C151
C121
C122
C123
C124
C125
C139
C146
C148
C152
C156
C157
C160
C161
C172
C173
C174
C175
C176
C177
C178
C179
C180
C181
C182
10UF
+
C183
+
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-2000185 DOCUMENT ISSUE NUMBER: 2 ISSUE DATE: 00/02/03 REVISION NUMBER: 2 PAGE:3 2 1 OF 20 A
A PLACE DECOUPLING CAPS CLOSE TO EACH POWER PIN
DRAWING ABBREV=SERDES_BLOCK TITLE=SERDES_BLOCK LAST_MODIFIED=Fri Dec 9 8 7 6 5 4
TITLE: SPECTRA 2488 4XOC12 REF DESIGN SERDES BLOCK CHANNEL ONE 8 15:52:25 2000 3 ENGINEER: MK
10
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
7D4< TDCLK2\I
H
SOIC U15
7D4> TCLK2\I
8 5
CLK_IN CLK_OUT FB_IN FB_OUT PI6C2502 AVCC VCC AGND GND
3 2
5V 5V
10 R179 0.01UF
CDRAVDD2
4.7UF C126 C199
AVDD2
0.01UF C142 C201 4.7UF
10 R181
G 3.3 V
G
7 4 C185
0.1UF
1 6
CDRAVDD2
5V 5V
C42 680
R156
CDRAVDD
R124 330
100 R26
4.7K R25
69 70 71 86 72 73
CKSRC[2] CKSRC[1] CKSRC[0] TXBC PH[1] PH[0] MXD[7] MXD[6] MXD[5] MXD[4] MXD[3] MXD[2] MXD[1] MXD[0] LBM[1] LBM[0] DXD[7] DXD[6] DXD[5] DXD[4] DXD[3] DXD[2] DXD[1] DXD[0] NOE NRESET RXBC FRPWR LOS CLRLOS LOR SDHCK SONETCK OC3 FP1 FP2 MMS DGND1 DGND2 DGND3 DGND4 DGND5 DGND6 DGND7 DGND8 AGND GND1 GND2 GND3 GND4 GND5 GND6
7E4>
TD2<7..0>\I
7 6 5 4 3 2 1 0 84 83 82 81 80 79 78 77 60 62 48 46 44 42 40 38 36 34 64 66 30 53 56 58 92 90 88 67 95 94 68
E
17D8> 7E9<
LBM<1..0>\I
1 0
CDRFP1 CDRFP2 REFCKT REFCKEP REFCKEN TXCKP TXCKN TXDP TXDN RXCKP RXCKN RXDP RXDN NSOL OOF DXSYNC NCDREN RLOCK
23 24 98 0.1UF C154 6 5 9 49.9 R127 49.9 R165 8 12 11 17 18 15 14 21 54 32 1 TP27 100 59 1 TP28 R186 4.7K R185 220 220 R187 82.5 82.5
2
R24
R23
330
R103
100
100
4.7K
SVDD1 SVDD2 SVDD3
N14148W
F
3.3 V
R125
TQFP U16
39PF
3.3 V
27 50 63 74 97 29 33 37 41 45 55 85 89 28 96 26 49 75
C43
4.7UF 1.5K
R182 2.0K R184
3.3 V
1
F
VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8
VDD1 VDD2 VDD3 VDD4 VDD5
AVDD
D5
REFCKEP2 REFCKEN2 50 OHMS 50 OHMS 50 OHMS 50 OHMS
5V
3G1> 3G1> 2G5< 2F5< 2F2> 2F2>
TXD2P\I TXD2N\I RXD2P\I RXD2N\I
E
RD2<7..0>\I
7 6 5 4 3 2 1 0
R75
R42
330
330
R43
R94
TQ8106
0.1UF
5V
330
R15
R78
130
17C10> 7D9<
RESETB\I RDCLK2\I
330 330 R14 R30 330 R38
D
TP7 TP8 TP9 TP10
1 1 1 1
130
R95
C99
D PLACE TERMINATION NETWORKS CLOSE TO RESPECTIVE PINS
CDRGND
17D8>
MMS\I
DVPP1 DVPP2 DVPP3 DVPP4 DVPP5 DVPP6
4 7 10 13 16 19
5V
VNN1 VNN2
1 22
31 35 39 43 47 57 87 91
25 52 61 65 76 99
93
51
330PF
C
301
R39
3 20
VPP1 VPP2
C
C41
0.33UF
AVDD2
C140
B
5V
B 3.3 V
5V
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
10UF
0.1UF
C184
C187
C188
C189
C190
C191
C192
C193
C194
C195
C196
C197
C198
C202
C203
C204
C205
C206
C207
C208
C209
C210
C211
C214
C216
10UF
C217
+
+
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-2000185 DOCUMENT ISSUE NUMBER: 2 PLACE DECOUPLING CAPS CLOSE TO EACH POWER PIN DRAWING ABBREV=SERDES_BLOCK TITLE=SERDES_BLOCK LAST_MODIFIED=Fri Dec 9 8 7 6 5 4 TITLE: SPECTRA 2488 4XOC12 REF DESIGN SERDES BLOCK CHANNEL TWO 8 15:52:29 2000 3 ENGINEER: MK 2 ISSUE DATE: 00/02/03 REVISION NUMBER: 2 PAGE:4 1 OF 20 A
10
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
7E4<
TDCLK3\I
SOIC U17
7E4>
TCLK3\I
8 5
CLK_IN CLK_OUT FB_IN FB_OUT PI6C2502 AVCC VCC AGND GND
3 2
5V 5V
G 3.3 V
10 R194 0.01UF
CDRAVDD3
4.7UF C155 C241
AVDD3
0.01UF C186 C258 4.7UF
10 R195
G
7 4 C215
0.1UF
1 6
CDRAVDD3
5V 5V
39PF
R161
CDRAVDD
R148 330
R45 4.7K R47
R44 100 R46
330
R139
100
4.7K
100
SVDD1 SVDD2 SVDD3
69 70 71 86 72 73
CKSRC[2] CKSRC[1] CKSRC[0] TXBC PH[1] PH[0] MXD[7] MXD[6] MXD[5] MXD[4] MXD[3] MXD[2] MXD[1] MXD[0] LBM[1] LBM[0] DXD[7] DXD[6] DXD[5] DXD[4] DXD[3] DXD[2] DXD[1] DXD[0] NOE NRESET RXBC FRPWR LOS CLRLOS LOR SDHCK SONETCK OC3 FP1 FP2 MMS DGND1 DGND2 DGND3 DGND4 DGND5 DGND6 DGND7 DGND8 AGND GND1 GND2 GND3 GND4 GND5 GND6
7E4>
TD3<7..0>\I
7 6 5 4 3 2 1 0 84 83 82 81 80 79 78 77 60 62 48 46 44 42 40 38 36 34 64 66 30 53 56 58 92 90 88 67 95 94 68
E
17D8> 7E9<
LBM<1..0>\I
1 0
CDRFP1 CDRFP2 REFCKT REFCKEP REFCKEN TXCKP TXCKN TXDP TXDN RXCKP RXCKN RXDP RXDN NSOL OOF DXSYNC NCDREN RLOCK
23 24 98 0.1UF C158 6 5 9 8 49.9 R128 49.9 R166 12 11 17 18 15 14 21 54 32 1 TP29 100 59 1 TP30 4.7K R188 R63 330 330 R64 R189 220 220 R190
2
N14148W
3.3 V
R149
TQFP U18
C49
27 50 63 74 97
29 33 37 41 45 55 85 89
28
96
26 49 75
F
3.3 V
C50
4.7UF 1.5K
R196 2.0K
3.3 V
F
680
VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8
VDD1 VDD2 VDD3 VDD4 VDD5
AVDD
D6
1
R197
REFCKEP3 REFCKEN3 50 OHMS 50 OHMS 50 OHMS 50 OHMS TXD3P\I TXD3N\I RXD3P\I RXD3N\I
3G1> 3G1> 2C10< 2C10< 2C7> 2C7>
E
5V
RD3<7..0>\I
7 6 5 4 3 2 1 0
82.5
82.5
R96
R98
TQ8106
5V
0.1UF
330
R17
130
R97
D
17C10> 7E9<
RESETB\I RDCLK3\I
330 330 R16 R51 330 R55
130
R101
C111
D
TP11 TP12 TP13 TP14
1 1 1 1
PLACE TERMINATION NETWORKS CLOSE TO RESPECTIVE PINS
CDRGND
17D8>
MMS\I
DVPP1 DVPP2 DVPP3 DVPP4 DVPP5 DVPP6
4 7 10 13 16 19
5V
VNN1 VNN2
1 22
31 35 39 43 47 57 87 91
25 52 61 65 76 99
93
51
C
330PF
301
R56
3 20
VPP1 VPP2
C
C48
0.33UF
AVDD3
C150
B
5V
B 3.3 V
5V
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
10UF
0.1UF
C218
C219
C220
C221
C222
C223
C224
C226
C227
C228
C229
C230
C231
C233
C234
C235
C240
C242
C243
C244
C245
C246
C247
C248
C249
10UF
C250
+
+
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-2000185 DOCUMENT ISSUE NUMBER: 2 PLACE DECOUPLING CAPS CLOSE TO EACH POWER PIN DRAWING ABBREV=SERDES_BLOCK TITLE=SERDES_BLOCK LAST_MODIFIED=Fri Dec 9 8 7 6 5 4 TITLE: SPECTRA 2488 4XOC12 REF DESIGN SERDES BLOCK CHANNEL THREE 8 15:52:34 2000 3 ENGINEER: MK 2 ISSUE DATE: 00/02/03 REVISION NUMBER: 2 PAGE:5 1 OF 20 A
10
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
7F4<
H TDCLK4\I
SOIC U19
7E4>
TCLK4\I
8 5
CLK_IN CLK_OUT FB_IN FB_OUT PI6C2502 AVCC VCC AGND GND
3 2
5V 5V
10 R198 0.01UF
CDRAVDD4
4.7UF C200 C287
AVDD4
0.01UF C239 C289 4.7UF
10 R199
G
7 4
G
3.3 V
0.1UF
C225
1 6
CDRAVDD4
5V 5V
4.7UF
3.3 V
R157
C143
1.5K
R200 2.0K R201
3.3 V
R162
CDRAVDD
R72 4.7K R77
R69 R155 330 330 100 R74 R153
SVDD1 SVDD2 SVDD3
69 70 71 86 72 73
CKSRC[2] CKSRC[1] CKSRC[0] TXBC PH[1] PH[0] MXD[7] MXD[6] MXD[5] MXD[4] MXD[3] MXD[2] MXD[1] MXD[0] LBM[1] LBM[0] DXD[7] DXD[6] DXD[5] DXD[4] DXD[3] DXD[2] DXD[1] DXD[0] NOE NRESET RXBC FRPWR LOS CLRLOS LOR SDHCK SONETCK OC3 FP1 FP2 MMS DGND1 DGND2 DGND3 DGND4 DGND5 DGND6 DGND7 DGND8 AGND GND1 GND2 GND3 GND4 GND5 GND6
7F4>
TD4<7..0>\I
7 6 5 4 3 2 1 0 84 83 82 81 80 79 78 77 60 62 48 46 44 42 40 38 36 34 64 66 30 53 56 58 92 90 88 67 95 94 68
E
17D8> 7F9<
1 0
R104
82.5
17C10> 7F9<
RESETB\I RDCLK4\I
330 330 R27 R82 330 R86
D
TP15 TP16 TP17 TP18
1 1 1 1
330
7 6 5 4 3 2 1 0
82.5
R106
R92
330
330
R93
RD4<7..0>\I
4.7K
R191
220
LBM<1..0>\I
R192
CDRFP1 CDRFP2 REFCKT REFCKEP REFCKEN TXCKP TXCKN TXDP TXDN RXCKP RXCKN RXDP RXDN NSOL OOF DXSYNC NCDREN RLOCK
23 24 98 6 5 9 49.9 R129 8 12 11 17 18 15 14 21 54 32 1 TP31 100 59 1 TP32
2
0.1UF C162
N14148W
F
4.7K
100 100
TQFP U20
C127
27 50 63 74 97
29 33 37 41 45 55 85 89
28
96
26 49 75
3.3 V
39PF
1
F
680
VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8
VDD1 VDD2 VDD3 VDD4 VDD5
AVDD
D7
REFCKEP4 REFCKEN4 50 OHMS 50 OHMS 50 OHMS 50 OHMS
5V
3G1> 3G1> 2C5< 2C5< 2C2> 2C2>
49.9 R167
TXD4P\I TXD4N\I RXD4P\I RXD4N\I
220
R193
E
5V
R105
130
R28
130
R107
C145
TQ8106
0.1UF
PLACE TERMINATION NETWORKS CLOSE TO RESPECTIVE INPUT PINS
D
CDRGND
17D8>
MMS\I
DVPP1 DVPP2 DVPP3 DVPP4 DVPP5 DVPP6
4 7 10 13 16 19
5V
VNN1 VNN2
1 22
31 35 39 43 47 57 87 91
25 52 61 65 76 99
93
51
C
330PF
301
R89
3 20
VPP1 VPP2
C
C51 0.33UF C159
AVDD4
B
5V
B 3.3 V
5V
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
10UF
0.1UF
C251
C252
C253
C256
C257
C259
C260
C261
C262
C263
C264
C265
C266
C267
C268
C269
C270
C271
C272
C273
C274
C275
C276
C277
C278
10UF
C279
+
+
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-2000185 DOCUMENT ISSUE NUMBER: 2 PLACE DECOUPLING CAPS CLOSE TO EACH POWER PIN DRAWING ABBREV=SERDES_BLOCK TITLE=SERDES_BLOCK LAST_MODIFIED=Fri Dec 9 8 7 6 5 4 TITLE: SPECTRA 2488 4XOC12 REF DESIGN SERDES BLOCK CHANNEL FOUR 8 15:52:38 2000 3 ENGINEER: MK 2 ISSUE DATE: 00/02/03 REVISION NUMBER: 2 PAGE:6 1 OF 20 A
10
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G
G
F
6E10>
RD4<7..0>\I
7 6 5 4 3 2 1 0 AE4 AF2 AE5 AF3 AG3 AH2 AK4 AJ5 AK5 AG6 AH6 V1 V2 V4 V5 W5 Y1 Y2 Y3 AA2 Y5 AA4 D2 E3 F5 E2 H5 G1 H4 H3 H1 J5 J3 C10 D10 A9 E10 D9 A8 E9 B8 A7 D8 B7 1 E8 P4 P5 R3 R4 N1
17E8<
RCLK<4..1>\I
4
2C2> 6D10>
SD4\I RDCLK4\I RD3<7..0>\I
7 6 5 4 3 2 1 0
5E10>
SBGA U4 SPECTRA2488 QUAD STS12 STM4 PM5315 1 of 5 RD4[7] TD4[7] RD4[6] TD4[6] RD4[5] TD4[5] RD4[4] TD4[4] RD4[3] TD4[3] RD4[2] TD4[2] TD4[1] RD4[1] RD4[0] TD4[0] SD4 TFPI4 RDCLK4 TDCLK4 RCLK4 TCLK4 RD3[7] RD3[6] RD3[5] RD3[4] RD3[3] RD3[2] RD3[1] RD3[0] SD3 RDCLK3 RCLK3 RD2[7] RD2[6] RD2[5] RD2[4] RD2[3] RD2[2] RD2[1] RD2[0] SD2 RDCLK2 RCLK2 RD1[7] RD1[6] RD1[5] RD1[4] RD1[3] RD1[2] RD1[1] RD1[0] SD1 RDCLK1 RCLK1 OOF ATP1 ATP0 TDREF1 TDREF0 PGMRCLK PGMTCLK LINE INTERFACE TD3[7] TD3[6] TD3[5] TD3[4] TD3[3] TD3[2] TD3[1] TD3[0] TFPI3 TDCLK3 TCLK3 TD2[7] TD2[6] TD2[5] TD2[4] TD2[3] TD2[2] TD2[1] TD2[0] TFPI2 TDCLK2 TCLK2 TD1[7] TD1[6] TD1[5] TD1[4] TD1[3] TD1[2] TD1[1] TD1[0] TFPI1 TDCLK1 TCLK1 TDCLK0P TDCLK0N
TD4<7..0>\I
AJ6 AG7 AK6 AH7 AG8 AL7 AH8 AJ8 AL9 AG9 AH9 7 6 5 4 3 2 1 0
6E10<
F
R131
4.7K
TDCLK4\I TCLK4\I TD3<7..0>\I
6H10> 6G10< 5E10<
E
2C7> 5D10>
3
SD3\I RDCLK3\I RD2<7..0>\I
7 6 5 4 3 2 1 0
AB2 7 AB3 6 AB4 5 AC1 4 AD1 3 AC5 2 AD2 1 AD3 0 AG10 AE1 AE2 K5 J1 K4 K3 L2 M5 M4 M3 U4 M1 N4 D7 B6 E7 C6 E6 C5 B4 D5 U3 E1 G5 AJ9 AK9 7 6 5 4 3 2 1 0
R132
4.7K
E TDCLK3\I TCLK3\I TD2<7..0>\I
5H10> 5G10< 4E10<
4E10>
2F2> 4D10>
2
SD2\I RDCLK2\I RD1<7..0>\I
7 6 5 4 3 2 1 0
R133
4.7K
3D10>
TDCLK2\I TCLK2\I TD1<7..0>\I
7 6 5 4 3 2 1 0
4H10> 4G10< 3E10<
D
D
2F7> 3D10>
1
SD1\I RDCLK1\I
TP37
2.67K R160
R134
4.7K
TDCLK1\I TCLK1\I
1 1
3G10> 3G10< 17E8<
TP38 TP39
17E8<
PGMRCLK\I
AH10
17E8< PGMTCLK\I
C
C
B
B
PMC-Sierra, Inc.
A NOTE:WHEN THE SPECTRA-2488 IS USED IN THE QUAD STS-12/STM4 MODE, THE FOLLOWING SIGNALS CAN BE TREATED AS N/CS: RDCLK+/-, RFP+/-, TFPI+/- AND TDCLK+/-. DOCUMENT NUMBER: PMC-2000185 DOCUMENT ISSUE NUMBER: 2 DRAWING: TITLE=SPECTRA_2488_BLOCK ABBREV=SPECTRA_2488_BLOCK LAST_MODIFIED=Fri Dec 8 15:53:06 2000 10 9 8 7 6 5 4 3 TITLE: SPECTRA 2488 4XOC12 REF DESIGN SPECTRA 2488 LINE INTERFACE ENGINEER: MK 2 ISSUE DATE: 00/02/03 REVISION NUMBER: 2 PAGE:7 1 OF 20 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
3.3 V
3.3 V
0.1UF
C58 0.1UF
C62 0.1UF
C66 0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
C82 0.1UF
C86 0.1UF
C90 0.1UF
C6 0.1UF
C96 0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
C107 0.1UF
C108 0.1UF
C109 0.1UF
C110 0.1UF
C16 0.1UF
10UF
10UF
10UF
C46 10UF
0.1UF
C70
C72
C74
C76
C78
C44
C45
C47
3.3 V
1.8 V G 1.8 V 1.8 V
2.2 R150
P2 E23 B15 E12 A5 J4 N2 W3 AG2 AL8 AJ14 AJ20 AL25 AE29 W29 R27 H27 A1 A31 B2 B30 C3 C4 C16 C28 C29 D3 D4 D16 D28 D29 E5 E11 E16 E21 E27 L5 L27 T3 T4 T5 T27 T28 T29 AA5 AA27 AG5 AG11 AG16 AG21 AG27 AH3 AH4 AH16 AH28 AH29 AJ3 AJ4 AJ16 AJ28 AJ29 AK2 AK30 AL1 AL31 R5 C8 E4 H2 M2 B9 D6 F2 K2 Y4 AD4 AG4 AK8
SBGA U4 SPECTRA2488 QUAD STS12 STM4 PM5315 5 of 5 QAVD QAVS VDDI15 VDDI14 VDDI13 VDDI12 VDDI11 VDDI10 VDDI9 VDDI8 VDDI7 VDDI6 VDDI5 VDDI4 VDDI3 VDDI2 VDDI1 VDDI0 VDD47 VDD46 VDD45 VDD44 VDD43 VDD42 VDD41 VDD40 VDD39 VDD38 VDD37 VDD36 VDD35 VDD34 VDD33 VDD32 VDD31 VDD30 VDD29 VDD28 VDD27 VDD26 VDD25 VDD24 VDD23 VDD22 VDD21 VDD20 VDD19 VDD18 VDD17 VDD16 VDD15 VDD14 VDD13 VDD12 VDD11 VDD10 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 VDD0 CAVDH RAVDH3 RAVDH2 RAVDH1 RAVDH0 RAVDL3 RAVDL2 RAVDL1 RAVDL0 TAVDH3 TAVDH2 TAVDH1 TAVDH0 TAVDL3 TAVDL2 TAVDL1 TAVDL0 VSS55 VSS54 VSS53 VSS52 VSS51 VSS50 VSS49 VSS48 VSS47 VSS46 VSS45 VSS44 VSS43 VSS42 VSS41 VSS40 VSS39 VSS38 VSS37 VSS36 VSS35 VSS34 VSS33 VSS32 VSS31 VSS30 VSS29 VSS28 VSS27 VSS26 VSS25 VSS24 VSS23 VSS22 VSS21 VSS20 VSS19 VSS18 VSS17 VSS16 VSS15 VSS14 VSS13 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 VSS0
C100
C102
C104
C105
C106
C128
+
+
+
+
C315
P3 A2 A3 A4 A6 A11 A16 A21 A26 A28 A29 A30 B1 B3 B16 B29 B31 C1 C2 C30 C31 D1 D31 F1 F31 L1 L31 T1 T2 T30 T31 AA1 AA31 AF1 AF31 AH1 AH31 AJ1 AJ2 AJ30 AJ31 AK1 AK3 AK16 AK29 AK31 AL2 AL3 AL4 AL6 AL11 AL16 AL21 AL26 AL28 AL29 AL30
G
0.1UF
C57 0.1UF
C61 0.1UF
C65 0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
C81 0.1UF
C85 0.1UF
C89 0.1UF
C93 0.1UF
C15 0.1UF
0.1UF
0.1UF
10UF
10UF
10UF
C27 10UF
C101
C103
+
+
+
C69
C71
C73
C75
C77
C97
C25
C26
C39
+
3.3 V
F
F
PLACE DECOUPLING CAPS CLOSE TO EACH POWER PIN
E
E
3.3 V
3.3 V
1.8 V
D
4.7 4.7 4.7 4.7 R34 R57 R62 R65 2.2 2.2 2.2 2.2 2.2 R66 R1 R2 R3 R4
D
CAVSH RAVSH3 RAVSH2 RAVSH1 RAVSH0 RAVSL3 RAVSL2 RAVSL1 RAVSL0 TAVSH3 TAVSH2 TAVSH1 TAVSH0 TAVSL3 TAVSL2 TAVSL1 TAVSL0
P1 C9 B5 G2 L3 B10 C7 F4 J2 W4 AC4 AF5 AK7 U5 AB1 AE3 AL5
1.8 V
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
C
C
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
C20
C55
C56
C59
C60
C63
C64
C67
W1 AB5 AG1 AJ7
C307
C68
C79
C80
C83
C84
C87
C88
C92
POWER
PLACE DECOUPLING CAPS CLOSE TO EACH POWER PIN
B
B
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-2000185 DOCUMENT ISSUE NUMBER: 2 DRAWING: TITLE=SPECTRA_2488_BLOCK ABBREV=SPECTRA_2488_BLOCK LAST_MODIFIED=Fri Dec 8 15:53:10 2000 10 9 8 7 6 5 4 3 TITLE: SPECTRA 2488 4XOC12 REF DESIGN SPECTRA 2488 POWER ENGINEER: MK 2 ISSUE DATE: 00/02/03 REVISION NUMBER: 2 PAGE:8 1 OF 20 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G
G
13D10<
DROP_D<31..0>\I
31 30 29 28 27 26 25 24 4 4 4 4 23 22 21 20 19 18 17 16 3 3 3 3 15 14 13 12 11 10 9 8 2 2 2 2 7 6 5 4 3 2 1 0 AE31 AD28 AD29 AD30 AC27 AD31 AC28 AC30 AB27 AD27 AC31 AE30 W30 W31 V27 V28 V29 V30 V31 U27 U28 W28 U29 W27 N28 N27 M31 M30 M29 M28 M27 L30 L28 N29 K31 N30 G30 G29 G28 F30 G27 F29 E31 F28 E30 G31 F27 H28 AE27 AG31 AF29
F
13C2< 13D2< 13C2< 13C2<
DPL<4..1>\I DDP<4..1>\I DJ0J1<4..1>\I IPAIS<4..1>\I
SBGA U4 SPECTRA2488 QUAD STS12 STM4 PM5315 3 of 5 DD4[7] AD4[7] DD4[6] AD4[6] DD4[5] AD4[5] DD4[4] AD4[4] DD4[3] AD4[3] DD4[2] AD4[2] DD4[1] AD4[1] AD4[0] DD4[0] APL4 DPL4 ADP4 DDP4 AJ0J1_FP4 DJ0J14 APAIS4 DALARM4 AD3[7] DD3[7] AD3[6] DD3[6] AD3[5] DD3[5] AD3[4] DD3[4] AD3[3] DD3[3] AD3[2] DD3[2] AD3[1] DD3[1] AD3[0] DD3[0] APL3 DPL3 ADP3 DDP3 AJ0J1_FP3 DJ0J13 APAIS3 DALARM3 AD2[7] DD2[7] AD2[6] DD2[6] AD2[5] DD2[5] AD2[4] DD2[4] AD2[3] DD2[3] AD2[2] DD2[2] AD2[1] DD2[1] AD2[0] DD2[0] DPL2 APL2 DDP2 ADP2 DJ0J12 AJ0J1_FP2 DALARM2 APAIS2 AD1[7] DD1[7] DD1[6] AD1[6] DD1[5] AD1[5] DD1[4] AD1[4] DD1[3] AD1[3] DD1[2] AD1[2] DD1[1] AD1[1] DD1[0] AD1[0] DPL1 APL1 DDP1 ADP1 DJ0J11 AJ0J1_FP1 DALARM1 APAIS1 DJ0REF ACK DCK ACMP DCMP TELECOM_BUS
13G10>ADD_D<31..0>\I
AB30 AB31 AA28 AA29 AA30 Y27 Y28 Y29 Y30 AB29 Y31 AB28 R31 R30 R29 R28 P31 P30 P29 P28 P27 U31 N31 U30 K28 J31 K27 J30 J29 J28 H31 J27 H30 K29 H29 K30 B28 C27 E26 B27 D26 A27 C26 E25 B26 D30 D25 E29 AE28 AF30 31 30 29 28 27 26 25 24 4 4 4 4 23 22 21 20 19 18 17 16 3 3 3 3 15 14 13 12 11 10 9 8 2 2 2 2 7 6 5 4 3 2 1 0 1 1 1 1
13G2> APL<4..1>\I 13G2> ADP<4..1>\I 13F2> AJ0J1<4..1>\I 13F2> APAIS<4..1>\I
F
E
E
D
1 1
1 1
D
17F1> 17F1> 17D8>
DJ0REF\I DCK\I DCMP\I
17G1> ACK\I 17D8> ACMP\I
C
C
B
B
PMC-Sierra, Inc.
A DRAWING TITLE=SPECTRA_2488_BLOCK ABBREV=SPECTRA_2488_BLOCK LAST_MODIFIED=Fri Dec 8 15:53:13 2000 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-2000185 DOCUMENT ISSUE NUMBER: 2 TITLE: SPECTRA 2488 4XOC12 REF DESIGN SPECTRA 2488 TELECOM BUS ENGINEER: MK 2 ISSUE DATE: 00/02/03 REVISION NUMBER: 2 PAGE:9 1 OF 20 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE
100MIL J2 H
1 2 3 4 1 2 3 4 1 2 3 4 4 3 2 1 4 3 2 1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
REV
DESCRIPTION
DATE
APPR
G
P_1 P_3 P_5 P_7 P_9 P_11 P_13 P_15 P_17 P_19 P_21 P_23 P_25 P_27 P_29 P_31 P_33 P_35 P_37 P_39 P_41 P_43 P_45 P_47 P_49
P_2 P_4 P_6 P_8 P_10 P_12 P_14 P_16 P_18 P_20 P_22 P_24 P_26 P_28 P_30 P_32 P_34 P_36 P_38 P_40 P_42 P_44 P_46 P_48 P_50
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 4 3 2 1
H
TPOHEN<4..1>
TPOHRDY<4..1> G
HEADER 25X2
5 RN2
7 RN3
5 RN3
7 RN4
6 RN4
8 RN5
6 RN5
8 RN6
6 RN6
8 RN7
6 RN7
8 RN8
F TOHCLK<4..1>
4 3 2 1
AG13 AK14 AL17 AK19 AL12 AH14 AL15 AL19
TOHFP<4..1>
4 3 2 1
SBGA U4 SPECTRA2488 QUAD STS12 STM4 PM5315 2 of 5 TOHCLK4 ROHCLK4 TOHCLK3 ROHCLK3 TOHCLK2 ROHCLK2 TOHCLK1 ROHCLK1 TOHFP4 TOHFP3 TOHFP2 TOHFP1 TTOH4 TTOH3 TTOH2 TTOH1 TTOHEN4 TTOHEN3 TTOHEN2 TTOHEN1 TPOH4 TPOH3 TPOH2 TPOH1 TPOHEN4 TPOHEN3 TPOHEN2 TPOHEN1 TPOHRDY4 TPOHRDY3 TPOHRDY2 TPOHRDY1 TSLDCLK TSLD TLDCLK TLD TRCPCLK4 TRCPCLK3 TRCPCLK2 TRCPCLK1 TRCPFP4 TRCPFP3 TRCPFP2 TRCPFP1 RPOH4 RPOH3 RPOH2 RPOH1 RPOHEN4 RPOHEN3 RPOHEN2 RPOHEN1 B3E1 ROHFP4 ROHFP3 ROHFP2 ROHFP1 RTOH4 RTOH3 RTOH2 RTOH1
4.7K 4 4.7K 2 4.7K 4 4.7K 2
4.7K 3 4.7K 1 4.7K 3 4.7K 1
4.7K 3 4.7K 1 4.7K 3 4.7K 1
F ROHCLK<4..1>
AL22 AG23 AG25 AH30 AH21 AL24 AK26 AG28 AJ21 AH23 AH25 AH27 4 3 2 1
ROHFP<4..1>
4 3 2 1
TTOH<4..1>
4 3 2 1 AJ12 AG14 AK15 AG18 AH12 AL13 AJ15 AK18 AG12 AK13 AH15 AL18 AK11 AJ13 AG15 AG17 AJ11 AH13 AL14 AH17 AH11 AL10 AK10 AJ10
RTOH<4..1>
4 3 2 1
TTOHEN<4..1> E TPOH<4..1>
4 3 2 1 4 3 2 1
E RPOH<4..1>
AK21 AJ23 AJ25 AK28 AG20 AK23 AK25 AJ27 AF27 1 4 3 2 1
TPOHEN<4..1>
4 3 2 1 4 3 2 1
RPOHEN<4..1>
4 3 2 1
TPOHRDY<4..1>
TP40
D
17D8< 17D8> 17D8< 17D8>
TSLDCLK\I TSLD\I TLDCLK\I TLD\I TRCPCLK<4..1>
4 3 2 1
RSLDCLK RLDCLK RSLD RLD SALM4 SALM3 SALM2 SALM1 RALM4 RALM3 RALM2 RALM1
AL20 AH19 AG19 AJ19 AJ22 AJ24 AL27 AG30 AK22 AK24 AJ26 AG29 AH20 AG22 AG24 AG26 4 3 2 1 1 1 1 1 4 3 2 1
17E8< RSLDCLK\I 17D8< RLDCLK\I 17D8< RSLD\I 17D8< RLD\I 17E8< SALM<4..1>\I
D
B23 A24 D24 B25 E22 D23 C24 E24 A23 C23 B24 A25
TRCPFP<4..1>
4 3 2 1
TRCPDAT<4..1>
4 3 2 1
TP42 TP43 TP44 TP45
TRCPDAT4 RRCPDAT4 TRCPDAT3 RRCPDAT3 TRCPDAT2 RRCPDAT2 TRCPDAT1 RRCPDAT1 TX/RX_OVRHD
8 RN1
7 RN1
6 RN2
8 RN3
6 RN3
8 RN4
5 RN4
7 RN5
5 RN5
7 RN6
5 RN6
7 RN7
5 RN7
6 RN1
5 RN1
8 RN2
4.7K 1
4.7K 2
7 RN2
4.7K 3 4.7K 1 4.7K 3 4.7K 1
4.7K 4 4.7K 2 4.7K 4 4.7K 2
4.7K 3 4.7K 4 4.7K 1 4.7K 2
4.7K 4 4.7K 2 4.7K 4 4.7K 2
7 RN8
C
C
B
B
J1
1 2 3 4 1 2 3 4 1 2 3 4 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31
A
P_1 P_3 P_5 P_7 P_9 P_11 P_13 P_15 P_17 P_19 P_21 P_23 P_25 P_27 P_29 P_31
P_2 P_4 P_6 P_8 P_10 P_12 P_14 P_16 P_18 P_20 P_22 P_24 P_26 P_28 P_30 P_32
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32
1 2 3 4 1 2 3 4
RRCPDAT<4..1>
ROHFP<4..1>
ROHCLK<4..1>
1 2 3 4
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-2000185 DOCUMENT ISSUE NUMBER: 2 DRAWING TITLE=SPECTRA_2488_BLOCK ABBREV=SPECTRA_2488_BLOCK LAST_MODIFIED=Fri Dec 8 15:53:16 2000 TITLE: SPECTRA 2488 4XOC12 REF DESIGN SPECTRA 2488 OVERHEAD ENGINEER: MK 3 2 ISSUE DATE: 00/02/03 REVISION NUMBER: 2 PAGE:10 1 OF 20 A
HEADER 16X2 CONN_MALE
10
9
8
7
6
5
4
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G
G
F
F
18H4<> 14F3<>
LD<31..0>\I
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D12 C12 B12 A12 E13 D13 C13 B13 A13 D14 C14 B14 A14 E15 D15 C15 A20 E19 C20 B20 D20 B21
E 3.3 V
SBGA U4 SPECTRA2488 QUAD STS12 STM4 PM5315 4 of 5 D[15] A[13] D[14] A[12] D[13] A[11] D[12] A[10] D[11] A[9] D[10] A[8] D[9] A[7] A[6] D[8] A[5] D[7] A[4] D[6] A[3] D[5] A[2] D[4] A[1] D[3] A[0] D[2] D[1] D[0] QUAD622 ALE TDO TDI CSB TMS WRB TCK RDB TRSTB RSTB INTB MICRO/JTAG
LA<31..2>\I
A15 A17 B17 C17 D17 E17 A18 B18 C18 D18 E18 A19 B19 C19 E20 C21 D21 A22 C22 B22 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2
18D4>
3.3 V
E
4.7K
R137
4.7K
R67
17E8> 17E8> 17E8> 17C10> 17E8<
CSB_SPECTRA\I WRB\I RDB\I RESETB\I INTB_SPECTRA\I
TP19
4.7K
R141
R138 4.7K
R140 4.7K
C
4.7K
R142
D
3.3 V
D
C
B
B
PMC-Sierra, Inc.
A DRAWING TITLE=SPECTRA_2488_BLOCK ABBREV=SPECTRA_2488_BLOCK LAST_MODIFIED=Fri Dec 8 15:53:19 2000 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-2000185 DOCUMENT ISSUE NUMBER: 2 TITLE: SPECTRA 2488 4XOC12 REF DESIGN SPECTRA 2488 BLOCK ENGINEER: MK 2 ISSUE DATE: 00/02/03 REVISION NUMBER: 2 PAGE:11 1 OF 20 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G
G
UBGA U11
16F10<
TWRK<8..1>\I
8 7 6 5 4 3 2 1
TPWRK4 TNWRK4 TPWRK3 TNWRK3 TPWRK2 TNWRK2 TPWRK1 TNWRK1 TPPROT4 TNPROT4 TPPROT3 TNPROT3 TPPROT2 TNPROT2 TPPROT1 TNPROT1 TPAUX4 TNAUX4 TPAUX3 TNAUX3 TPAUX2 TNAUX2 TPAUX1 TNAUX1
50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM
K24 K23 K26 K25 J25 J24 H24 H23 T25 T24 R26 R25 R24 R23 P26 P25 AA26 AA25 AA24 AA23 Y25 Y24 W26 W25 AC22 C23 AB25 AB23
TBS PM5310 1 of 5 TPWRK[4] RPWRK[4] TNWRK[4] RNWRK[4] TPWRK[3] TNWRK[3] TPWRK[2] TNWRK[2] TPWRK[1] TNWRK[1] RPWRK[3] RNWRK[3] RPWRK[2] RNWRK[2] RPWRK[1] RNWRK[1]
H25 H26 G24 G25 F23 F24 F25 F26 N25 N26 M23 M24 M25 M26 L24 L25 W23 W24 V24 V25 U25 U26 U23 U24 AD23 A24 AD12 C22
50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM 50 OHM
RPWRK4 RNWRK4 RPWRK3 RNWRK3 RPWRK2 RNWRK2 RPWRK1 RNWRK1 RPPROT4 RNPROT4 RPPROT3 RNPROT3 RPPROT2 RNPROT2 RPPROT1 RNPROT1 RPAUX4 RNAUX4 RPAUX3 RNAUX3 RPAUX2 RNAUX2 RPAUX1 RNAUX1
8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1
16F10> RWRK<8..1>\I
F
F
16G10<
TPROT<8..1>\I
8 7 6 5 4 3
TPPROT[4] RPPROT[4] TNPROT[4] RNPROT[4] TPPROT[3] RPPROT[3] TNPROT[3] RNPROT[3] TPPROT[2] RPPROT[2] TNPROT[2] RNPROT[2] TPPROT[1] RPPROT[1] TNPROT[1] RNPROT[1] TPAUX[4] TNAUX[4] TPAUX[3] TNAUX[3] TPAUX[2] TNAUX[2] TPAUX[1] TNAUX[1] TJ0FP TCMP RPAUX[4] RNAUX[4] RPAUX[3] RNAUX[3] RPAUX[2] RNAUX[2] RPAUX[1] RNAUX[1] RJ0FP OCMP SYSCLK RWSEL
16G10> RPROT<8..1>\I
E
16C10<
2 1
E
16A10> RAUX<8..1>\I
TAUX<8..1>\I
8 7 6 5 4 3 2 1
16E10< 17E4>
TJ0FP\I TCMP_TBS\I
17F1> RJ0FP_TBS\I
D
ATB1 ATB0 SERIAL TELECOMBUS
OCMP_TBS\I SYSCLK\I RWSEL_TBS\I
17E4> 17G1> 17E4>
D
C
C
B
B
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-2000185 DOCUMENT ISSUE NUMBER: 2 DRAWING: TITLE=TBS_BLOCK ABBREV=TBS_BLOCK LAST_MODIFIED=Fri Dec 10 9 8 7 6 5 4 TITLE: SPECTRA 2488 4XOC12 REF DESIGN TBS BLOCK SERIAL 8 15:53:21 2000 3 ENGINEER: MK 2 ISSUE DATE: 00/02/03 REVISION NUMBER: 2 PAGE:12 1 OF 20 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G
9F3<
UBGA U11 ADD_D<31..0>\I
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AF16 AD15 AE15 AF15 AD14 AE13 AD13 AF12 AA4 AC1 AB2 Y4 AB1 AA2 Y3 W4 M3 L1 M4 L2 K1 L3 K2 L4 D6 A4 B5 C6 D7 A5 C7 A6
G
9F3< ADP<4..1>\I
AF17 AB4 M1 A3 AC12 Y2 J1 B7 AE11 W3 K3 C8 AD16 AD4 N3 D3 AD17 AD5 P3 D2 AF18 AE4 P2 C1 AE17 AC5 N2 E4 AC15 AD1 M2 B4 1 1 1 1 4 3 2 1
F
E
TBS PM5310 2 of 5 OD[4][7] ODP[4] OD[4][6] ODP[3] OD[4][5] ODP[2] OD[4][4] ODP[1] OD[4][3] OD[4][2] OPL[4] OD[4][1] OPL[3] OD[4][0] OPL[2] OPL[1] OD[3][7] OD[3][6] OJ0J1[4] OD[3][5] OJ0J1[3] OD[3][4] OJ0J1[2] OD[3][3] OJ0J1[1] OD[3][2] OD[3][1] OPAIS[4] OD[3][0] OPAIS[3] OPAIS[2] OD[2][7] OPAIS[1] OD[2][6] OTV5[4] OD[2][5] OTV5[3] OD[2][4] OTV5[2] OD[2][3] OTV5[1] OD[2][2] OD[2][1] OD[2][0] OTPL[4] OTPL[3] OTPL[2] OD[1][7] OTPL[1] OD[1][6] OD[1][5] OD[1][4] OTAIS[4] OD[1][3] OTAIS[3] OD[1][2] OTAIS[2] OD[1][1] OTAIS[1] OD[1][0] OCOUT[4] OCOUT[3] OCOUT[2] OCOUT[1]
OUTGOING TELECOMBUS
9F3< APL<4..1>\I
4 3 2 1
9F3< AJ0J1<4..1>\I
4 3 2 1 4 3 2 1
9F3< APAIS<4..1>\I
F
TP33 TP34 TP35 TP36
E
D UBGA U11 TBS PM5310 3 of 5
9F9>
D
DROP_D<31..0>\I
9F9> DDP<4..1>\I
AE22 AE9 V2 G1 AD18 AD6 R2 F4 AF19 AF4 R1 E3 AF23 AD10 W1 H2 AF24 AD11 W2 H1 AE23 AE10 V3 K4 AC21 AF9 U4 J3 4 3 2 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AD21 AC20 AF22 AE21 AF21 AE20 AD19 AF20 AC10 AD9 AF7 AD8 AF6 AC8 AE6 AF5 U3 V1 U2 T3 T2 R4 T1 R3 G2 F1 G3 F2 E1 G4 F3 E2
ID[4][7] ID[4][6] ID[4][5] ID[4][4] ID[4][3] ID[4][2] ID[4][1] ID[4][0] ID[3][7] ID[3][6] ID[3][5] ID[3][4] ID[3][3] ID[3][2] ID[3][1] ID[3][0]
IDP[4] IDP[3] IDP[2] IDP[1] IPL[4] IPL[3] IPL[2] IPL[1] IJOJ1[4] IJOJ1[3] IJOJ1[2] IJOJ1[1]
9F9> DPL<4..1>\I
4 3 2 1
9F9> DJ0J1<4..1>\I
4 3 2 1
C
C
9F9> IPAIS<4..1>\I
B
IPAIS[4] IPAIS[3] IPAIS[2] ID[2][7] IPAIS[1] ID[2][6] ITV5[4] ID[2][5] ITV5[3] ID[2][4] ITV5[2] ID[2][3] ITV5[1] ID[2][2] ID[2][1] ID[2][0] ITPL[4] ITPL[3] ITPL[2] ID[1][7] ITPL[1] ID[1][6] ID[1][5] ID[1][4] ITAIS[4] ID[1][3] ITAIS[3] ID[1][2] ITAIS[2] ID[1][1] ITAIS[1] ID[1][0]
INCOMING TELECOMBUS
4 3 2 1
B
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-2000185 DOCUMENT ISSUE NUMBER: 2 DRAWING: TITLE=TBS_BLOCK ABBREV=TBS_BLOCK LAST_MODIFIED=Fri Dec 10 9 8 7 6 5 4 TITLE: SPECTRA 2488 4XOC12 REF DESIGN TBS_BLOCK OUTGOING/INCOMING 8 15:53:24 2000 3 ENGINEER: MK 2 ISSUE DATE: 00/02/03 REVISION NUMBER: 2 PAGE:13 1 OF 20 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G
G
F UBGA U11
18D4>
F
LA<31..2>\I
3.3 V E
4.7K 4.7K R68 R143
13 12 11 10 9 8 7 6 5 4 3 2
B13 B14 A15 B15 C15 A16 D15 B16 A17 C16 B17 D16
TBS PM5310 4 of 5 A[11]/TRS D[15] D[14] A[10] D[13] A[9] D[12] A[8] D[11] A[7] D[10] A[6] A[5] D[9] A[4] D[8] A[3] D[7] A[2] D[6] A[1] D[5] A[0] D[4] D[3] D[2] D[1] D[0] RSTB CSB WRB RDB ALE INTB TRSTB TCK TMS TDI TDO
17G10< 17E4<
A7 B8 C9 D10 B9 C10 A9 D11 B10 C11 B11 D12 A11 C12 B12 A12 B21 C21 D20 D19 B20 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
11E8<
18H4<> LD<31..0>\I
E
17C10> 17E8> 17E8> 17E8> 17F8<
RESETB\I CSB_TBS\I WRB\I RDB\I ALE INTB_TBS\I
A23 D17 B19 B18 C17 A20
1
TP20
R144 4.7K
R145 4.7K
3.3 V
D
4.7K
R146
MICRO JTAG
D
C
C
B
B
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-2000185 DOCUMENT ISSUE NUMBER: 2 DRAWING: TITLE=TBS_BLOCK ABBREV=TBS_BLOCK LAST_MODIFIED=Fri Dec TITLE: SPECTRA 2488 4XOC12 REF DESIGN TBS BLOCK MICRO/JTAG 8 15:53:26 2000 ENGINEER: MK 10 9 8 7 6 5 4 3 2 PAGE:14 1 OF 20 ISSUE DATE: 00/02/03 REVISION NUMBER: 2 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE
1.8 V 1.8 V H
0.1UF C131 0.1UF C135 0.1UF C164 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF C314 0.1UF C318 0.1UF C52 0.1UF C53 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF C323 0.1UF C326 0.1UF 10UF C328 10UF 10UF C254 C302 C306 C310 C129 C286 C308 C316 C320 C255 C329 C330 10UF C331
REV
DESCRIPTION
DATE
APPR
H + + + +
C3
3.3 V 3.3 V G
0.1UF C130 0.1UF C134 0.1UF C138 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF C313 0.1UF C317 0.1UF C321 0.1UF C132 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF C169 0.1UF C170 0.1UF C280 0.1UF 10UF C54 10UF 10UF C167 C171 C301 C305 C309 C133 C136 C137 C165 C166 C281 C285 C288 10UF C311
G + + + +
UBGA U11 PLACE DECOUPLING CAPS CLOSE TO EACH POWER PIN 3.3 V
V4 N4 H4 D8 D4 D23 D18 D13 C3 C24 B25 B2 AE25 AE2 AD3 AD24 AC9 AC4 AC23 AC19 AC14 A18 A21 A8 AC2 AD20 AD22 AD7 AE12 AE18 AE5 AE8 B6 C13 D1 D21 H3 J2 P4 U1 Y1 N23
F
1.8 V E
3.3 V
1.8 V
3.3 V
TBS PM5310 5 of 5 VSS39 VDDO0 VSS38 VDDO1 VSS37 VDDO2 VSS36 VDDO3 VSS35 VDDO4 VSS34 VDDO5 VSS33 VDDO6 VSS32 VDDO7 VSS31 VDDO8 VSS30 VDDO9 VSS29 VDDO10 VSS28 VDDO11 VSS27 VDDO12 VSS26 VDDO13 VSS25 VDDO14 VSS24 VDDO15 VSS23 VDDO16 VDDO17 VSS22 VDDO18 VSS21 VDDO19 VSS20 VDDO20 VSS19 VSS18 VSS17 VDDI19 VSS16 VDDI18 VSS15 VDDI17 VSS14 VDDI16 VSS13 VDDI15 VSS12 VDDI14 VSS11 VDDI13 VSS10 VDDI12 VDDI11 VSS9 VDDI10 VSS8 VDDI9 VSS7 VDDI8 VSS6 VDDI7 VSS5 VDDI6 VSS4 VDDI5 VSS3 VDDI4 VSS2 VSS1 VDDI3 VSS0 VDDI2 VDDI1 VDDI0 RES CSU_AVDH AVDH6 AVDH5 AVDH4 AVDH3 AVDH2 AVDH1 AVDH0 AVDL5 AVDL4 AVDL3 AVDL2 AVDL1 AVDL0 POWER RESK
A1 A13 A14 A2 A25 A26 AB26 AC25 AC26 AD2 AD25 AD26 AE1 AE24 AE26 AE3 AF1 AF13 AF14 AF2 AF25 AF26 B1 B24 B26 B3 C2 C25 C26 D25 D26 E26 G26 J26 L26 N1 P1 T26 V26 Y26 E25 E23 3.16K R5
F
E
R108
R109
R110
R111
R112
R113
R114
R115
R58
R60
R90
2.2
2.2
2.2
2.2
R91
2.2
2.2
2.2
0
0
0
0
0
D
AB24 AC24 D24 E24 J23 T23 Y23 G23 L23 P23 N24 P24 V23 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF C282 C283 C284 C290 C291 C292 C293 C294 C295 C296 C299 C300 C303 0.1UF C304
0
R116
4.7
R117
D
C
C
PLACE DECOUPLING CAPS CLOSE TO EACH POWER PIN
B
B
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-2000185 DOCUMENT ISSUE NUMBER: 2 DRAWING: TITLE=TBS_BLOCK LAST_MODIFIED=Fri Dec 8 15:53:30 2000 ENGINEER: AS 10 9 8 7 6 5 4 3 2 PAGE:15 1 OF 20 TITLE: SPECTRA 2488 4XOC12 REF DESIGN TBS BLOCK POWER ISSUE DATE: 00/02/03 REVISION NUMBER: 2 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
WORKING AND PROTECT LVDS LINKS
12F8> 12F3<
FEMALE_RA J6
AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10
TPROT<8..1>\I RPROT<8..1>\I
8 6 4 2 1 3 5 7 8 6 4 2 1 3 5 7
G FEMALE_RA J6
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AMP_HS3_6X10
G
FEMALE_RA J6
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10
FEMALE_RA J6
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 A9 B9 A10 B10 AMP_HS3_6X10
RPPROT4 RPPROT3 RPPROT2 RPPROT1 RPWRK4 RPWRK3 RPWRK2 RPWRK1
50 50 50 50 50 50 50 50
OHM OHM OHM OHM OHM OHM OHM OHM
50 50 50 50 50 50 50 50
OHM OHM OHM OHM OHM OHM OHM OHM
RNPROT4 RNPROT3 RNPROT2 RNPROT1 RNWRK4 RNWRK3 RNWRK2 RNWRK1
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10
C1 D1 C2 D2 C3 D3 C4 D4 C5 D5 C6 D6 C7 D7 C8 D8 C9 D9 C10 D10 AMP_HS3_6X10
TPPROT4 TPPROT3 TPPROT2 TPPROT1 TPWRK4 TPWRK3 TPWRK2 TPWRK1
50 50 50 50 50 50 50 50
OHM OHM OHM OHM OHM OHM OHM OHM
50 50 50 50 50 50 50 50
OHM OHM OHM OHM OHM OHM OHM OHM
TNPROT4 TNPROT3 TNPROT2 TNPROT1 TNWRK4 TNWRK3 TNWRK2 TNWRK1
E1 E2 E3 E4 E5 E6 E7 E8 E9 E10
E1 F1 E2 F2 E3 F3 E4 F4 E5 F5 E6 F6 E7 F7 E8 F8 E9 F9 E10 F10 AMP_HS3_6X10
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10
FEMALE_RA J6
CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10
CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10 AMP_HS3_6X10
F FEMALE_RA J6
12F3< 12F8>
F
RWRK<8..1>\I
8 6 4 2 1 3 5 7
TWRK<8..1>\I
12D8> 17E1<
TJ0FP\I SYSCLK1P\I SYSCLK1N\I FP\I RWSEL\I SYSCLK2P\I SYSCLK2N\I XCMP\I 50 OHM 50 OHM 50 OHM 50 OHM
EF1 EF2 EF3 EF4 EF5 EF6 EF7 EF8 EF9 EF10
EF1 EF2 EF3 EF4 EF5 EF6 EF7 EF8 EF9 EF10 AMP_HS3_6X10
8 6 4 2
1 3 5 7
E
17E1< 17E4< 17E4< 17E1< 17E1< 17E4<
E
D
TPROT<8..1>, TWRK<8..1>, RWRK<8..1>, RPROT<8..1>, TAUX<8..1> AND RAUX<8..1> CONSIST OF DIFFERENTIAL LVDS PAIRS. EACH PAIR SHOULD BE ROUTED TOGETHER ON THE SAME LAYER AND HAVE THE SAME LENGTH. ALL LVDS TRACES SHOULD BE 50 OHM.
D
FEMALE_RA J5 AUXILLARY LVDS LINKS DO NOT POPULATE CONNECTOR IF AUXILLARY LVDS LINKS NOT REQUIRED C
12E8>
AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10
TAUX<8..1>\I
7 5 3 1 2 4 6 8
AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AMP_HS3_6X10
C
FEMALE_RA J5
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
FEMALE_RA J5
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10
FEMALE_RA J5
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
FEMALE_RA J5
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10
B
A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 A9 B9 A10 B10 AMP_HS3_6X10
D1 C1 D2 C2 D3 C3 D4 C4 D5 C5 D6 C6 C7 D7 C8 D8 D9 C9 C10 D10 AMP_HS3_6X10
TNAUX4 TNAUX3 TNAUX2 TNAUX1 RNAUX4 RNAUX3 RNAUX2 RNAUX1
50 50 50 50
OHM OHM OHM OHM
50 50 50 50
OHM OHM OHM OHM
TPAUX4 TPAUX3 TPAUX2 TPAUX1 RPAUX4 RPAUX3 RPAUX2 RPAUX1
50 OHM 50 OHM 50 OHM 50 OHM
50 OHM 50 OHM 50 OHM 50 OHM
E1 E2 E3 E4 E5 E6 E7 E8 E9 E10
E1 F1 E2 F2 E3 F3 E4 F4 E5 F5 E6 F6 E7 F7 E8 F8 E9 F9 E10 F10 AMP_HS3_6X10
CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10 AMP_HS3_6X10
B
FEMALE_RA J5
EF1 EF2 EF3 EF4 EF5 EF6 EF7 EF8 EF9 EF10
DRAWING: TITLE=SYS_INTERFACE_BLOCK LAST_MODIFIED=Fri Dec 8 15:52:43 2000
12E3<
RAUX<8..1>\I
A
EF1 EF2 EF3 EF4 EF5 EF6 EF7 EF8 EF9 EF10 AMP_HS3_6X10
7 5 3 1
2 4 6 8
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-2000185 DOCUMENT ISSUE NUMBER: 2 TITLE: SPECTRA 2488 4XOC12 REF DESIGN SYSTEM_INTERFACE_BLOCK ENGINEER: MK ISSUE DATE: 00/03/22 REVISION NUMBER: 2 PAGE:16 2 1 OF 20 A
10
9
8
7
6
5
4
3
10
9
8
7
6
5
4
3
2
1
REVISIONS
VCC=3_3V SO20WB U10
1
ZONE
3.3 V
YA1 YA2 YA3 YA4
18 16 14 12 1 2 3 4
RES_ARRAY_4
REV
DESCRIPTION
DATE
APPR
OEA*
H
SPECTRA_INT TBS_INT LED_1 LED_2
2 4 6 8
A1 A2 A3 A4
SMD RN10 150
8 K1 7 K2 6 K3 5 K4
GREEN D1
A1 A2 A3 A4
H
LED SSF-LXH5147
3.3 V PLACE PI49FCT3805 CLOSE TO CPLD OUTPUT PIN 3.3 V
0.1UF C14 560 R289 20
MC74AHC244ADW
LED_3
TP46 TP47 TP48
1 1 1 4.7K 4.7K
11 13 15 17
B1 B2 B3 B4 OEB*
YA1 YB2 YB3
9 7 5 1 2 3 4
SMD RN9 150
8 K1 7 K2 6 K3 5 K4
RES_ARRAY_4
GREEN D2
A1 A2 A3 A4
YB4 3
LED SSF-LXH5147
R31
R32
4.7K
R33
19
G
G
12D3<
49.9 R298
U2
J13 2-767004-2
MICTOR 38 PIN
VCCA
1
VCCB
SYSCLK\I ACK\I
9D3<
14F3<> 18H4<>
LD<31..0>\I
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F
VCCINT VCCINT VCCINT
18D4>
LA<31..2>\I
39 40 41 42 43
17F8< 14E9< 14E9< 17F8<
E
14D9> 14E9< 11D8< 11D8< 11D8< 11D8> 7D4> 7C4> 7C9> 10D2>
INTB_TBS\I CSB_TBS\I WRB\I RDB\I CSB_SPECTRA\I INTB_SPECTRA\I TCLK1\I PGMTCLK\I PGMRCLK\I RSLDCLK\I
7F10>
RCLK<4..1>\I
16 13 18 20 14 15 25 17 28 33 36 1 29 2 39 3 30 4 1 40 22 TP41 23 27 1 2 3 4 87 94 91 93 95 96 97 1 6 8 9 11 10 12 92 3 4 99
VCCIO VCCIO VCCIO VCCIO
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37
P1 P3 P5 P7 P9 P11 P13 P15 P17 P19 P21 P23 P25 P27 P29 P31 P33 P35 P37
GNDA GNDB GNDQ
17D4> 18F2> 18F2> 17D4> 17D4> 17E8> 17E8> 17D4> 18F2>
P2 P4 P6 P8 P10 P12 P14 P16 P18 P20 P22 P24 P26 P28 P30 P32 P34 P36 P38
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38
BUF_ENA
9 10
OEA INA
L_CLK\I L_WRB\I L_ADSB\I L_READYB\I L_INTB\I CSB_TBS\I CSB_SPECTRA\I LHOLDA\I LHOLD\I
13 14 15 16 17
OA4 OA3 OA2 OA1 OA0 OB4 OB3 OB2 OB1 OB0 MON
7 6 4 3 2
49.9 1 1 R299
TP1 TP2
49.9 R300 49.9
PI49FCT3805
9D9< DCK\I 9D9< DJ0REF\I
12
OEB INB
3.3 V
11
14 1 TP21 15 1 TP22 17 1 18 TP23 19 12D3< 13 1
R297 49.9 R301
RJ0FP_TBS\I F
TP24
5 57 98
3.3 V
10D2>
SALM<4..1>\I
3.3 V
0.1UF
4.7K
R262
LOCAL SYSCLK Y3
1 4
D TRI GND 77.76MHZ 100PPM 3V3 OUT
8 5 56 R263
10D2> 10D2> 10D2> 10D10> 10D10< 10D10> 10D10< 9D9< 9D3< 6D10< 5D10< 4D10< 3C10< 6E10< 5E10< 4E10< 3E10<
RSLD\I RLDCLK\I RLD\I TSLDCLK\I TSLD\I TLDCLK\I TLD\I DCMP\I ACMP\I LED_1 MMS\I
0 1
LBM<1..0>\I
IO4 IO1 IO4 IO1 IO4 IO1 IO4 IO1 IO1 12D3< IO4 12D3< IO4 IO1 IO4 IO1 IO4 IO1 IO1 16D10> IO4 IO4 IO1 IO1 16E10> IO4 IO4 IO1 IO4 IO1 IO1 20D8> IO4 IO4 IO1 IO1/GCK1 IO4 IO1/GCK2 IO4 IO1/GCK3 IO4 XC9572XL IO2 TQ100 IO3 IO2 10NS IO3 IO3 IO2 IO3 IO2 IO3 IO2 IO3 IO2 IO2 IO3 IO3 IO2 IO2 18F2< IO3 IO2 17F8< IO3 IO2 18F2> IO3 IO2 IO3 IO2 18F2> IO3 IO2 18E2< IO3 IO2 17F8< IO3 IO2/GTS1 IO3 IO2/GTS2 IO3 IO2/GSR IO3 TCK TDI TDO TMS
65 67 71 72 68 76 77 70 66 81 56 R19 74 82 85 78 89 14 86 15 90 16 79 17 41 32 49 50 35 53 54 37 42 60 52 61 63 55 56 64 58 59 48 45 83 47 0 1 2 3 4 5 6 7
5 16 8
U7
26 38 51 88
12D8< TCMP_TBS\I
SOIC8 U3
56 R290 56 R291 7 6 5
TTL PECL
EXTERNAL SYSCLK
R295 1 2 R296 3 4 8 100 100
OCMP_TBS\I RWSEL_TBS\I SYSCLK1 SYSCLK2 XCMP\I FP\I RWSEL\I TBS_INT SPECTRA_INT PWROK_1_8V\I
Q0 Q1 GND
D0P D0N D1P D1N VCC
0.1UF C13
50 OHM 50 OHM 50 OHM 50 OHM
SYSCLK1P\I SYSCLK1N\I SYSCLK2P\I SYSCLK2N\I
16E10> 16E10> 16E10> 16E10>
16E10>
MC100EPT23
3.3 V
E
18D4> LA<31..2>\I
LD<31..0>\I
14F3<> 18H4<>
C7
18F2> LHOLD\I
LHOLDA\I L_ADSB\I L_READYB\I L_WRB\I L_INTB\I L_CLK\I LED_2 LED_3 TCK TDI TDO TMS
D
17F8< 18F2<
17F8< 18E2<
3.3 V
1 2 3 4 5 6
GND GND GND GND GND GND GND GND
100MIL J3 P_1 P_2 P_3 P_4 P_5 P_6
18E2> L_RSTOB\I
21 31 44 62 69 75 84 100
3.3 V
0.1UF
C U1
14E9< 11D8< 4D10< 3D10< 6D10< 5D10<
12 4 C168
C SOT143 U25 SW1 83P VCC MAX811T RIGHT_ANGLE
3 1
PBNO
RESETB\I
11
74HC08
13
2
RESET MR GND
1
2
U1
1 3
74HC08
2
3.3 V B
3.3 V
3.3 V
6
U1
4
74HC08
B
5
C18 0.01UF
C23 0.01UF
0.01UF
C17 0.01UF
C4 0.01UF
C21 0.01UF
C22 0.01UF
0.1UF
C91 0.1UF
C94 0.1UF
C95 0.1UF
C8 0.1UF
C120 0.1UF
C1 0.1UF
C9 10UF
C10 10UF
C11 10UF
10UF
U1
C12
+
+
+
+
C5
C2
9 8
74HC08
10
PLACE DECOUPLING CAPS CLOSE TO PINS
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-2000185 DOCUMENT ISSUE NUMBER: 2 DRAWING: TITLE=CPLD_BLOCK ABBREV=CPLD_BLOCK LAST_MODIFIED=Fri Dec TITLE: SPECTRA 2488 4XOC12 REF DESIGN CPLD BLOCK 8 15:53:02 2000 3 ENGINEER: MK 2 ISSUE DATE: 00/02/03 REVISION NUMBER: 2 PAGE:17 1 OF 20 A
A
10
9
8
7
6
5
4
10
9
8
7
6
5
4
3
2
1
REVISIONS
CPCI BRIDGE
3.3 V H 3.3 V
4.7K R7_1
ZONE
REV
DESCRIPTION
DATE
APPR
H 3.3 V 3.3 V 3.3 V 3.3 V LD<31..0>\I
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
14F3<> 11E8< 17E4< 17G10<
4.7K 4.7K 4.7K 4.7K
4.7K 4.7K 4.7K 4.7K
4.7K 4.7K 4.7K 4.7K
4.7K 4.7K 4.7K 4.7K
6 8 7 7
95 96 97 98 100 101 102 103 104 105 106 107 110 111 112 113 114 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131
19H8<>
AD<31..0>
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 2 1 0
3.3 V
162 147 141 133 116 109 99 89 70 62 45 35 28 20 1 139 138 137 136 134 163 144 143 148 90 149 135 146 145 91 92 153 151 150 160 142 53 154 152 159 158 157 156 155 176 161 140 132 115 108 88 69 61 44 27 19
LD<31> LD<30> LD<29> LD<28> LD<27> LD<26> LD<25> LD<24> LD<23> LD<22> LD<21> LD<20> LD<19> LD<18> LD<17> LD<16> LD<15> LD<14> LD<13> LD<12> LD<11> LD<10> LD<9> LD<8> LD<7> LD<6> LD<5> LD<4> LD<3> LD<2> LD<1> LD<0>
7 6 5 8
6 8 6 7
7 5 8 5
G
F
19H8<>
C/BE<3..0>
AD<31> AD<30> AD<29> AD<28> AD<27> AD<26> AD<25> AD<24> AD<23> AD<22> AD<21> AD<20> AD<19> AD<18> AD<17> AD<16> AD<15> AD<14> AD<13> AD<12> AD<11> AD<10> AD<9> AD<8> AD<7> AD<6> AD<5> AD<4> AD<3> AD<2> AD<1> AD<0> C/BE<3> C/BE<2> C/BE<1> C/BE<0>
10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10
2 3 4 1 2 3 4 3 4 1 2 3 4 1 2 2 3 4 1 2 3 4 1 2 4 1 2 3 4 1 2 3 1 3 1 3 4 4 3 4 3 2 1 4 2 1 2 1
7 6 5 8 7 6 5 6 5 8 7 6 5 8 7 7 6 5 8 7 6 5 8 7 5 8 7 6 5 8 7 6 8 6 8 6 5 5 6 5 6 7 8 5 7 8 7 8
RN8_1 RN8_1 RN8_1 RN9_1 RN9_1 RN9_1 RN9_1 RN10_1 RN10_1 RN11_1 RN11_1 RN11_1 RN11_1 RN12_1 RN12_1 RN17_1 RN17_1 RN17_1 RN18_1 RN18_1 RN18_1 RN18_1 RN19_1 RN19_1 RN19_1 RN20_1 RN20_1 RN20_1 RN20_1 RN21_1 RN21_1 RN21_1 RN10_1 RN12_1 RN17_1 RN19_1 RN21_1 RN14_1 RN13_1 RN13_1 RN14_1 RN14_1 RN14_1 RN12_1 RN13_1 RN13_1 RN10_1
R16_1
ADX31 ADX30 ADX29 ADX28 ADX27 ADX26 ADX25 ADX24 ADX23 ADX22 ADX21 ADX20 ADX19 ADX18 ADX17 ADX16 ADX15 ADX14 ADX13 ADX12 ADX11 ADX10 ADX9 ADX8 ADX7 ADX6 ADX5 ADX4 ADX3 ADX2 ADX1 ADX0 CBEX3 CBEX2 CBEX1 CBEX0 ENUMX PARX DEVSELX STOPX SERRX PERRX LOCKX FRAMEX TRDYX IRDYX IDSELX REQX
173 174 175 2 3 4 5 8 9 10 11 12 13 14 15 31 32 33 34 36 37 38 39 40 42 43 46 47 48 49 50 51 6 16 30 41 167 52 29 22 23 26 25 24 17 21 18 7 172 169 171 170 168
AD<31> AD<30> AD<29> AD<28> AD<27> AD<26> AD<25> AD<24> AD<23> AD<22> AD<21> AD<20> AD<19> AD<18> AD<17> AD<16> AD<15> AD<14> AD<13> AD<12> AD<11> AD<10> AD<9> AD<8> AD<7> AD<6> AD<5> AD<4> AD<3> AD<2> AD<1> AD<0>
VDD15 VDD14 VDD13 VDD12 VDD11 VDD10 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 DP<3> DP<2> DP<1> DP<0>
5 6 5 8
4.7K 4.7K 4.7K 4.7K RN4_1 RN5_1 RN5_1 RN4_1
4 3 4 1
RES_ARRAY_4
2 3 4 1
3 1 3 2
2 4 1 4
RN2_1 RN2_1 RN2_1 RN1_1
RN1_1 RN5_1 RN3_1 RN3_1
RN1_1 RN3_1 RN2_1 RN1_1
RN4_1 RN3_1 RN5_1 RN4_1
3 1 2 2
G
PART#PCI9054-AB50PI
U2_1
BTERM* BIGEND* LHOLDA LHOLD BLAST* LW/R* BREQO READY* LSERR* ADS* LBE2* LBE3* DMPAF/EOT* WAIT* BREQI CCS* LCLK LEDON/LEDIN LINT* LRESETO* USERI/DACK0/LLOCKI* USERO/DREQ0/LLOCKO* MODE<1> MODE<0> TEST VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1
17D4> LHOLDA\I
LHOLD\I
17F8< 17D4< L_WRB\I
17D4< 17F8<
L_READYB\I L_ADSB\I
F
17D4> 17D4< 17F8<
PCI9054 C-MODE
C/BE<3>* C/BE<2>* C/BE<1>* C/BE<0>* PME* ENUM* PAR DEVSEL* STOP* SERR* PERR* LOCK* FRAME* TRDY* IRDY* IDSEL REQ* RST* GNT* PCLK INTA* EEDI/O EESK EECS
19C5< P_ENUMB 19C5<> 19F5<> 19C5<> 19A5<>
10 P_PAR 10 P_DEVSELB 10 10 P_STOPB P_PERRB 10 10 10 10 10 10 10
39.2
17D4> L_CLK\I
19F5< P_SERRB
L_INTB\I L_RSTOB\I L_USERI\I L_USERO\I
17D4> 17D1<
E
19B5<> P_LOCKB 19E5<> 19B5<> 19D5<> 19E5> 19G5< 19D5> 19C5> 19G5< 19G1>
1 1K 2 1K 3 1K 4 1K
19B5> P_GNTB
LBE0* LBE1* LA<2> LA<3> LA<4> LA<5> LA<6> LA<7> LA<8> LA<9> LA<10> LA<11> LA<12> LA<13> LA<14> LA<15> LA<16> LA<17> LA<18> LA<19> LA<20> LA<21> LA<22> LA<23> LA<24> LA<25> LA<26> LA<27> LA<28> LA<29> LA<30> LA<31>
P_CLK 10 P_INTAB VIO_PCI\I
1
8
RN7_1
INTAX
5
8 7 6 5
RSTX
2
B A
VCC
166 165 164
RN15_1 RN15_1 RN15_1 RN15_1
RN6_1 RN6_1 RN6_1 RN6_1
DCK U5
8 7 6 5
1 1K 2 1K 3 1K 4 1K
P_FRAMEB P_TRDYB P_IRDYB P_IDSEL P_REQB P_RSTB
10
RN8_1
LBE0 LBE1
E
PWROK\I D 3.3 V 3.3 V
R14_1 4.7K
1
1.5K
GND
3
LBE0 94 LBE1 93
R99
87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 68 67 66 65 64 63 60 59 58 57 56 55 54
OUT
4
3.3 V D
0.1UF C16_1 0.1UF C17_1 0.1UF C15_1 0.1UF 0.1UF C14_1 0.1UF C19_1 0.1UF C22_1 0.1UF C13_1 C23_1 10UF C24_1 10UF
LA<31..2>\I
11E3< 14F8< 17E4< 17F8<
U1_1
NM93CS66LEN
C20_1 0.1UF
C21_1
10UF
8 7 6 5 R15_1
VCC PRE PE GND
CS SK DI DO
1 2 3 4 R13_1
+
PLACE AROUND U2
4.7K
C
PLACE NEAR U1
2.2K
C25_1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
+
+
C
PRECHARGE
D1_1
DL4148
ADJ U3_1
LT1117CST
1V_PRECHG 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K
1
2
2 4 150 R12_1
VOUT VIN TAB ADJ
3
3_3V_LONG
19H7>
VIO_LONG
19H7>
0.1UF
R11_1
C4_1
1
R10_1
8
5
8
100
7
10K 10K 10K 10K
8
5
6
7
5
7
6
7
8
5
8
6
6
7
8
8
5
6
7
7
5
6
7
8
5
6
5
6
7
8
5
6
7
6
8
8
5
8
7
6
5
7
8
5
7
6
24
100K
R8_1
1
4
3
2
4
2
3
2
1
4
1
3
3
2
1
1
4
3
2
2
4
3
2
1
4
3
4
3
2
1
4
3
2
3
1
1
4
1
2
3
4
2
1
4
2
RN22_1 RN22_1 RN22_1 RN23_1 RN23_1 RN23_1 RN23_1 RN24_1 RN24_1 RN24_1 RN25_1 RN25_1 RN25_1 RN25_1 RN26_1 RN26_1 RN26_1 RN30_1 RN30_1 RN31_1 RN31_1 RN31_1 RN31_1 RN32_1 RN32_1 RN33_1 RN33_1 RN33_1 RN33_1 RN34_1 RN34_1 RN34_1
RN24_1 RN26_1 RN30_1 RN32_1 RN30_1 RN29_1 RN29_1 RN29_1 RN29_1 RN32_1 RN28_1 RN28_1 RN28_1 RN28_1
3
B
B
1
4
1
RN34_1 RN22_1 RN27_1 RN27_1
2
CBEX0 CBEX1 CBEX2 CBEX3 FRAMEX IRDYX TRDYX DEVSELX STOPX IDSELX LOCKX PARX PERRX SERRX
DRAWING: TITLE=CPCI_BLOCK ABBREV=CPCI_BLOCK LAST_MODIFIED=Fri Dec P_GNTB
8 15:52:50 2000
ADX0 ADX1 ADX2 ADX3 ADX4 ADX5 ADX6 ADX7 ADX8 ADX9 ADX10 ADX11 ADX12 ADX13 ADX14 ADX15 ADX16 ADX17 ADX18 ADX19 ADX20 ADX21 ADX22 ADX23 ADX24 ADX25 ADX26 ADX27 ADX28 ADX29 ADX30 ADX31
RSTX ENUMX INTAX REQX
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-2000185 DOCUMENT ISSUE NUMBER: 2 TITLE: SPECTRA 2488 4XOC12 REF DESIGN CPCI_BLOCK ENGINEER: MK ISSUE DATE: 00/04/19 REVISION NUMBER: 2 PAGE:18 2 1 OF 20 A
A
NOTES: 1. 2. 3. 4. 5.
ALL 10 OHM STUBS WITHIN 0.6" ALL PCI SIGNAL TRACES < 1.5" P_CLK TRACE MUST BE 2.5" +/CPCI BUS TRACES ARE 65 OHM. 39 OHM STUB RESISTOR ON REQB
OF J1 EXCEPT P_CLK 0.1" PLACED NEAR BRIDGE PIN
10
9
8
7
6
5
4
3
10
9
8
7
6
5
4
3
2
1
REVISIONS
AD<31..0>
18H10<>
ZONE
REV
DESCRIPTION
DATE
APPR
H
18F10<> C/BE<3..0>
H 3.3 V
20F8<
20G8<
18C5<
18C3<
3_3V_PCI\I
1 2 3 4
4.7K 4.7K 4.7K 4.7K
5V_PCI\I
3_3V_LONG
VIO_LONG
RN16_1 8 RN16_1 7 RN16_1 6 RN16_1 5
CPCI J1
G
J1_1 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 ZPACK5X22A CPCI
A1 A2 A3 A4 A5 A6 A7 AD<30> A8 AD<26> A9 C/BE<3> A10 AD<21> A11 AD<18> A15 A16 A17 A18 A19 A20 AD<12> A21 A22 AD<7> A23 A24 AD<1> A25 B1 B2 B3 B4 B5 B6 B7 AD<29> B8 B9 B10 B11 AD<17> B15 B16 B17 B18 B19 AD<15> B20 B21 AD<9> B22 B23 AD<4> B24 B25 C1 C2 C3 C4 C5 C6 C7 AD<28> C8 C9 AD<23> C10 C11 AD<16> C15 C16 C17 C18 C19 AD<14> C20 C21 AD<8> C22 C23 AD<3> C24 C25 D1 D2 D3 D4 D5 D6 D7 D8 AD<25> D9 D10 AD<20> D11 D15 D16 D17 D18 D19 D20 AD<11> D21 D22 AD<6> D23 D24 AD<0> D25 E1 E2 E3 E4 E5 E6 AD<31> E7 AD<27> E8 AD<24> E9 AD<22> E10 AD<19> E11 C/BE<2> E15 E16 E17 E18 C/BE<1> E19 AD<13> E20 AD<10> E21 C/BE<0> E22 AD<5> E23 AD<2> E24 E25
VIO_PCI\I
PLACE DECOUPLING CAPS CLOSE TO CONNECTOR 5V_PCI\I
0.1UF C10_1 10UF
3_3V_PCI\I
0.1UF C5_1 0.1UF C12_1 10UF
VIO_PCI\I
0.1UF C9_1 10UF C11_1 10UF C8_1
18D9< 20F8<
C6_1
+
+
+
C7_1
+
G
18E9> P_INTAB 18E9> P_REQB
30 26 3 21 18
12V_PCI\I
0.1UF
VEE_PCI\I
0.1UF C18_1 10UF
18E9<> P_DEVSELB 18E9> P_SERRB
12 7 1
C1_1 10UF
C3_1
F
F1 F3 F5 F7 F9 F11 F13 F15 F17 F19 F21 F23 F25
F1 F3 F5 F7 F9 F11 F13 F15 F17 F19 F21 F23 F25
C2_1
+
+
F
20E8< VEE_PCI\I
HEALTHYB\I
29
20E8>
18E9< P_IDSEL
17
18E9<> P_FRAMEB
E
15 9 4
E
18E9< P_RSTB
28
P1_1
STRIP3
23 16
3
1
2 10M R2_1
HOLE_SIZE= 150 MIL
MOUNTING HOLE
D
18E9<> P_IRDYB
STRIP2
ESD STRIP
10M R3_1
TP2_1 T CHASSIS D TP1_1 T CHASSIS
14 8 3
STRIP1
CPCI ESD STRIP
18E9> P_ENUMB 20E8< 12V_PCI\I
1 R1_1
18E9< P_CLK
25 20
C
10M
C
20E8< BD_SELB\I 18E9<> P_STOPB 18E9<> P_PAR
11 6 0
B
B
18E9< P_GNTB
31 27 24 22 19 2
18E9<> P_TRDYB 18E9<> P_LOCKB 18E9<> P_PERRB
1 13 10 0 5 2
DRAWING: TITLE=CPCI_BLOCK ABBREV=CPCI_BLOCK LAST_MODIFIED=Fri Dec
8 15:52:54 2000
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-2000185 DOCUMENT ISSUE NUMBER: 2 TITLE: SPECTRA 2488 4XOC12 REF DESIGN CPCI_BLOCK ENGINEER: MK ISSUE DATE: 00/04/19 REVISION NUMBER: 2 PAGE:19 2 1 OF 20 A
A
10
9
8
7
6
5
4
3
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
H
G HOT SWAP CONTROLLER
100 R29
5V
G
3.3 V
19H7>
5V_PCI\I
8IRF7413 3 2 5 4 1
0.01 R15_2 7 6
7 6
8 IRF7413 3 2 5 4 1
+5V
19H8>
3_3V_PCI\I
0.01 R5_2 0.01 R14_2
+3.3V
R8_2 220UF
10
R6_2
C9_2
10
+
F
19G1>
100 R9_2 0.047UF C8_2
+12V
F
VIO_PCI\I
10 11 13 12 R2_2 R3_2 1.2K 2.0K 2.0K R4_2
U2_2
3V_SENSE
5V_SENSE
3V_OUT
19C5> 19F5> 19C5>
12V_PCI\I VEE_PCI\I BD_SELB\I
5V_OUT
3V_IN
5V_IN
GATE
14
9
3
1 2 5 6
12V_IN VEE_IN ONB FAULTB
12V_OUT VEE_OUT
16 15
12V_OUT VEE_OUT
LTC1643LCGN
5V
E
TIMER
R13_2
+12V
R12_2 R10_2 63.4
3.3 V
R11_2
E
19F5<
7
PWRGDB
GND
HEALTHYB\I D1_2
0.1UF C5_2 0.1UF 2 C6_2
560
560
150
8
0.01UF 4
GREEN D3
K1 K2 K3 K4
1
VEE
C7_2
A1 A2 A3 A4
LED SSF-LXH5147
GND VEE
D
17E4<
D PWROK_1_8V\I
5V
3.3 V
1.8 V
220UF
R16_2
2.2UF
C3_2 220UF
C1_2
100K
C2_2
C4_2 182
MAX812REUS-T
3
MR
RESET GND
1
2
9 10 11
PWROK SENSE TRIM ENABLE GND GND
5 6
3
R1_2
U3_2 VCC
2.2UF
C
7 8
+
+
U1_2 SIE501.8R VIN1 VOUT1 1 VIN2 VOUT2 2 VOUT3 4
4.7K
R7_2
4
C +
+
B
B
DRAWING: TITLE=POWER_BLOCK ABBREV=PCIPWRBLOCK LAST_MODIFIED=Fri Dec
8 15:52:57 2000
PMC-Sierra, Inc.
A DOCUMENT NUMBER: PMC-2000185 DOCUMENT ISSUE NUMBER: 2 TITLE: SPECTRA 2488 4XOC12 REF DESIGN POWER_BLOCK ENGINEER: MK 10 9 8 7 6 5 4 3 2 ISSUE DATE: 00/04/19 REVISION NUMBER: 2 PAGE:20 1 OF 20 A
RELEASED REFERENCE DESIGN PMC-2000185 ISSUE 2
PM5315 SPECTRA-2488
SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
10
BILL OF MATERIALS Table 11 : Major Components List
NO. Manufacturer Part Number 1 PANASONIC ECJ-1VB1C104K
Ref Des C1, C10_1, C11_1, C12_1, C13, C13_1, C14, C14_1, C15, C15_1, C2, C3, C6-C8, C16, C20, C24, C30-C32, C52, C53, C55-C97, C99-C111, C113C116, C120-C125, C128-C139, C144C146, C148, C152-C154, C156-C158, C160-C162, C164-C169, C16_1, C170-C179, C17_1, C180-C182, C184, C185, C187-C189, C18_1, C190-C193, C195-C198, C19_1, C1_1, C202-C212, C214-C216, C218, C219, C21_1, C220-C226, C228, C229, C22_1, C230, C231, C233C235, C23_1, C240, C242-C249, C251-C257, C259-C261, C263-C278, C280-C284, C286, C290-C310, C313-C318, C320, C321, C323, C326, C4_1, C5_2, C6_2, C9_1
Qty 260
Descriptions CAP-0.1UF, 16V, CERAMIC X7R_603
2 3
PANASONIC ECE-V1AA221P NEWARK -- 52F023
C1_2, C4_2, C9_2 C140, C149, C150, C159
3 4
CAP-220UF, 10V, ELECTROLYTIC CAP-0.33UF, 16V, MURATA NICKEL INNER ELECTRODE TYPE, Y5V_805
4
DIGI-KEY -- PCT2475CT-ND
C19, C29, C35-C38, C40, C43, C50, C112, C117-C119, C141, C143, C147, C199, C201, C213, C232, C241, C258, C287, C289
24
CAP-4.7UF, 10V, TANT TEH
5 6 7 8 9
PANASONIC ECS-H1VC225R PANASONIC ECS-H1CC106R PANASONIC ECU-V1H331KBN PANASONIC ECU-V1H390JCG PANASONIC ECU-V1H103KBV
C2_2, C3_2 C20_1, C24_1, C25_1, C2_1, C3_1, C5_1, C6_1, C7_1, C8_1 C28, C41, C48, C51 C33, C42, C49, C127 C4, C5, C17, C18, C21-C23, C34, C98, C126, C142, C155, C186, C200, C239, C7_2
2 9 4 4 16
CAP_POL-2.2UF, 35V, TANCAPC CAP_POL-10UF, 16V, TANCAPC CAP-330PF, 50V, CERAMIC, X7R_805 CAP-39PF, 50V, CERAMIC, NPO_805 CAP-0.01UF, 50V, CERAMIC, X7R_603
10
PANASONIC ECU-V1H473KBW
C8_2
1
CAP-0.047UF, 50V, CERAMIC, X7R_1206
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
31
RELEASED REFERENCE DESIGN PMC-2000185 ISSUE 2
PM5315 SPECTRA-2488
SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
NO. Manufacturer Part Number 11 PANASONIC ECS-T0JY106R
Ref Des C9-C12, C25-C27, C39, C44-C47, C54, C151, C183, C194, C217, C227, C250, C262, C279, C285, C288, C311, C328-C331
Qty 28
Descriptions CAP_POL-10UF, 6.3V, TANCAPA
12 13 14 15 16 17
MICROSEMI DL4148MS DIODES INC ZM4742A LUMEX SSF-LXH5147LGD VISHAY/LITE- ON 1N4148W SULLINS PZC36DAAN AMP 352068-1
D1_1 D1_2 D1-D3 D4-D7 J1 J1_1
1 1 3 4 1 1
DIODE RECT 150MA 75V SMT MINIMELF ZENER DIODE 12.0V 5% 1.0W SURFACE MOUNT LED QUAD GREEN HORIZONTAL SURFACE MOUNT SWITCHING DIODE CONN HEADER 2 ROW 0.1"X0.1" 2X16 CONNECTOR ZPACK CPCI 2MM HM 110 POS. TYPE A WITH GND SHIELD
18 19 20 21 22
JOHNSON COMPONENTS 1313701-341 AMP 2-767004-2 SULLINS PZC36DAAN X 25/36 SULLINS ELECTRONICS PZC36SAAN AMP 120673-1
J10 J13 J2 J3 J5, J6
1 1 1 1 2
50 OHM RIGHT ANGLE BULKHEAD JACK RECEPTACLE CONNECTOR 38 POS VERTICAL .025" TO .64" SMD MICTOR HEADER 25X2 GOLD 0.1" SPACING CONN HEADER STRAIGHT 36POS MALE .1" SINGLE ROW Z-PACK 6 ROW HS3 BACKPLANE CONNECTOR, RIGHT ANGLE RECEPTACLE
23 24 25 26 27 28 29 30 31
PANASONIC ELJ-FD1R0KF MOUNTING HOLE PART OF PCB INTERNATIONA L RECTIFIER IRF7413 PANASONIC ERJ-8GEYJ106V PANASONIC ERJ-3EKF1820V PANASONIC ERJ-3EKF1000V PANASONIC ERJ-3GSYJ151V PANASONIC ERJ-3GSYJ331V
L1-L8 M1_1 P1_1 Q1_2, Q2_2 R1_1, R2_1, R3_1 R1_2 R10_1, R173, R295, R296, R9_2 R10_2 R10-R17, R21, R22, R27, R28, R30, R38, R40-R43, R51, R55, R63, R64, R73, R82, R86, R87, R92, R93, R103, R118-R122, R124, R130,
8 1 1 2 3 1 5 1 44
INDUCTOR 1.0UH 10% TYPE FD 0805 MOUNTING_HOLE_150MIL BASE PART OF PCB COMPACT PCI ESD STRIP IC POWER MOSFET, SOIC-BASE RES-10M, 5%, 1206 RES-182, 1%, 603 RES-100, 1%, 603 RES-150, 5%, 603 RES-330, 5%, 603
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
32
RELEASED REFERENCE DESIGN PMC-2000185 ISSUE 2
PM5315 SPECTRA-2488
SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
NO. Manufacturer Part Number
Ref Des R135, R139, R148, R153, R155, R163, R180, R183
Qty
Descriptions
32 33 34 35 36 37 38
PANASONIC ERJ-6GEYJ240V PANASONIC ERJ-3EKF63R4V PANASONIC ERJ-3GSY0R00V PANASONIC ERJ-3EKF1500V PANASONIC ERJ-3GSYJ561V PANASONIC ERJ-3GSYJ222V PANASONIC ERJ-3GSYJ472V
R11_1 R11_2 R111-R116, R175-R178 R12_1 R12_2, R13_2, R289 R13_1 R14_1, R15_1, R7, R9, R20, R23, R25, R45, R47, R67, R68, R72, R77, R131-R134, R137, R138, R140-R146, R262, R7_1, R7_2
1 1 10 1 3 1 29
RES-24, 5%, 805 RES-63.4, 1%, 603 RES-0, 5%, 603 RES-150, 1%, 603 RES-560, 5%, 603 RES-2.2K, 5%, 603 RES-4.7K, 5%, 603
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59
VISHAY WSL2512-R01-1 PANASONIC ERJ-3GSYJ681V PANASONIC ERJ-3GSYJ100V PANASONIC ERJ-3EKF39R2V PANASONIC ERJ-3GSYJ104V PANASONIC ERJ-3EKF2671V PANASONIC ERJ-3GSYJ221V PANASONIC ERJ-3GSYJ202V PANASONIC ERJ-3EKF3010V DIGI-KEY -- PGCT-ND PANASONIC ERJ-3GSYJ560V PANASONIC ERJ-3GSYJ4R7V PANASONIC ERJ-3GSYJ122V DIGI-KEY -- PGCT-ND PANASONIC ERJ-3GSYJ2R2V PANASONIC ERJ-3EKF82R5V PANASONIC ERJ-3EKF1300V PANASONIC ERJ-3EKF49R9V PANASONIC ERJ-3EKF3161V PANASONIC ERJ-3GSYJ101V DIGI-KEY -- PACT-ND
R14_2, R15_2, R5_2 R156, R161, R162 R159, R168, R179, R181, R194, R195, R198, R199, R6_2, R8_2 R16_1 R16_2, R8_1 R160 R171, R172, R186, R187, R189, R190, R192, R193 R174, R184, R197, R201, R3_2, R4_2 R18, R39, R56, R89 R185, R188, R191 R19 R1-R4, R117 R2_2 R263, R290, R291 R90, R91, R108-R110, R150 R35, R59, R75, R94, R96, R98, R104, R106 R36, R71, R78, R95, R97, R101, R105, R107
3 3 10 1 2 1 8 6 4 3 1 5 1 3
RES-0.01, 1%, 2512 RES-680, 5%, 603 RES-10, 5%, 603 RES-39.2, 1%, 603 RES-100K, 5%, 603 RES-2.67K, 1%, 603 RES-220, 5%, 603 RES-2.0K, 5%, 603 RES-301, 1%, 603 RES-4.7K, 5%, 603 RES-56, 5%, 603 RES-4.7, 5%, 603 RES-1.2K, 5%, 603 RES-56, 5%, 603 RES-2.2, 5%, 603 RES-82.5, 1%, 603 RES-130, 1%, 603 RES-49.9, 1%, 603 RES-3.16K, 1%, 603 RES-100, 5%, 603 RES-680, 5%, 805
R34, R57, R58, R60, R62, R65, R66, 13 8 8
R37, R127-R129, R164-R167, R169, 14 R297-R301 R5 R6, R8, R24, R26, R29, R44, R46, R69, R74, R88, R125, R149, R157 R61 1 1 13
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
33
RELEASED REFERENCE DESIGN PMC-2000185 ISSUE 2
PM5315 SPECTRA-2488
SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
NO. Manufacturer Part Number 60 61 PANASONIC ERJ-3GSYJ152V PANASONIC -- EXB-V8V472JV
Ref Des R99, R170, R182, R196, R200 RN3, RN3_1, RN4, RN4_1, RN5, RN5_1, RN6-RN8
Qty 5
Descriptions RES-1.5K, 5%, 603 RES_ARRAY_4_SMD-4.7K
RN1, RN16_1, RN1_1, RN2, RN2_1, 14
62
PANASONIC -- EXB-V8V100JV
RN10_1, RN11_1, RN12_1, RN13_1, 13 RN14_1, RN17_1, RN18_1, RN19_1, RN20_1, RN21_1, RN7_1, RN8_1, RN9_1
RES_ARRAY_4_SMD-10
63 64
PANASONIC -- EXB-V8V102JV PANASONIC -- EXB-V8V103JV
RN15_1, RN6_1 RN26_1, RN27_1, RN28_1, RN29_1, RN30_1, RN31_1, RN32_1, RN33_1, RN34_1
2
RES_ARRAY_4_SMD-1K RES_ARRAY_4_SMD-10K
RN22_1, RN23_1, RN24_1, RN25_1, 13
65 66 67 68 69 70 71
DIGI-KEY -- Y4ND DIGIKEY -- CKN4002-ND TEST POINT TEST POINT FAIRCHILD SEMI MM74HC08M MILL MAX 614-93-308-31-012 IPD CONVERTERS SIE501.8R
RN9, RN10 SW1 TP1-TP32 TP33-TP45 U1 U1_1 U1_2
2 1 32 13 1 1 1
RES_ARRAY_4_SMD-150 RIGHT ANGLE PCB MOUNT SPST PUSH BUTTOM, CK_TP11 TEST POINT THRU-HOLE PAD50CIR32D TEST POINT THRU-HOLE PAD60CIR36D IC QUAD 2 IN AND GATE SOIC14 NARROW BODY, VCC =3_3V SOCKET FOR PART# NM93CS66LEN, DIP8_SOCKET REGULATOR 5.0V TO 1.8V 6A, 100MV MAX RIPPLE CONVERTER, SIP_DC_DC_90 -1
72
MOTOROLA MC74HC244ADW
U10
1
IC OCTAL 3-STATE NONINVERTING BUFFER/LINE DRIVER/LINE RECEIVER SO20WB 3V
73 74 75 76
PMC SIERRA PM5310 PERICOM PI6C2502W TRIQUINT SEMICONDUCTO R TQ8106 PERICOM PI49FCT3805CQ
U11 U13, U15, U17, U19 U14, U16, U18, U20 U2
1 4 4 1
IC TELECOMBUS SERIALIZER, PBGA352 IC PHASE LOCKED LOOP CLOCK DRIVER, SOIC8 IC SONET/SDH TRANSCEIVER W/ CDR, TQFP100 IC 3.3V 2X1:5 CMOS CLOCK DRIVER SPEED-GRADE-C QSOP20
77
PLX TECHNOLOGY PCI9054AB50PI
U2_1
1
IC PCI-TO-LOCAL BUS, QFP176
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
34
RELEASED REFERENCE DESIGN PMC-2000185 ISSUE 2
PM5315 SPECTRA-2488
SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
NO. Manufacturer Part Number 78 79 80 LINEAR TECHNOLOGY LTC1643LCGN MC100ELT22 MAXIM MAX811TEUS-T
Ref Des U2_2 U23 U25
Qty 1 1 1
Descriptions IC CPCI HOT SWAP CONTROLLER, SSOP16 100ELT22_SOIC-BASE-V CC=5V IC 4 PIN UP VOLTAGE MONITOR WITH MANUAL RESET INPUT 3.08V SOT143
81 82 83
MOTOROLA SEMICONDUCTO R U3 MC100EPT23D LINEAR TECHNOLOGIES LT1117CST MAXIM MAX812REUS-T U3_2 U3_1
1 1 1
IC DUAL PECL/TTL TRNSLTR. 3.3V, SOIC8 REGULATOR ADJUSTABLE SOT223 800MA OUTPUT IC VOLTAGE MONITOR WITH MANUAL RESET INPUT 2.63V SOT143
84
PMC SIERRA PM5315
U4
1
IC SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 2488 MBIT/SEC, QUAD-STS 12STM4, SBGA520
85 86
TI SN74AHC1G08DCKR MOTOROLA MC100EL14DW
U5 U6
1 1
IC SINGLE 2-INPUT POSITIVE AND GATE, MO-203 MC100EL14_SOIC-BASE, IC LOW SKEW 1:5 CLOCK DISTRIBUTION CHIP, SO20WB
87 88
XILINX XC9572XL-10TQ100I SIEMENS V23826-H18-C363
U7 U8, U9, U12, U21
1 4
XC9572XL-TQ10- CPLD, 10NS, 3.3V, TQFP100 3.3V DC/DC SINGLE MODE 1300NM 622MBD 1X9 TRANSCEIVER, LCD-PMD-SOCK ET
89 90
CONNOR WINFIELD -- EE13-541 Y1 MMD COMPONENTS MB3100H- Y3 77.76MHZ
1 1
77.76 MHZ, LVPECL OSCILLATOR, 20 PPM, 5V OSC HCMOS/TTL HALF SIZE 8 PIN 77.76MHZ 100PPM
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
35
RELEASED REFERENCE DESIGN PMC-2000185 ISSUE 2
PM5315 SPECTRA-2488
SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
11
LAYOUT
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
36
RELEASED REFERENCE DESIGN PMC-2000185 ISSUE 2
PM5315 SPECTRA-2488
SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
NOTES
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
37
RELEASED REFERENCE DESIGN PMC-2000185 ISSUE 2
PM5315 SPECTRA-2488
SPECTRA-2488 WITH TBS QUAD OC-12 LINE CARD
CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com (604) 415-4533 http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 2001 PMC-Sierra, Inc. PMC-2000185 (R2) ref PMC-1990821 (R2) Issue date: March 2001
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