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87C196CA/87C196CB 16 MHz ADVANCED 16-BIT CHMOS MICROCONTROLLER WITH INTEGRATED CAN 2.0
Express
Advance Information Datasheet
Product Features
s s s s s s s s s s s s s s
-40C to +85C Ambient High Performance CHMOS 16-Bit CPU Up to 32 Kbytes of On-Chip EPROM Up to 1 Kbyte of On-Chip Register RAM Up to 512 Bytes of Additional RAM (Code RAM) Register-Register Architecture 8 Channel/10-Bit A/D with Sample/Hold 37 Prioritized Interrupts Up to Seven 8-Bit (56) I/O Ports Full Duplex Serial I/O Port Dedicated Baud Rate Generator Interprocessor Communication Slave Port Selectable Bus Timing Modes for Flexible Interfacing Oscillator Fail Detection Circuitry
s s s s s s s s s s s s s
High Speed Peripheral Transaction Server (PTS) Two Dedicated 16-Bit High-Speed Compare Registers 10 High Speed Capture/Compare (EPA) Full Duplex Synchronous Serial I/O Port (SSIO) Two Flexible 16-Bit Timer Counters Quadrature Counting Inputs Flexible 8-/16-Bit External Bus (Programmable) Programmable Bus (HLD/HLDA) 1.4 s 16 x 16 Multiply 2.4 s 32/16 Divide 68-Pin PLCC Package for 87C196CA 84-Pin PLCC Package for 87C196CB 16 MHz Operation
Notice: This document contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
Order No: 273151-001 January 1998
87C196CA/87C196CB - Express
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 87C196CA/87C196CB - Express may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation PO Box 5937 Denver CO 80217-9808 call 1-800-548-4725 Copyright (c) Intel Corporation 7/8/97 *Third-party brands and names are the property of their respective owners.
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Advance Information Datasheet
87C196CA/87C196CB - Express
Contents
1.0 2.0 3.0 4.0 5.0
5.1
INTRODUCTION.....................................................................................................1 BLOCK DIAGRAM .................................................................................................. 2 PROCESS INFORMATION ................................................................................. 3 PIN DESCRIPTIONS ............................................................................................. 6 ELECTRICAL CHARACTERISTICS ...............................................................11
DC CHARACTERISTICS .............................................................................. 11 5.1.1 8xC196CB Additional Bus Timing Modes ........................................ 14 5.1.1.1 MODE 3............................................................................... 14 5.1.1.2 MODE 0............................................................................... 14 AC CHARACTERISTICS .............................................................................. 14 5.2.1 Test Conditions ................................................................................ 14 5.2.2 87C196CA/87C196CB - Express Timings ....................................... 17 5.2.3 87C196CB Timings .......................................................................... 18 5.2.4 8xC196CB Timings .......................................................................... 19 5.2.5 8xC196CB AC Characteristics - Slave Port ..................................... 20 5.2.6 Explanation of AC Symbols.............................................................. 24 EPROM Specifications .................................................................................. 25 5.3.1 AC EPROM Programming Characteristics....................................... 25 5.3.2 EPROM Programming Waveforms .................................................. 26 AC CHARACTERISTICS - Serial Port - Shift Register Mode........................ 28 5.4.1 A/D Characteristics........................................................................... 28 5.4.1.1 A/D Converter Specification ................................................ 29 5.4.2 87C196CA Design Considerations................................................... 32 5.4.3 87C196CA ERRATA ........................................................................ 33 5.4.4 87C196CA DESIGN CONSIDERATIONS........................................ 33
5.2
5.3
5.4
6.0
DATASHEET REVISION HISTORY................................................................34
Advance Information Datasheet
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87C196CA/87C196CB - Express
Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 8XC196CB Block Diagram ...............................................................................2 The 87C196CA/87C196CB - Express Family Nomenclature...........................3 84-Pin PLCC TN87C196CB Diagram ..............................................................4 68-Pin PLCC TN87C196CA Diagram ..............................................................5 Chip Configuration Registers .........................................................................10 87C196CA ICC vs Frequency .........................................................................13 87C196CB ICC vs Frequency .........................................................................13 87C196CA/87C196CB - Express System Bus Timing ...................................17 87C196CA/87C196CB - Express Ready Timings (One Wait State) ..............18 87C196CB Buswidth Timings ........................................................................18 87C196CB HOLD#/HOLDA# Timings............................................................19 Slave Port Waveform - (SLPL = 0).................................................................20 Slave Port Waveform - (SLPL = 1).................................................................21 Synchronous Serial Port ................................................................................23 External Clock Drive Waveforms ...................................................................24 Input Test Conditions .....................................................................................24 Output Test Conditions ..................................................................................24 Slave Programming Mode Data Program Mode with Single Program Pulse .26 Slave Programming Mode in Word Dump or Data Verify Mode with Auto Increment .......................................................................................27 Slave Programming Mode Timing in Data Program Mode with Repeated Program Pulse and Auto Increment .......................................27 Waveform - Serial Port - Shift Register Mode 0 .............................................28 AD_TIME 1FAFH:Byte ...................................................................................29
Tables
1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Device Overview ..............................................................................................1 Thermal Characteristics ...................................................................................3 Pin Descriptions ...............................................................................................6 87C196CB Memory Map..................................................................................8 87C196CA Memory Map..................................................................................9 DC Characteristics (Under Listed Operating Conditions)...............................11 AC Characteristics the 87C196CA/87C196CB - Express Meets ...................14 AC Characteristics System Must Meet to Work with 87C196CA/87C196CB - Express ...........................................................16 8xC196CB HOLD#/HOLDA# Timings (Over Specified Operation Conditions) ..........................................................19 Slave Port Timing - (SLPL = 0, 1, 2, 3) ..........................................................20 Slave Port Timing - (SLPL = 1, 2, 3) ..............................................................21 Normal Master/Slave Operation .....................................................................22 Handshake Operation ....................................................................................22 External Clock Drive.......................................................................................23 Explanation of AC Symbols............................................................................25 AC EPROM Programming Characteristics.....................................................25 DC EPROM Programming Characteristics ....................................................26 Serial Port Timing - Shift Register Mode ........................................................28 10-Bit Mode A/D Operating Conditions ..........................................................29 10-Bit Mode A/D Characteristics (Using Above Operating Conditions) .........30 8-Bit Mode A/D Operating Conditions ............................................................30 8-Bit Mode A/D Characteristics (Using Above Operating Conditions) ...........31
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Advance Information Datasheet
87C196CA/87C196CB - Express
1.0
INTRODUCTION
The 87C196CA/87C196CB - Express are members of the MCS(R) 96 microcontroller family. These devices are based upon the MCS 96 Kx/Jx microcontroller product families with enhancements ideal for automotive and industrial applications. The CA/CB are the first devices in the Kx family to support networking through the integration of the CAN 2.0 (Controller Area Network) peripheral on-chip. The 87C196CB offers the highest memory density of the MCS 96 microcontroller family, with 56K of on-chip EPROM, 1.5K of on-chip register RAM, and 512 bytes of additional RAM (Code RAM). In addition, the 87C196CB provides up to 16 Mbyte of Linear Address Space. The 87C196CA is a sub-set of the CB, offering 32K of on-chip EPROM, up to 1.0 K of on-chip register.
Table 1. Device Overview
Device 87C196CB 87C196CA Pins/Pac kage 84-Pin PLCC 68-Pin PLCC EPROM 56K 32K Reg RAM 1.5K 1.0K Code RAM 512b 256b I/O 56 38 EPA 10 6 SIO Y Y SSIO Y Y CAN Y Y A/D 8 6 Addr Space 1 Mbyte 64 Kbyte
ADVANCE INFORMATION Datasheet
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87C196CA/87C196CB - Express
2.0
BLOCK DIAGRAM
The MCS 96 microcontroller family members are all high-performance microcontrollers with a 16-bit CPU. The 87C196CB is composed of the high-speed (16 MHz) macrocore with up to 16 Mbyte linear address space, 56 Kbytes of program EPROM, up to 1.5 Kbytes of register RAM, and up to 512 bytes of code RAM (16-bit addressing modes) with the ability to execute from this RAM space. It supports the high-speed, serial communications protocol CAN 2.0, with 15 message objects of 8 bytes data length, an 8-channel, 10-bit / 3 LSB analog to digital converter with programmable S/H times, and conversion times k 20 ms at 16 MHz. It has an asynchronous/synchronous serial I/O port (SIO) with a dedicated 16-bit baud rate generator, an additional synchronous serial I/O port (SSIO) with full duplex master/slave transceivers, a flexible timer/counter structure with prescaler, cascading, and quadrature capabilities. There are ten modularized, multiplexed, high-speed I/O for capture and compare (called Event Processor Array) with 200 ns resolution and double buffered inputs, and a sophisticated prioritized interrupt structure with programmable Peripheral Transaction Server (PTS) implementing several channel modes, including single/burst block transfers from any memory location to any memory location, a PWM and PWM toggle mode to be used in conjunction with the EPA, and an A/D scan mode. Note: This is an advance information data sheet. The AC and DC parameters contained within this data sheet may change after full express temperature characterization of the device has been performed. Contact your local sales office before finalizing the timing and DC characteristics of a design to verify you have the latest information.
Figure 1. 8XC196CB Block Diagram
VREF ANGND
A/D Converter
CPU
1.5K Byte Register File ALU
16
Interrupt Controller
56K On-chip EPROM (optional) 512 Bytes Internal RAM
Port 5 Control Signals
S/H
Microcode Engine
8
Peripheral Transaction Server
Memory Controller Queue Port 3 AD0-7 Port 4 AD8-15
MUX
16
Port 0
Sync Serial Port and Baud Gen
Watchdog Timer Timer 1 Timer 2 Event Processor Array
Serial Port
Baud Rate Gen
EPORT A16-23
Port 6
Port 1
Port 2
CAN 2.0
RXCAN TXCAN
A/D Port 0
Port 6 SSIO
Port 1 EPA
Port 2 / Hold Control
A4546-01
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ADVANCE INFORMATION Datasheet
87C196CA/87C196CB - Express
3.0
PROCESS INFORMATION
These devices are manufactured on P629.5, a CHMOS III-E process. Additional process and reliability information is available in Intel's Components Quality and Reliability Handbook, Order Number 210997. All thermal impedance data is approximate for static air conditions at 1 W of power dissipation. Values change depending on operation conditions and applications. See the Intel Packaging Handbook (order number 240800) for a description of Intel's thermal impedance test methodology.
Figure 2. The 87C196CA/87C196CB - Express Family Nomenclature
T N 8 7 C 1 9 6 C A/B
Product Designation Product Family CHMOS Technology Program Memory Options: 7 = EPROM, OTP 0 = CPU Package Type Options: N = PLCC (plastic leaded chip carrier) Temperature and Burn-in Options: T = -40C to + 85C ambient with Intel Standard Burn-in
A4582-01
Table 1. Thermal Characteristics
Device and Package TN87C196CB (84-Lead PLCC Package) TN87C196CA (68-Lead PLCC Package) JA 35C/W 36.5C/W JC 11C/W 10C/W
NOTES: 1. JA = Thermal resistance between junction and the surrounding environment (ambient) measurements are taken 1 ft. away from case in air flow environment. JV = Thermal resistance between junction and package face (case). 2. All values of JA and JC may fluctuate depending on the environment (with or without airflow, and how much airflow) and device power dissipation at temperature of operation. Typical variations are 2C/W. 3. Values listed are at a maximum power dissipation of 1 W.
ADVANCE INFORMATION Datasheet
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87C196CA/87C196CB - Express
Figure 3. 84-Pin PLCC TN87C196CB Diagram
PS.7 / BUSW EP3.1 / A17 EP3.0 / A16 P4.7 / AD15 P4.6 / AD14 P4.5 / AD13 P4.4 / AD12 P4.3 / AD11 P4.2 / AD10 P4.1 / AD9 P4.0 / AD8 VSS1 VCC P3.7 / AD7 P3.6 / AD6 P3.5 / AD5 P3.4 / AD4 P3.3 / AD3 P3.2 / AD2 P3.1 / AD1 EP3.2 / A18
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
P5.2 / WR# P5.5 /BHE# P5.3 / RD# VPP P5.0 / ALE P5.1 / INST P5.6 / READY P5.4 / SLPINT EP3.3 / A19 VCC VSS1 VSS RXCAN TXCAN XTAL1 XTAL2 P6.7 / SD1 P6.6 / SC1 P6.5 / SD0 P6.4 / SC0 VCC
TN87C196CB
84-Lead PLCC View of component as mounted on PC board
74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54
PLLEN P6.3 / T1DIR P6.2 / T1CLK P6.1 / EPA9 P6.0 / EPA8 P1.0 / EPA0 P1.1 / EPA1 P1.2 / EPA2 P1.3 / EPA3 P1.4 / EPA4 P1.5 / EPA5 P1.6 / EPA6 P1.7 / EPA7 VSS1 VCC VREF AGND P0.7 / ACH7 P0.6 / ACH6 P0.5 / ACH5 P0.4 / ACH4
P3.0 / AD0 RESET NMI EA# VSS1 VCC VSS P2.0 / TXD P2.1 / RXD P2.2 / EXTINT P2.3 / INTB# P2.4 / INTINTOUT# P2.5 / HLD# P2.6 / HLDA# P2.7 / CLKOUT VCC VSS1 P0.0 / ACH0 P0.1 / ACH1 P0.2 / ACH2 P0.3 / ACH3
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
A4581-01
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ADVANCE INFORMATION Datasheet
87C196CA/87C196CB - Express
Figure 4. 68-Pin PLCC TN87C196CA Diagram
NC AD15 / P4.7 AD14 / P4.6 AD13 / P4.5 AD12 / P4.4 AD11 / P4.3 AD10 / P4.2 AD9 / P4.1 AD8 / P4.0 AD7 / P3.7 AD6 / P3.6 AD5 / P3.5 AD4 / P3.4 AD3 / P3.3 AD2 / P3.2 NC NC
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
WR# / P5.2 WRH# / P5.5 RD# / P5.3 VPP VSS ALE / P5.0 READY / P5.6 P5.4 VSS1 XTAL1 XTAL2 RXCAN TXCAN SD1 / P6.7 SC1 / P6.6 SD0 / P6.5 SC0 / P6.4
TN87C196CA 68 - ld PLCC View of component as mounted on PC board
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
NC NC VCC EPA9 / P6.1 EPA8 / P6.0 EPA0 / P1.0 / T2CLK EPA1 / P1.1 EPA2 / P1.2 / T2DIR EPA3 / P1.3 NC VREF ANGND ACH7 / P0.7 ACH6 / P0.6 ACH5 / P0.5 ACH4 / P0.4 NC
P3.1 / AD1 P3.0 / AD0 RESET# NMI EA# VSS1 VCC VSS TXD / P2.0 RXD / P2.1 EXTINT / P2.2 P2.4 P2.6 CLKOUT / P2.7 ACH2 / P0.2 ACH3 / P0.3 NC
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
A4583-01
ADVANCE INFORMATION Datasheet
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87C196CA/87C196CB - Express
4.0
PIN DESCRIPTIONS
Table 2. Pin Descriptions (Sheet 1 of 3)
Name VCC V SS, VSS1 VREF Main supply voltage (+5 V). Digital circuit ground (0 V). There are seven VSS pins CB (4 on CA), all of which MUST be connected to a single ground plane. Reference for the A/D converter (+5 V). VREF is also the supply voltage to the analog portion of the A/D converter and the logic used to read Port 0. Must be connected for A/D and Port 0 to function. Programming voltage for the EPROM parts. It should be +12.5 V for programming. It is also the timing pin for the return from powerdown circuit. Connect this pin with a 1 F capacitor to VSS and a 1 M resistor to VCC . If this function is not used, VPP may be tied to VCC. Reference ground for the A/D converter. Must be held at nominally the same potential as VSS. Input of the oscillator inverter and the internal clock generator. Output of the oscillator inverter. Reset input to the chip. Input low for at least 16 state times resets the chip. The subsequent low-to-high transition resynchronizes CLKOUT and commences a 10-state time sequence in which the PSW is cleared, bytes are read from 2018H, 201AH and 201CH (if enabled) loading the CCBs, and a jump to location 2080H is executed. Input high for normal operation. RESET# has an internal pullup. A positive transition causes a non-maskable interrupt vector through memory location 203EH. If not used, this pin should be tied to VSS. May be used by Intel Evaluation boards. Input for memory select (External Access). EA# equal to a high causes memory accesses to locations 0FF2000H through 0FFFFFH to be directed to on-chip EPROM/ROM. EA# equal to a low causes accesses to these locations to be directed to off- chip memory. EA# = +12.5 V causes execution to begin in the Programming Mode. EA# latched at reset. Selects between PLL mode or PLL bypass mode. This pin must be either tied high or low. PLLEN pin = 0, bypass PLL mode. PLLEN pin = 1, places a 4x PLL at the input of the crystal oscillator. Allows for a low frequency crystal to drive the device (i.e., 5 MHz = 16 MHz operation). Dual-function I/O ports that have a system function as Synchronous Serial I/O. Two pins are clocks and two pins are data, providing full duplex capability. Also, LSIO when not used as SSIO. Dual-function I/O pin. Primary function is that of a bidirectional I/O pin, however, it may also be used as a TIMER1 Direction input. The TIMER1 increments when this pin is high and decrements when this pin is low. Dual-function I/O pin. Primary function is that of a bidirectional I/O pin, however may also be used as a TIMER1 Clock input. The TIMER1 increments or decrements on both positive and negative edges of this pin. Dual-function I/O port pins. Primary function is that of bidirectional I/O. System function is that of High Speed capture and compare. Input for bus width selection. If CCR bit 1 is a one and CCR1 bit 2 is a one, this pin dynamically controls the Buswidth of the bus cycle in progress. If BUSWIDTH is low, an 8-bit cycle occurs, if BUSWIDTH is high, a 16-bit cycle occurs. If CCR bit 1 is "0" and CCR1 bit 2 is "1", all bus cycles are 8-bit, if CCR bit 1 is "1" and CCR1 bit 2 is "0", all bus cycles are 16-bit. CCR bit 1 = "0" and CCR1 bit 2 = "0" is illegal. Also an LSIO pin when not used as BUSWIDTH. Description
V PP
ANGND XTAL1 XTAL2
RESET#
NMI
EA#
PLLEN (196CB only)
P6.4-6.7/SSIO
P6.3/T1DIR (CB only) P6.2/T1CLK (CB only) P6.0-6.1/EPA8-9
P5.7/BUSWIDTH (CB only)
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87C196CA/87C196CB - Express
Table 2. Pin Descriptions (Sheet 2 of 3)
Name Description Ready input to lengthen external memory cycles, for interfacing with slow or dynamic memory, or for bus sharing. If the pin is high, CPU operation continues in a normal manner. If the pin is low prior to the falling edge of CLKOUT, the memory controller goes into a wait state mode until the next positive transition in CLKOUT occurs with READY high. When external memory is not used, READY has no effect. The max number of wait states inserted into the bus cycle is controlled by the CCR/CCR1. Also an LSIO if READY is not selected. Byte High Enable or Write High output, as selected by the CCR. BHE# = 0 selects the bank of memory that is connected to the high byte of the data bus. A0 = 0 selects the bank of memory that is connected to the low byte. Thus accesses to a 16-bit wide memory can be to the low byte only (A0 = 0, BHE# = 1), to the high byte only (A0 = 1, BHE# = 0) or both bytes (A0 = 0, BHE# = 0). If the WRH# function is selected, the pin goes low if the bus cycle is writing to an odd memory location. BHE#/WRH# is only valid during 16-bit external. Also an LSIO pin when not BHE/WRH#. Dual-function I/O pin. As a bidirectional port pin or as a system function. The system function is a Slave Port Interrupt Output Pin (on CA, bidirectional port pin only). Read signal output to external memory. RD# is active only during external memory reads or LSIO when not used as RD#. Write and Write Low output to external memory, as selected by the CCR, WR# goes low for every external write, while WRL# goes low only for external writes where an even byte is being written. WR#/WRL# is active during external memory writes. Also an LSIO pin when not used as WR#/WRL#. Output high during an external memory read indicates the read is an instruction fetch. INST is valid throughout the bus cycle. INST is active only during external memory fetches, during internal EPROM fetches INST is held low. Also LSIO when not INST. Address Latch Enable or Address Valid output, as selected by CCR. Both pin options provide a latch to demultiplex the address from the address/data bus. When the pin is ADV#, it goes inactive (high) at the end of the bus cycle. ADV# can be used as a chip select for external memory. ALE/ADV# is active only during external memory accesses. Also LSIO when not used as ALE. 8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the multiplexed address/data bus which has strong internal pullups. Output of the internal clock generator. The frequency is the oscillator frequency. CLKOUT has a 50% duty cycle. Also LSIO pin when not used as CLKOUT. Bus Hold Acknowledge. Active-low output indicates that the bus controller has relinquished control of the bus. Occurs in response to an external device asserting the HLD# signal. Also LSIO when not used as HLDA#. Bus Hold. Active-low signal indicates that an external device is requesting control of the bus. Also LSIO when not used as HLD#. Interrupt Output. This active-low output indicates that a pending interrupt requires use of the external bus. Also LSIO when not used as INTOUT#. Bus Request. This active-low output signal is asserted during a HOLD cycle when the bus controller has a pending external memory cycle. Also LSIO when not used as BREQ#. A positive transition on this pin causes a maskable interrupt vector through memory location 203CH. Also LSIO when not used as EXTINT. Receive data input pin for the Serial I/O port. Also LSIO if not used as RXD. Transmit data output pin for the Serial I/O port. Also LSIO if not used as TXD. Dual-function I/O port pins. Primary function is that of bidirectional I/O. System function is that of High Speed capture and compare. EPA0 and EPA2 have another function of T2CLK and T2DIR of the TIMER2 timer/counter.
P5.6/READY
P5.5/BHE#/WRH#
P5.4/SLPINT P5.3/RD#
P5.2/WR#/WRL#
P5.1/INST (CB only)
P5.0/ALE/ADV#
PORT3 and 4 P2.7/CLKOUT
P2.6/HLDA# P2.5/HLDY (CB only) P2.4/INTOUT# P2.3/BREQ# (CB only) P2.2/EXTINT P2.1/RXD P2.0/TXD PORT 1/EPA0-7
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87C196CA/87C196CB - Express
Table 2. Pin Descriptions (Sheet 3 of 3)
Name PORT 0/ACH0-7 Description 8-bit high impedance input-only port. These pins can be used as digital inputs and/or as analog inputs to the on-chip A/D converter. These pins are also used as inputs to EPROM parts to select the Programming Mode. 8-bit bidirectional standard and I/O Port. These bits are shared with the extended address bus, A16-A19 for CB PLCC. Pin function is selected on a per pin basis. Push-pull output to the CAN bus line. High impedance input-only from the CAN bus line.
EPORT (CB only) TXCAN RXCAN
Table 3. 87C196CB Memory Map
Address FFFFFFH FF2080H FF207FH FF2000H FF1FFFH FF0600H FF05FFH FF0400H FF03FFH FF0100H FF00FFH FF0000H FEFFFFH 0F0000H 0EFFFFH 010000H 00FFFFH 002080H 00207FH 002000H 001FFFH 001FE0H 001FDFH 001F00H 001EFFH 001E00H 001DFFH 001C00H 001BFFH 000600H Description Program Memory - Internal EPROM or External Memory (Determined by EA# Pin) Special Purpose Memory - Internal EPROM or External Memory (Determined by EA# Pin) External Memory Internal RAM (Identically Mapped into 00400H005FFH) External Memory Reserved for ICE Notes
Overlaid Memory (External) 900 Kbytes External Memory External Memory or Remapped OTPROM (Program Memory) External Memory or Remapped OTPROM (Special Purpose Memory) Memory Mapped Special Function Registers (SFR's) Internal Peripheral Special Function Registers (SFR's) Internal CAN Peripheral Memory Internal Register RAM External Memory
(5)
(1) (1,3)
(5) (5)
NOTES: 1. These areas are mapped internal EPROM if the REMAP bit (CCB2.2) is set and EA# = 5 V. Otherwise they are external memory. 2. Code executed in locations 0000H to 003FFH is forced external. 3. Reserved memory locations must contain 0FFH unless noted. 4. Reserved SFR bit locations must be written with 0. 5. Refer to 8XC196CB User's Guide for SFR, CAN and Paging Descriptions.
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Table 3. 87C196CB Memory Map
Address 0005FFH 000400H 0003FFH 000100H 0000FFH 000018H 000017H 000000H Description Internal RAM (Code RAM) (Address with Indirect or Indexed Modes) Register RAM Upper Register File (Address with Indirect or Indexed Modes or through Windows.) Register RAM Lower Register File. (Address with Direct, Indirect, or Indexed Modes.) CPU SFR's Notes
(2) (2) (4)
NOTES: 1. These areas are mapped internal EPROM if the REMAP bit (CCB2.2) is set and EA# = 5 V. Otherwise they are external memory. 2. Code executed in locations 0000H to 003FFH is forced external. 3. Reserved memory locations must contain 0FFH unless noted. 4. Reserved SFR bit locations must be written with 0. 5. Refer to 8XC196CB User's Guide for SFR, CAN and Paging Descriptions.
Table 4. 87C196CA Memory Map
Address 00FFFFH 00A000H 009FFFH 002080H 00207FH 002000H 001FFFH 001FE0H 001FDFH 001F00H 001EFFH 001E00H 001DFFH 000500H 0004FFH 000400H 0003FFH 000100H 0000FFH 000018H 000017H 000000H Internal Register RAM - Upper Register File (Address with Indirect or Indexed Modes or through Windows) Internal Register RAM - Lower Register File (Address with Direct, Indirect, or Indexed Modes. CPU Special Function Registers (SFR's) (2) (2) (2,3) External Memory Internal EPROM (32 Kbytes) (Determined by EA# Pin) Reserved Memory (Internal EPROM or External Memory) Memory Mapped Special Function Registers (SFR's) Internal Special Function Registers (SFR's) Internal CAN Peripheral Memory External Memory (Address with Indirect or Indexed Modes) Internal RAM (Code RAM) Description Notes
(1)
NOTES: 1. Refer to 8XC196KX Family User's Guide for SFR Description. 2. Code executed in locations 0000H to 003FFH is forced external. 3. Reserved SFR bit locations must be written with 0.
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87C196CA/87C196CB - Express
Figure 5. Chip Configuration Registers
CCB (2018H: Byte) 0 1 2 3 4 5 6 7 PD BW0 WR ALE IRC0 IRC1 LOC0 LOC1 = = = = = = = = "1" Enables Powerdown See Table CCB1 (201AH: Byte) 0 1 CCR2 IRC2 BW1 WDE 1 0 MEMSEL0 MEMSEL1 = = = = = = = = "1" Fetch CCB2 ("0" for CA) See Table See Table "0" = Always Enabled Reserved Must Be "1" Reserved Must Be "1" See Table See Table
"1" = WR#/BHE - "0" = WRL#/WRH# 2 "1" = ALE - "0" = ADV 3 4 5 6 7
} See Table } See Table
CCB2 (201CH: Byte) (CB Only) 0 1 2 3 4 5 6 7 0 MODE16 REMAP 1 1 1 1 1 = = = = = = = =
Reserved Must Be "0" Select 16-Bit or 24-Bit Mode "0"-Select EPROM/CODERAM in Segment 0FFH only "1"-Select Both Segment 0FFH and Segment 00H Reserved Must Be "1"
}
Reserved Must Be "1" Reserved Must Be "1" Reserved Must Be "1" Reserved Must Be "1"
LOC1 0 0 1 1
LOC0 0 1 0 1
Function Read and Write Protected Write Protected Only Read Protected Only No Protection
IRC2 0 1 1 1 1
IRC1 0 0 0 1 1
IRC0 0 0 1 0 1
Max Wait States Zero Wait States 1 Wait State 2 Wait States 3 Wait States INFINITE
MSEL1 0 0 1 1
MSEL0 0 1 0 1
"CB" Bus Timing Mode Mode 0 (1-Wait KR) Mode 1 Mode 2 Mode 3 (KR)
BW1 0 0 1 1
BW0 0 1 0 1
Bus Width ILLEGAL 16-Bit Only 8-Bit Only BW Pin Controlled
Mode 0 (1-Wait KR): Mode 3 (KR):
Designed to be similar to the 87C196KR bus timing with 1 automatic wait state. See AC Timings section for actual timings data. Designed to be similar to the 87C196KR bus timing. See AC Timings section for actual timings data.
10
ADVANCE INFORMATION Datasheet
87C196CA/87C196CB - Express
5.0
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS* Storage Temperature -60C to +150C Voltage from VPP or EA# to VSS or ANGND................................ -0.5 V to +13.0 V Voltage from any other pin to VSS or ANGND................................ -0.5 V to +7.0 V This includes VPP on ROM and CPU devices. Power Dissipation ................................. 0.5 W OPERATING CONDITIONS TA (Ambient Temperature Under Bias).....-40C to +85C V CC (Digital Supply Voltage) V REF (Analog Supply Voltage) 4.5 V to 5.5 V 4.5 V to 5.5 V
NOTICE: This is a production data sheet. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
*WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
FOSC (Oscillator Frequency) .................... 4 MHz to 16 MHz NOTE: ANGND and VSS should be nominally at the same potential.
5.1
DC CHARACTERISTICS
Table 5. DC Characteristics (Under Listed Operating Conditions) (Sheet 1 of 2)
Symbol Parameter VCC Supply Current (-40C to +85C Ambient) CA CB A/D Reference Supply Current Idle Mode Current IIDLE IPD VIL VIH CA CB Powerdown Mode Current Input Low Voltage (All Pins) Input High Voltage -0.5 0.7 VCC 50 40 35 TBD 0.3 VCC VCC + 0.5 mA 90 100 5 Min Typ Max Units Test Conditions XTAL1 = 16 MHz mA VCC = VPP = VREF= 5.5 V (While Device in Reset) mA XTAL1 = 16 MHz VCC = VPP = VREF = 5.5 V VCC = VPP = VREF = 5.5 V (Notes 6,9) For PORT0 (Note 8) For PORT0 (Note 8)
ICC
IREF
A V V
NOTES: 1. All BD (bidirectional) pins except INST and CLKOUT. INST and CLKOUT are excluded due to not being weakly pulled high in reset. BD pins include Port1, Port2, Port3, Port4, Port5 and Port6 except SPLINT (P5.4) and HLDA (P2.6). 2. Standard Input pins include XTAL1, EA#, RESET and Port 1/2/5/6 when setup as inputs. 3. All Bidirectional I/O pins when configured as Outputs (Push/Pull). 4. Device is Static and should operate below 1 Hz, but only tested down to 4 MHz. 5. Maximum IOL /IOH currents per pin are characterized and published at a later date. 6. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room temperature and VREF = VCC = 5 V. 7. Violating these specifications in reset may cause the device to enter test mode (P5.4 and P2.6). 8. When P0 is used as analog inputs, refer to A/D specifications for this characteristic. 9. For temperatures < 100C typical is 10 A.
ADVANCE INFORMATION Datasheet
11
87C196CA/87C196CB - Express
Table 5. DC Characteristics (Under Listed Operating Conditions) (Sheet 2 of 2)
Symbol V OL Parameter Output Low Voltage (Outputs Configured as Complementary) Output High Voltage (Output Configured as Complementary) Input Leakage Current (Standard Inputs) Input Leakage Current (Port 0) SPLINT (P5.4) and HLDA (P2.6) Output High Voltage in RESET Output High Voltage in RESET Pin Capacitance (Any Pin to VSS) Reset Pull-up Resistor (CB) Reset Pull-up Resistor (CA) Weak Pull-up Resistance (Approximate) 65 K 6K 9 150 K VCC - 1 10 180 K 65 K VCC - 0.3 VCC - 0.7 VCC - 1.5 10 CA 1.5 CB 1 2 Min Typ Max 0.3 0.45 1.5 Units V Test Conditions IOL = 200 A (Note 3,5) IOL = 3.2 mA IOL = 7 mA IOH = -200 A (Note 3,5) IOH = -3.2 mA IOH = -7 mA VSS < VIN < VCC V SS < VIN < VREF IOH = 0.8 mA (Note 7) IOH = -15 A (Note 1) FTEST = 1 MHz (Note 6) For CB For CA (Note 6)
V OH ILI ILI1 V OH1 V OH2 CS RRST RRST RWPU
V A A V V pF
NOTES: 1. All BD (bidirectional) pins except INST and CLKOUT. INST and CLKOUT are excluded due to not being weakly pulled high in reset. BD pins include Port1, Port2, Port3, Port4, Port5 and Port6 except SPLINT (P5.4) and HLDA (P2.6). 2. Standard Input pins include XTAL1, EA#, RESET and Port 1/2/5/6 when setup as inputs. 3. All Bidirectional I/O pins when configured as Outputs (Push/Pull). 4. Device is Static and should operate below 1 Hz, but only tested down to 4 MHz. 5. Maximum IOL /IOH currents per pin are characterized and published at a later date. 6. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room temperature and VREF = VCC = 5 V. 7. Violating these specifications in reset may cause the device to enter test mode (P5.4 and P2.6). 8. When P0 is used as analog inputs, refer to A/D specifications for this characteristic. 9. For temperatures < 100C typical is 10 A.
12
ADVANCE INFORMATION Datasheet
87C196CA/87C196CB - Express
Figure 6. 87C196CA ICC vs Frequency
90 80 70 60
ICC = [mA]
Active ICC Max = 90 mA Active ICC = 75 mA
50 40 30 20 10 0 2 8 14 20
A5862-01
Idle Max = 40 mA Idle ICC = 32 mA
Figure 7. 87C196CB ICC vs Frequency
100 90
Active ICC Max = 100 mA Active ICC = 83 mA
80 70
ICC = [mA]
60 50 40
Idle Max = 35 mA
30 20 10 0 2 8 14
Idle ICC = 28 mA
20
A5863-01
ADVANCE INFORMATION Datasheet
13
87C196CA/87C196CB - Express
5.1.1
8xC196CB Additional Bus Timing Modes
The 8xC196CB device has two bus timing modes for external memory interfacing.
5.1.1.1
MODE 3
Mode 3 is the standard timing mode. Use this mode for systems that emulate the 8xC196KR bus timings.
5.1.1.2
MODE 0
Mode 0 is the standard timing mode, but 1 (minimum) wait state is always inserted in external bus cycles.
5.2
5.2.1
AC CHARACTERISTICS
Test Conditions * Capacitive load on all pins = 100 pF * Rise and Fall Times = 10 ns
Table 6. AC Characteristics the 87C196CA/87C196CB - Express Meets (Sheet 1 of 2)
Symbol FXTAL TOSC TXHCH TOFD TCLCL TCHCL TCLLH TLLCH TLHLH TLHLL TAVLL TLLAX TLLRL Parameter
Frequency on XTAL1 XTAL1 Period (1/FXTAL) XTAL1 High to CLKOUT High or Low Clock Failure to Reset Pulled Low CLKOUT Period CLKOUT High Period CLKOUT Low to ALE/ADV High ALE/ADV# Lowe to CLKOUT High ALE/ADV# Cycle Time ALE/ADV# High Time Address Valid to ALE Low Address Hold after ALE/ADV# Low ALE/ADV# Low to RD# Low
Min 4 62.5 + 20 4 2TOSC TOSC-10 -15 -20 4TOSC TOSC-10 TOSC-15 TOSC-40 TOSC-30
Max 16 250 110 40
Units MHz (1) ns ns
s (6) ns
TOSC+15 + 10 + 15
ns ns ns ns (5)
TOSC+10
ns ns ns ns
NOTES: 1. Testing performed at 4 MHz, however, the device is static by design and typically operates below 1 Hz. 2. Typical specifications, not guaranteed. 3. Assuming back-to-back bus cycles. 4. 8-bit bus only. 5. If wait states are used, add 2TOSC x n = number of wait states. If mode 0 (1 automatic wait state added) operation is selected, add 2TOSC to specification. 6. TOFD is the time for the oscillator fail detect circuit (OFD) to react to a clock failure. The OFD circuitry is enabled by programming the UPROM location 0778H with the value 0004H. Programming the CDE bit enables oscillator fail detection.
14
ADVANCE INFORMATION Datasheet
87C196CA/87C196CB - Express
Table 6. AC Characteristics the 87C196CA/87C196CB - Express Meets (Sheet 2 of 2)
Symbol Parameter
RD Low to CLKOUT Low
Min
Max
Units
TRLCL TRLRH TRHLH TRLAZ TLLWL TCLWL TQVWH TCHWH TWLWH TWHQX TWHLH TWHBX TWHAX TRHBX TRHAX
Data Hold after WR# High WR# High to ALE/ADV# High BHE#, INST Hold after WR# High AD8-15 Hold after WR# High BHE#, INST Hold after RD# High AD8-15 Hold after RD# High RD# Low Period RD# High to ALE/ADV# High RD# Low to Address Float ALE/ADV# Low to WR# Low CLKOUT Low to WR# Low Data Valid before WR# High CLKOUT High to WR# High WR# Low Period
CA CB
+4 -8 TOSC-10 TOSC
+ 30 + 20
ns
ns (5)
TOSC+25 5
ns (3) ns ns
TOSC-10 -5 TOSC-23 -10 TOSC-30 TOSC-20 TOSC-25 TOSC-10 TOSC-10 TOSC-30 TOSC-10 TOSC-30 TOSC+15 + 15 + 25
ns ns ns ns (5)
CA CB
ns ns (3) ns ns (4) ns ns (4)
NOTES: 1. Testing performed at 4 MHz, however, the device is static by design and typically operates below 1 Hz. 2. Typical specifications, not guaranteed. 3. Assuming back-to-back bus cycles. 4. 8-bit bus only. 5. If wait states are used, add 2TOSC x n = number of wait states. If mode 0 (1 automatic wait state added) operation is selected, add 2TOSC to specification. 6. TOFD is the time for the oscillator fail detect circuit (OFD) to react to a clock failure. The OFD circuitry is enabled by programming the UPROM location 0778H with the value 0004H. Programming the CDE bit enables oscillator fail detection.
ADVANCE INFORMATION Datasheet
15
87C196CA/87C196CB - Express
Table 7. AC Characteristics System Must Meet to Work with 87C196CA/87C196CB - Express
Symbol TAVYV TLLYV TYLYH TCLYX TAVGV TLLGV TCLGX TAVDV TRLDV TCLDV TRHDZ TRHDX
CLKOUT Low to Input Data Valid End of RD# to INput Data Valid Data Hold after RD# High
Parameter
Address Valid to Ready Setup ALE Low to Ready Setup Non Ready Time READY Hold after CLKOUT Low Address Valid to BUSWIDTH Setup ALE Low to BUSWIDTH Setup BUSWIDTH Hold after CLKOUT Low Address Valid to Input Data Valid RD# Active to Input Data Value
Min
Max 20 250 No Upper Limit
Units ns (3) ns (3) ns
0
TOSC-30 TOSC-75 TOSC-60
ns (1)
ns (2,3) ns (2,3) ns
0 3TOSC -55 TOSC-22 TOSC-30 3TOSC -50
ns (2)
CA CB
ns (2)
ns ns
0
ns
NOTES: 1. Testing performed at 4 MHz, however, the device is static by design and typically operates below 1 Hz. 2. Typical specifications, not guaranteed. 3. Assuming back-to-back bus cycles. 4. 8-bit bus only. 5. If wait states are used, add 2TOSC x n = number of wait states. If mode 0 (1 automatic wait state added) operation is selected, add 2TOSC to specification. 6. TOFD is the time for the oscillator fail detect circuit (OFD) to react to a clock failure. The OFD circuitry is enabled by programming the UPROM location 0778H with the value 0004H. Programming the CDE bit enables oscillator fail detection.
16
ADVANCE INFORMATION Datasheet
87C196CA/87C196CB - Express
5.2.2
87C196CA/87C196CB - Express Timings
Figure 8. 87C196CA/87C196CB - Express System Bus Timing
TOSC XTAL1 TCLCL CLKOUT TCLLH ALE / ADV# TLHLL RD# TRLAZ TAVLL BUS READ TLLAX TRHDZ TRHDX Data In TLLRL TRLRH TRLDV TRHLH TLLCH TLHLH TXHCH
Address Out A0 - A15 TAVDV TLLWL TWLWH
WR# TQVWH BUS WRITE Address Out Data Out TWHBX or TRHBX BHE#, INST BHE, INST Valid TWHAX or TRHAX AD8-AD15 Address Out AD8-AD15 Valid 8-Bit Bus Mode TWHQX
If mode 0 operation is selected, add 2 TOSC to this time.
A5872-01
ADVANCE INFORMATION Datasheet
17
87C196CA/87C196CB - Express
Figure 9. 87C196CA/87C196CB - Express Ready Timings (One Wait State)
TOSC XTAL1 TXHCH CLKOUT TCLLH ALE TLLYV READY TAVYV RD# TLLCH TCLYX
(max)
TCLCL
TCLYX
(min)
TRLRH + 2 TOSC TAVDV + 2 TOSC TRHDX
Data In
BUS READ
Address Out
TWLWH + 2 TOSC
WR#
TQVWH + 2 TOSC
BUS WRITE Address Out Data Out
If mode 0 selected (CB only), one wait state is always added. If additional wait states are required, add 2 TOSC to these specifications.
A5837-01
5.2.3
87C196CB Timings
Figure 10. 87C196CB Buswidth Timings
TOSC XTAL1
CLKOUT
ALE TLLGV BUS WIDTH TAVGV BUS WRITE Address Out Data Out Address Out Valid TCLGX Valid
If mode 0 selected (CB only), add 2 TOSC to these specifications.
A5861-01
18
ADVANCE INFORMATION Datasheet
87C196CA/87C196CB - Express
5.2.4
8xC196CB Timings
Table 8. 8xC196CB HOLD#/HOLDA# Timings (Over Specified Operation Conditions)
Symbol THVCH TCLHAL TCLBRL TAZHAL TBZHAL TCLHAH TCLBRH THAHAX THAHBV HOLD Setup Time CLKOUT Low to HLDA Low CLKOUT Low to BREQ Low
HLDA Low to Address Float HLDA Low to BHE#, INST, RD#, WR# Weakly Driven CLKOUT Low to HLDA High CLKOUT Low to BREQ High HLDA High to Address No Longer Float HLDA High to BHE#, INST, RD#, WR# Valid
Parameter
Min + 65 -15 -15
Max
Units ns (1)
+ 15 + 15 + 25 + 25
ns ns ns ns ns ns ns
-15 -25 -15 -10
+ 15 + 25
+ 15
ns
NOTE: 1. To guarantee recognition at next clock.
Figure 11. 87C196CB HOLD#/HOLDA# Timings
TOSC
CLKOUT
THVCH
HOLD#
Hold Latency
THVCH
TCLHAL
HOLDA#
TCLHAH TCLBRH
TCLBRL
BREQ#
THALAZ
BUS
THAHAX
THALBZ
BHE#, INST, RD#, WR#
THAHAX TCHLH
ALE
A5848-01
ADVANCE INFORMATION Datasheet
19
87C196CA/87C196CB - Express
5.2.5
8xC196CB AC Characteristics - Slave Port
Figure 12. Slave Port Waveform - (SLPL = 0)
CS
TSRHAV
ALE / A1
TSRLRH
RD
TSRLDV
P3
TSRHDZ
TSDVWH TSAVWL
WR
TSWLWH
TSWHQX
A5847-01
Table 9. Slave Port Timing - (SLPL = 0, 1, 2, 3)
Symbol TSAVWL TSRHAV TSRLRH TSWLWH TSRLDV TSDVWH TSWHQX TSRHDZ Parameter Address Valid to WR# Low RD# High to Address Valid RD# Low Period
WR# Low Period RD# Low to Output Data Valid Input Data Setup to WR# High WR# High to Data Invalid RD# High to Data Float
Min 50 60 TOSC TOSC
Max
Units ns ns ns ns
60 20 30 15
ns ns ns ns
NOTE: 1. Test Conditions: * FOSC = 16 MHz * TOSC = 60 ns * Rise/Fall Time = 10 ns * Capacitive Pin Load = 100 pF 2. These values are not tested in production, and are based upon theoretical estimates and/or laboratory tests. 3. Specifications above are advance information and are subject to change.
20
ADVANCE INFORMATION Datasheet
87C196CA/87C196CB - Express
Figure 13. Slave Port Waveform - (SLPL = 1)
TSELLL
CS
TSRHEH
ALE RD
TSLLRL
TSRLRH
TSRLDV
P3
TSRHDZ
TSDVWH TSAVLL
WR
TSLLAX
TSWLWH
TSWHQX
A5846-01
Table 10. Slave Port Timing - (SLPL = 1, 2, 3)
Symbol TSELLL TSRHEH TSLLRL TSRLRH TSWLWH TSAVLL TSLLAX TSRLDV TSDVWH TSWHQX TSRHDZ Parameter CS# Low to ALE Low RD# or WR# High to CS# High ALE Low to RD# Low RD# Low Period WR# Low Period Address Valid to ALE Low
ALE Low to Address Invalid RD# Low to Output Data Valid Input Data Setup to WR# High WR# High to Data Invalid RD# High to Data Float
Min 20 60 TOSC TOSC TOSC 20 20
Max
Units ns ns ns ns ns ns ns
60 20 30 15
ns ns ns ns
NOTE: 1. Test Conditions: * FOSC = 16 MHz * TOSC = 60 ns * Rise/Fall Time = 10 ns * Capacitive Pin Load = 100 pF 2. These values are not tested in production, and are based upon theoretical estimates and/or laboratory tests. 3. Specifications above are advance information and are subject to change.
ADVANCE INFORMATION Datasheet
21
87C196CA/87C196CB - Express
Table 11. Normal Master/Slave Operation
Symbol TCHCH TCLCH TCLDV TCLDV1 TDVCH TCHDX Clock Period Clock Low Time/Clock High Time Clock Falling to Data Out Valid (Master) Clock Falling to Data Out Valid (Slave) Data In Setup to Clock Rising Edge Clock Rising Edge to Data In Invalid Parameter Min (1) 4t 2t-10 0.5t 0.5t 10 t + 15 1.5t + 20 1.5t + 20 Max Units ns ns (2) ns ns ns ns
NOTE: 1. t = 1 state time (125 ns @ 16 MHz). 2. Timings are guaranteed by design.
Table 12. Handshake Operation
Symbol TCHCH TCLCH TCLDV TCLDV1 TDVCH TCHDX Clock Period Clock Low Time/Clock High Time Clock Falling to Data Out Valid (Master) Clock Falling to Data Out Valid (Slave) Data In Setup to Clock Rising Edge Clock Rising Edge to Data In Invalid Parameter Min (1) 4t 2t-10 0.5t 0.5t 10 t + 15 1.5t + 20 1.5t + 20 Max Units ns ns (2) ns ns ns ns
NOTE: 1. t = 1 state time (125 ns @ 16 MHz). 2. This specification refers to input clocks during slave operation. During master operation, the device outputs a nominal 50% duty cycle clock.
22
ADVANCE INFORMATION Datasheet
87C196CA/87C196CB - Express
Figure 14. Synchronous Serial Port
1 SCx
2
3
4
5
6
7
8
TCHCL TCLCH TCHCH
STE Bit
SDx (out)
MSB
D6
D5
D4
D3
D2
D1
D0
TD1DV
SDx (in) SCx (Handshake Mode)
valid valid valid valid valid valid valid valid
TDVCX
1 2 3 4 5 6 7
TDXCX
8
TCXDX
NOTE:
TCXDV
Slave Receiver Pulls SCx low
The top SCx signal assumes that the SSIO is configured to sample on the leading edge with an active-high clock signal. The CSx signal will be different for other configurations, however, setup and hold timings will still be the same in relation to the latching edge of SCx.
A5845-01
Table 13. External Clock Drive
Symbol 1/TXLXL TXLXL TXHXX TXLXX TXLXH TXHXL Parameter Oscillator Frequency Oscillator Period (TOSC) High TIme Low Time Rise TIme Fall Time Min (1) 4 62.5 0.35 x TOSC 0.35 x TOSC Max 16 250 0.65 TOSC 0.65 TOSC 10 10 Units MHz ns ns ns ns ns
NOTE: 1. t = 1 state time (125 ns @ 16 MHz). 2. This specification refers to input clocks during slave operation. During master operation, the device outputs a nominal 50% duty cycle clock.
ADVANCE INFORMATION Datasheet
23
87C196CA/87C196CB - Express
Figure 15. External Clock Drive Waveforms
TXHXX 0.7 VCC + 0.5 V 0.7 VCC + 0.5 V
TXLXH TXLXX 0.3 VCC - 0.5 V 0.7 VCC + 0.5 V 0.3 VCC - 0.5 V TXLXL
TXHXL
A5842-01
Figure 16. Input Test Conditions
INPUTS
OUTPUTS
3.5 V Test Points 0.45 V
2.0 V 0.8 V
Note: AC testing inputs are driven at 3.5 V for a logic "1" and 0.45 V for a logic "0". Timing measurements are made at 2.0 V for a logic "1" and 0.8 V for a logic "0".
A5843-01
Figure 17. Output Test Conditions
VLOAD + 0.15 V VLOAD VLOAD - 0.15 V Timing Reference Points
VOH - 0.15 V
VOL + 0.15 V
Note: For timing purposes, a port pin is no longer floating when a 150 mV change from load voltage occurs and begins to float when a 150 mV change from the loading VOH/VOL level occurs with IOL/IOH 15 mA.
A5844-01
5.2.6
Explanation of AC Symbols
Each symbol is two pairs of letters prefixed by "T" for time. The characters in a pair indicate a signal and its condition, respectively. Symbols represent the time between the two signal/condition points.
24
ADVANCE INFORMATION Datasheet
87C196CA/87C196CB - Express
Table 14. Explanation of AC Symbols
Conditions H - High L - Low V - Valid X - No Longer Valid Z - Floating Signals A - Address B - BHE# BR - BREQ# C - CLKOUT D - DATA G - Buswidth H - HOLD# HA - HLDA# L - ALE/ADV# Q - Data Out R - RD# W - WR#/WRH#/WRI# X - XTAL1 Y - READY
5.3
5.3.1
EPROM Specifications
AC EPROM Programming Characteristics
Operating Conditions:
* Load Capacitance = 150 pF * TC = 25C 5C * VREF = 5.0 V 0.5 V * VCC * ANGND = 0 V * VPP = 12.5 V 0.25 V * V SS * EA# = 12.5 V 0.25 V * FOSC = 5.0 MHz
Table 15. AC EPROM Programming Characteristics (Sheet 1 of 2)
Symbol TAVLL TLLAX TDVPL TPLDX TLLLH TPLPH TLHPL TPHLL TPHDX TPHPL TLHPL TPLDV TSHLL TPHIL TILIH TILVH TILPL RESET# High to First PALE# Low PROG# High to AINC# Low AINC# Pulse Width PVER Hold after AINC# Low AINC# Low to PROG# Low PALE# High to PROG# Low PROG# High to Next PALE# Low Word Dump Hold Time PROG# High to Next PROG# Low PALE# High to PROG# Low PROG# Low to Word Dump Valid CA CB 1100 0 240 50 170 50 100 TOSC TOSC TOSC TOSC TOSC TOSC 220 220 Parameter Address Setup Time Address Hold Time Data Setup Time Data Hold Time PALE# Pulse Width PROG# Pulse Width (2) CA CB 50 100 220 220 50 TOSC TOSC TOSC TOSC TOSC TOSC Min 0 100 0 400 50 Max Units TOSC TOSC TOSC TOSC TOSC
ADVANCE INFORMATION Datasheet
25
87C196CA/87C196CB - Express
Table 15. AC EPROM Programming Characteristics (Sheet 2 of 2)
Symbol TPHVL Parameter PROG# High to PVER# Valid Min Max 220 Units TOSC
NOTES: 1. Run time programming is done with FOSC = 6 MHz to 10 MHz, VCC, VPD, VREF = 5 V 0.5 V, TC = 25C 5C and VPP = 12.5 V 0.25 V. For run-time programming over a full operating range, contact factory. 2. Programming Specifications are not tested, but guaranteed by design. 3. This specification is for the word dump mode. For programming pulses use 300 TOSC + 100 s.
Table 16. DC EPROM Programming Characteristics
Symbol IPP Parameter VPP Programming Supply Current Min 200 Max mA Units
NOTE: VPP must be within 1 V of VCC while VCC < 4.5 V. VPP must not have a low impedance path to ground or VSS while VCC > 4.5 V.
5.3.2
EPROM Programming Waveforms
Figure 18. Slave Programming Mode Data Program Mode with Single Program Pulse
RESET#
TAVLL TDVPL Data TLLAX TPLDX Address/Command
PORTS 3/4
Address/Command TSHLL
PALE# P2.1
TLLLH TLHPL TPLPH TPHLL
PROG# P2.2
TPHVL
PVER# P2.0
Valid TLLVH A5838-01
26
ADVANCE INFORMATION Datasheet
87C196CA/87C196CB - Express
Figure 19. Slave Programming Mode in Word Dump or Data Verify Mode with Auto Increment
RESET#
ADDR ADDR + 2 Ver Bits/WD Dump TPLDV TPHDX
PORTS 3/4
Address/Command TSHLL TPLDV
Ver Bits/WD Dump TPHDX
PALE# P2.1 PROG# P2.2
TILPL TPHPL
PVER# P2.0
A5839-01
Figure 20. Slave Programming Mode Timing in Data Program Mode with Repeated Program Pulse and Auto Increment
RESET#
PORTS 3/4
Address/Command
Data
Data
PALE# P2.1 PROG# P2.2 PVER# P2.0 AINC# P2.4
TPHPL P1 P2
TILPL
TILVH Valid For P1 Valid For P2 TILIH
TPHIL A5840-01
ADVANCE INFORMATION Datasheet
27
87C196CA/87C196CB - Express
5.4
AC CHARACTERISTICS - Serial Port - Shift Register Mode
Operating Conditions:
* * * *
TA = -40C +85C VSS = 0.0 V VCC = 5.0 V 10% Load Capacitance = 100 pF
Table 17. Serial Port Timing - Shift Register Mode
Symbol TXLXL TXLXH TQVXH TXHQX TXHQV TDVXH TXHDX (1) TXHQZ (1) Parameter Serial Port Clock Period Serial Port Clock Falling Edge to Rising Edge Output Data Setup to Clock Rising Edge Output Data Hold after Clock Rising Edge Next Output Data Valid after Clock Rising Edge Input Data Setup to Clock Rising Edge Input Data Hold after Clock Rising Edge Last Clock Rising to Output Float 2 TOSC - 200 0 5TOSC Min 8 TOSC 4 TOSC - 50 3 TOSC 2 TOSC - 50 2 TOSC + 50 4 TOSC + 50 Max Units ns ns ns ns ns ns ns ns
NOTE: 1. Parameter not tested.
Figure 21. Waveform - Serial Port - Shift Register Mode 0
TXLXL TXDx TQVXH RXDx (Out) RXDx (In)
0 1 2
TXLXH
3
TXHQV
4
TXHQX
5 6
TXHQZ
7
TDVXH
Valid Valid Valid
TXHDX
Valid Valid Valid Valid Valid
A5841-01
5.4.1
A/D Characteristics
The sample and conversion time of the A/D converter in the 8-bit or 10-bit modes is programmed by loading a byte into the AD_TIME Special Function Register. This allows optimizing the A/D operation for specific applications. The AD_TIME register is functional for all possible values, but the accuracy of the A/D converter is only guaranteed for the times specified in the operating conditions table. The value loaded into AD_TIME bits 5, 6, 7 determines the sample time, SAMP. The value loaded into AD_TIME bits 0, 1, 2, 3 and 4 determines the bit conversion time, CONV. These bits, as well as the equation for calculating the total conversion time, T, are shown in Figure 22.
28
ADVANCE INFORMATION Datasheet
87C196CA/87C196CB - Express
Figure 22. AD_TIME 1FAFH:Byte 7 6 5 Sample Time 4 3 2 1 Bit Conversion Time (CONV) n + 1 state times n = 2 to 31 0
(SAMP) 4n + 1 state times n = 1 to 7
Equation: T = (SAMP + Bx (CONV) + 25 T = total conversion time (states) B = number of bits conversion (8 or 10) n = programmed register value The converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of VREF. V REF must be closed to VCC since it supplies both the resistor ladder and the analog portion of the converter and input port pins. There is also an AD_TEST SFR that allows for conversion on ANGND and VREF as well as adjusting the zero offset. The absolute error listed is without doing any adjustments.
5.4.1.1
A/D Converter Specification
The specifications given assume adherence to the operating conditions section of this data sheet. Testing is performed with VREF = 5.12 V and 16 MHz operating frequency. After a conversion is started, the device is placed in IDLE mode until the conversion is completed.
Table 18. 10-Bit Mode A/D Operating Conditions
Symbol TA VCC VREF TSAM TCONV FOSC Ambient Temperature Digital Supply Voltage Analog Supply Voltage Sample Time Conversion Time Oscillator Frequency Parameter Min -40 4.5 4.5 2 15 4 18 16 Max +85 5.5 5.5 (1) Units C V V s (2) s (2) MHz
NOTES: 1. VREF must be within+0.5 V of VCC . 2. The value of AD_TIME is selected to meet these specifications.
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87C196CA/87C196CB - Express
Table 19. 10-Bit Mode A/D Characteristics (Using Above Operating Conditions) (1)
Parameter Resolution Absolute Error Full-scale Error Zero Offset Error Non-Linearity Differential Non-Linearity Channel-to-Channel Matching Repeatability Temperature Coefficients: Offset Fullscale Differential Non-Linearity Off Isolation Feedthrough VCC Power Supply Rejection Input Resistance DC Input Leakage Voltage on Analog Input Pin Sampling Capacitor 3 1 - 60 - 60 750 0 ANGND -0.5 1.2 K 3 VREF + 0.5 0.1 0.25 0.25 0.5 0.25 0.5 12 > - 0.75 0 0 3 + 0.75 1 Typical (2,3) Min 1024 10 0 Max 1024 10 3 Units (4) Levels Bits LSBs LSBs LSBs LSBs LSBs LSBs LSBs (2) Notes
0.009
LSB/C
(2)
- 60
dB dB dB A V pF
(2,4,5) (2,4) (2,4) (2)
(7)
NOTES: 1. All conversions performed with processor in IDLE mode. 2. These values are expected for most parts at 25C but are not tested or guaranteed. 3. These values are not tested in production and are based on theoretical estimates and/or laboratory test. 4. An "LSB", as used here, has a value of approximately 5 mV 5. DC to 100 KHz 6. Multiplexer Break-Before-Make Guaranteed. 7. Applying voltages beyond these specifications will degrade the accuracy of other channels being converted.
Table 20. 8-Bit Mode A/D Operating Conditions
Symbol TA VCC VREF TSAM TCONV FOSC Parameter Ambient Temperature Digital Supply Voltage Analog Supply Voltage Sample Time Conversion Time Oscillator Frequency Min -40 4.5 4.5 2 12 4 15 16 Max +85 5.5 5.5 (1) Units C V V s (2) s (2) MHz
NOTES: 1. V REF must be within+0.5 V of VCC. 2. The value of AD_TIME is selected to meet these specifications.
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87C196CA/87C196CB - Express
Table 21. 8-Bit Mode A/D Characteristics (Using Above Operating Conditions) (1)
Parameter Resolution Absolute Error Full-scale Error Zero Offset Error Non-Linearity Differential Non-Linearity Channel-to-Channel Matching Repeatability Temperature Coefficients: Offset Fullscale Differential Non-Linearity Off Isolation Feedthrough VCC Power Supply Rejection Input Resistance DC Input Leakage Voltage on Analog Input Pin Sampling Capacitor 3 1 - 60 - 60 750 0 ANGND -0.5 1.2 K 1.5 VREF + 0.5 0.25 > - 0.75 0 0 0.5 0.5 1 + 0.5 1 Typical (2,3) Min 256 8 0 Max 1024 10 1 Units (4) Levels Bits LSBs LSBs LSBs LSBs LSBs LSBs LSBs (2) Notes
0.003
LSB/C
(2)
- 60
dB dB dB A V pF
(2,4,5) (2,4) (2,4) (2)
(7)
NOTES: 1. All conversions performed with processor in IDLE mode. 2. These values are expected for most parts at 25C but are not tested or guaranteed. 3. These values are not tested in production and are based on theoretical estimates and/or laboratory test. 4. An "LSB", as used here, has a value of approximately 5 mV 5. DC to 100 KHz 6. Multiplexer Break-Before-Make Guaranteed. 7. Applying voltages beyond these specifications will degrade the accuracy of other channels being converted.
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87C196CA/87C196CB - Express
5.4.2
87C196CA Design Considerations
The 87C196CA device is a memory scalar of the 87C196KR device with integrated CAN 2.0. The CA is designed for strict functional and electrical compatibility to the Kx family as well as integration of on-chip networking capability. The 87C196CA has fewer peripheral functions than the 196KR, due in part to the integration of the CAN peripheral. Following are the functionality differences between the 196KR and 196CA devices. 196KR Features Unsupported on the 196CA:
* * * *
Analog Channels 0 and 1 INST Pin Functionality SLPINT and SLPCS Pin Support HLD/HLDA Functionality
* * * *
External Clocking/Direction of Timer1 Quadrature Clocking Timer 1 Dynamic Buswidth EPA Capture Channels 47
1. External Memory. Removal of the Buswidth pin means the bus cannot dynamically switch from 8- to 16-bit bus mode or vice versa. The programmer must define the bus mode by setting the associated bits in the CCB. 2. Auto-Programming Mode. The 87C196CA device will ONLY support the 16-bit zero wait state bus during auto-programming. 3. EPA4 through EPA7. Since the CA device is based on the KR design, these functions are in the device, however there are no associated pins. A programmer can use these as compare only channels or for other functions like software timer, start an A/D conversion, or reset timers. 4. Slave Port Support. The Slave port can not be used on the 196CA due to a function change for P5.4/SLPINT and P5.1/SLPCS not being bonded-out. 5. Port Functions. Some port pins have been removed. P5.1, P6.2, P6.3, P1.4 through P1.7, P2.3, P2.5, P0.0 and P0.1. The PxREG, PxSSEL, and PxIO registers can still be updated and read. The programmer should not use the corresponding bits associated with the removed port pins to conditionally branch in software. Treat these bits as RESERVED. Additionally, these port pins should be setup internally by software as follows: * Written to PxREG as 1'' or 0''. * Configured as Push/Pull, PxIO as 0''. * Configured as LSIO. This configuration will effectively strap the pin either high or low. DO NOT Configure as Open Drain output '1'', or as an Input pin. This device is CMOS. 6. EPA Timer RESET/Write Conflict. If the user writes to the EPA timer at the same time that the timer is reset, it is indeterminate which will take precedence. Users should not write to a timer if using EPA signals to reset it. 7. Valid Time Matches. The timer must increase/decrease to the compare value for a match to occur. A match does not occur if the timer is loaded with a value equal to an EPA compare value. Matches also do not occur if a timer is reset and 0 is the EPA compare value. 8. Write Cycle during Reset. If RESET occurs during a write cycle, the contents of the external memory device may be corrupted. 9. Indirect Shift Instruction. The upper 3 bits of the byte register holding the shift count are not masked completely. If the shift count register has the value 32 c n, where n e 1, 3, 5, or 7, the operand will be shifted 32 times. This should have resulted in no shift taking place. 10. P2.7 (CLKOUT). P2.7 (CLKOUT) does not operate in open drain mode.
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5.4.3
87C196CA ERRATA
This data sheet was published prior to first available silicon. Consequently, there is no known errata at this time.
5.4.4
87C196CA DESIGN CONSIDERATIONS
1. PORT0 On the 87C196CA the analog inputs for P0.0 and P0.1 have been multiplexed and tied to VREF. Therefore, initiating an analog conversion on ACH0 or ACH1 results in a value equal to full scale (3FFh). On the CA, the digital inputs for these two channels are tied to ground, therefore, reading P0.0 or P0.1 results in a digital "0". 2. PORT1 On the 87C196CA, P1.4, P1.5, P1.6 and P1.7 have been removed from the device and is not available to the programmer. Corresponding bits in the port registers have been "hard-wired" to provide the following results when read:
Register Bits P1_PIN.x P1_REG.x P1_DIR.x P1_MODE.x NOTE: Writing to these bits has no effect. (x = 4,5,6,7) (x = 4,5,6,7) (x = 4,5,6,7) (x = 4,5,6,7) When Read 1 1 1 0
3. PORT2 On the 87C196CA, P2.3 and P2.5 have been removed from the device and are not available to the programmer. Corresponding bits in the port registers have been "hard-wired" to provide the following results when read.
Register Bits P2_PIN.x P2_REG.x P2_DIR.x P2_MODE.x NOTE: Writing to these bits has no effect. (x = 3,5) (x = 3,5) (x = 3,5) (x = 3,5) When Read 1 1 1 0
4. PORT5 On the 87C196CA, P5.1 and P5.7 have been removed from the device and are not available to the programmer. Corresponding bits in the port registers have been "hard-wired" to provide the following results when read:
Register Bits P5_PIN.x P5_REG.x P5_DIR.x P5_MODE.x P5_MODE.x NOTE: Writing to these bits has no effect. (x = 1,7) (x = 1,7) (x = 1,7) (x = 1) (x = 7) When Read 1 1 1 0 1
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87C196CA/87C196CB - Express
5. PORT6 On the 87C196CA, P6.2 and P6.3 have been removed from the device and are not available to the programmer. Corresponding bits in the port registers have been "hard-wired" to provide the following results when read:
Register Bits P6_PIN.x P6_REG.x P6_DIR.x P6_MODE.x NOTE: Writing to these bits has no effect. (x = 2,3) (x = 2,3) (x = 2,3) (x = 2,3) When Read 1 1 1 0
6.0
DATASHEET REVISION HISTORY
This is the -001 version of the "87C196CA/87C196CB - Express" datasheet.
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