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Voltage Regulators
AN1149NFHK
6-ch DC-DC Converter
I Overview
4 channels of step-up, 1 channel of step-down and 1 channel of step-up/down voltage, 6 channels in total have been integrated onto a single chip. Each channel can be remote-controlled and work with two dry cells. A high precision output voltage can be obtained thanks to the accurate reference of VREF 1%.
9.00.2 7.00.1 36 37 25 24
(0.75) 7.00.1 9.00.2
Unit: mm
48
I Features
* Low voltage operation (1.5 V min.) * High precision reference voltage (1%) * Remote control for each channel
(0.75)
13 1 12 0.200.05
(1.0) 0.10+0.10 -0.05
0.5
0.10 M (1.0)
1.20 max. 0.150.05
I Applications
* Digital still cameras
0 to 8 0.50.1
TQFP048-P-0707B (Lead-free package)
Publication date: May 2002
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AN1149NFHK
I Block Diagram
PVCC1 PVCC2 SVCC 10PV 26 32 PV
CC1 CC2
VREF 40
Reference voltage supply 1.26 V 1% R LATCH Q S
RT CT CTL 1 39 38 46
OSC Start-up VBAT Latch circuit U.V.L.O. RQS
S.C.P.1 41 14 VBAT
SCP
37
VCC U.V.L.O.
SVCC
EO 1 IN-1
3 2
Error-amp.1
VREF
PVCC1
PWM1
VREF S.C.P. comp. 0.9 V VREF
13
PGND1 REG-amp.1
Out 1
VREF PVCC1
SRFB 47 SRIN 1 SRDV 48 SS 1 12 Out 2
EO 2 6 IN-2 4
Error-amp.2 CTL
PWM2
16
VREF PGND1 VREF VREF comp.2
CTL 2 45 15 SS 2 EO 3 9
Error-amp.3
7 FB 3 8 IN-3
VREF
PWM3
Boot-up /step-down switch
PVCC1
36 18
UDSW Out 3 SS 3
VREF PGND1
35 EO 4 34 FB 4 33 IN-4 CTL 34 EO 5 IN-5 44 30 31
17
PVCC2
Error-amp.4
VREF
CTL comp.4
PWM4
VREF
19
PGND2
Out 4
VREF PVCC2
Error-amp.5
20
SS 4
VREF
CTL comp.5
PWM5
VREF
21
PGND2
Out 5
CTL 5 EO 6 IN-6 IN+6 CTL 6
43 27 29 28 42
Error-amp.6
VREF
22
PVCC2 VREF
CTL VREF comp.6
SS 5
PWM6
23
PGND2
Out 6 SS 6
24 5 11 25 SGND PGND 1 PGND 2
2
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AN1149NFHK
I Pin Descriptions
Pin No. Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Description Pin No. Symbol 27 28 29 30 31 32 33 34 35 36 37 EO 6 IN+6 IN-6 E 5 IN-5 Description Output pin for part-6 error amplifier Non-inverted input pin for part-6 error amplifier Inverted input pin for part-6 error amplifier Output pin for part-5 error amplifier Inverted input pin for part-5 error amplifier SRIN Regulator amplifier input pin IN-1 EO 1 IN-2 Inverse input for part-1 error amplifier Output for part-1 error amplifier Inverse input for part-2 error amplifier
SGND Signal GND pin EO 2 FB 3 IN-3 EO 3 Output for part-2 error amplifier CH 3 output voltage detection pin Inverse input for part-3 error amplifier Output for part block-3 error amplifier
SVCC Supply voltage application pin for signal block IN-4 FB 4 EO 4 Inverted input pin for part-4 error amplifier CH 4 output voltage detection pin Output pin for part-4 error amplifier
PVCC1 Voltage application pin 1 for output block PGND1 Output GND pin 1 SS-1 CH 1 soft start setting pin
UDSW Step-down output setup pin for CH 3 SCP Short-circuit protection time constant setup capacitance connection pin for CH 2-6
Out-1 Push-pull output pin for out-1 block VBAT Battery voltage application pin SS-2 CH 2 soft start setting pin
38
CT
Oscillator frequency setup capacitor connection pin
39
RT
Oscillator frequency setup resistor connection pin
Out-2 Totem pole output pin for out-2 block SS-3 CH 3 soft start setting pin 40 41 VREF
Reference voltage output pin
Out-3 Totem pole output pin for out-3 block Out-4 Totem pole output pin for out-4 block SS-4 CH 4 soft start setting pin
SCP 1 Output short-circuit protection time constant setup capacitor connection pin for CH 1
42 43 44 45 46 47 48
CTL 6 CH 6. on-off control pin CTL 5 CH 5. on-off control pin CTL 34 CH 3, CH 4. on-off control pin CTL 2 CH 2. on-off control pin CTL 1 CH 1. on-off control pin SRFB Regulator amplifier output voltage detection pin SRDV Regulator amplifier drive pin
Out-5 Totem pole output pin for out-5 block SS-5 CH 5 soft start setting pin
Out-6 Totem pole output pin for out-6 block SS-6 CH 6 soft start setting pin
PGND2 Output GND pin 2 PVCC2 Voltage application pin 2 for output block
I Absolute Maximum Ratings
Parameter Supply voltage Power VCC1 allowable application voltage Power VCC2 allowable application voltage Battery input allowable application voltage Allowable application voltage to regulator output voltage detection input pin Symbol SVCC PVCC1 PVCC2 VBAT VSRFB Rating 9.2 9.2 9.2 9.2 SVCC Unit V V V V V
Note) 1. Do not apply external currents or voltages to any pins not specifically mentioned. For the circuit currents, '+' denotes current flowing into the IC, and '-' denotes current flowing out of the IC. 2. Except for the power dissipation, operating ambient temperature and storage temperature, all ratings are for Ta = 25C.
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I Absolute Maximum Ratings (continued)
Parameter Step up / down switch input allowable application voltage *2 Allowable application voltage to output voltage detection input 3 Allowable application voltage to output voltage detection input 4 Allowable application voltage to control input 1 Allowable application voltage to control input 2 Allowable application voltage to control input 3, 4 Allowable application voltage to control input 5 Allowable application voltage to control input 6 Error amplifier allowable application voltage to input pin Supply current Output 2 allowable peak current Output 3 allowable peak current Output 4 allowable peak current Output 5 allowable peak current Output 6 allowable peak current Output 1 allowable sequence current Output 2 allowable sequence current Output 3 allowable sequence current Output 4 allowable sequence current Output 5 allowable sequence current Output 6 allowable sequence current Reference voltage allowable application current Power dissipation *1 Operating ambient temperature Storage temperature Symbol VUDSW VFB3 VFB4 VCTL1 VCTL2 VCTL34 VCTL5 VCTL6 VIN ICC IOP2 IOP3 IOP4 IOP5 IOP6 IO1 IO2 IO3 IO4 IO5 IO6 IREF PD Topr Tstg Rating SVCC SVCC SVCC VBAT SVCC SVCC SVCC SVCC - 0.2 to SVCC 400 400 400 400 400 -50 100 100 100 100 100 -5 160 -20 to +85 -55 to +125 Unit V V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mW C C
Note) 1. Do not apply external currents or voltages to any pins not specifically mentioned. For the circuit currents, '+' denotes current flowing into the IC, and '-' denotes current flowing out of the IC. 2. Except for the power dissipation, operating ambient temperature and storage temperature, all ratings are for Ta = 25C. 3. *1: Ta = 85C. For the independent IC without a heat sink. Note that applications must observe the derating curve for the relationship between the IC power consumption and the ambient temperature. *2: Allowable application voltage shall be 8.2 V or less when SVCC 8.2 V.
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I Recommended Operating Range
Parameter Supply voltage Symbol VBAT SVCC Range 1.5 to 9 4.5 to 9 Unit V V
I Recommended Operating Conditions
Parameter Out-1 source current Out-2 to Out-6 peak current Timing resistance Timing capacitance Oscillation frequency Short-circuit protection time constant setting capacitance Symbol IOUT1 IOUT2 to 6 RT CT fOUT CSCP1, 2 Range 30 (max.) -400 to 400 8 to 100 560 (fixed) 100 to 1 000 1 000 (min.) Unit mA mA k pF kHz pF
I Electrical Characteristics at VBAT = 3 V, SVCC = PVCC1 = PVCC2 = 5 V, CREF = 0.1 F, Ta = 25C
Parameter Reference voltage Reference voltage Line regulation Load regulation SVCC low voltage protection Circuit operation start voltage Circuit operation stop voltage VBAT low voltage protection Circuit operation start voltage Circuit operation stop voltage Oscillator CH 1 oscillation frequency at startup CH 1 to CH 6 oscillation frequency Output block CH 1 to CH 6 output maximum duty ratio CH 1 output duty ratio at startup Output high voltage 1 (CH 1) Output source current DUST VOH1 IOL1 DU1 to 6 RT = 20 k CT = 560 pF CH 4 except CH 4 78 82 60 VCC - 2 20 VCC - 1 84 88 68 90 94 76 1 % % % V mA V V 5 fST CT = 560 pF SVCC = PVCC1 = PVCC2 = 1 V 55 490 80 540 105 590 kHz kHz VBATON VBATOFF 1.36 1.33 1.43 1.39 1.5 1.45 V V SVCCON SVCCOFF 3.9 3.7 4.1 3.9 4.3 4.1 V V VREF Line Load IREF = - 0.1 mA VCC = 4.5 V to 9 V IREF = - 0.1 mA to -1 mA 1.247 -20 1.26 3 -5 1.273 20 V mV mV Symbol Conditions Min Typ Max Unit
fOUT1 to 6 RT = 20 k CT = 560 pF
CT = 560 pF SVCC = PVCC1 = PVCC2 = 1 V IOUT1 = 20 mA VOUT1 = 0.7 V
Output high voltage 2 to 6 (CH 2 to CH 6) VOH2 to 6 IOUT2 to 6 = - 0.1 mA Output low voltage 2 to 6 (CH 2 to CH 6) VOL2 to 6 IOUT2 to 6 = 0.1 mA
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I Electrical Characteristics at VBAT = 3 V, SVCC = PVCC1 = PVCC2 = 5 V, CREF = 0.1 F, Ta = 25C (continued)
Parameter Output block (continued) Output high voltage at standby (CH 3, CH 4) Output low voltage at standby (CH 2, CH 3, CH 5, CH 6) CH 3 output setup block Threshold voltage Error amplifier (CH 1 to CH 6) Input threshold voltage 1 to 6 Input bias current 2, 5, 6 High-level output voltage 1 to 6 Low-level output voltage 1 to 6 Output source current 1 to 6 Output sink current 1 to 6 CH 6 offset voltage CH 1, CH 3, CH 4 output detection resistance division ratio VTH1 to 6 IB2, 5, 6 VEH1 to 6 VEL1 to 6 ISO1 to 6 ISI1 to 6 VOFF6 RO1, 3, 4 1.241 1.26 -38 1.279 0.2 -32 6 1 V A V V A mA mV % - 0.22 - 0.12 1.0 -45 0.5 -6 -1 VCTH 1.56 1.96 2.36 V VOHS3, 4 IOUT3, 4 = - 0.1 mA VOLS2 to 6 IOUT2, 3, 5, 6 = 0.1 mA VCC - 1 1.0 V V Symbol Conditions Min Typ Max Unit
CH 1 short-circuit protection circuit block Pin voltage at standby Latch threshold voltage Pin voltage at latch operation Charge current VSTB1 VLTH1 VSLT1 ICHG1 VSTB1 VLTH2 to 6 VSLT2 to 6 ICHG1 ICTL2 to 6 VCTL1 VCTL2 to 6 VSCP = 0 V VSCP1 = 0 V 0.27 -3.1 0.8 -1.53 -1.53 1.07 0.3 -2.4 0.9 0.1 0.33 0.1 -1.7 0.1 1.0 0.1 V V V A V V V A A V V
CH 2 to CH 6 short-circuit protection circuit block Pin voltage at standby Latch threshold voltage 2 to 6 Pin voltage 2 to 6 at latch operation Charge current Control Pin current (CH 2, CH 34, CH 5, CH 6) CH 1 threshold voltage CH 2, CH 34, CH 5, CH 6 threshold voltage Regulator amplifier Output high voltage Pin voltage when external PNP transistor is connected Output detection resistance division ratio 6 VHRA VRA ROR
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-1.2 - 0.87 -1.2 - 0.87 1.0 1.26 1.5 1.45
VCC = 5 V ISRDV = 10 mA SVCC = 5.5 V to 7.5 V
4.9 -1
5.0
1 5.1 1
V V %
AN1149NFHK
I Electrical Characteristics at VBAT = 3 V, SVCC = PVCC1 = PVCC2 = 5 V, CREF = 0.1 F, Ta = 25C (continued)
Parameter Current consumption Current consumption at startup Average current consumption Standby current IBAT ICC(AV) ISB VBAT = 3 V SVCC = 1 V Duty = 50% VBAT = 3 V, SVCC = 1 V VCTL1 = 0 V 34 440 9 42 655 12 50 A mA A Symbol Conditions Min Typ Max Unit
* Design reference data
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter Reference voltage VREF temperature characteristics RT pin voltage SVCC low voltage protection
Symbol
Conditions Ta = -20C to 85C
Min -1.5
Typ
Max +1.5
Unit
VREFdT VRT
% V V
0.7 SVCCON - SVCCOFF > 0 0.2
Voltage difference between operation SVCC start and stop VBAT low voltage protection Voltage difference between operation start and stop Error amplifier (CH 1 to CH 6) VTH temperature characteristics Open loop gain Oscillator Frequency supply voltage characteristics Frequency temperature characteristics Short-circuit protection circuit Comparator threshold voltage Control (CTL 1) CTL 1 pin current ICTL1 VTHS fdV fdT VTHdT AV VBAT
VBATON - VBATOFF > 0
0.04
V
Ta = -30C to 85C
-1.5 80
+1.5
% dB
VCC = 4.5 V to 9 V RT = 20 k, CT = 560 pF Ta = -30C to 85C RT = 20 k, CT = 560 pF
-16 -3
+16 +3
% %
1.26 VCTL1 = 3 V
V A
230
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I Terminal Equivalent Circuits
Pin No. 1 Equivalent circuit
SVCC SRFB 37.4 k 1 12.6 k VREF
Description SRIN : Output voltage detection pin / inverting input pin for regulator amplifier. 12.6 k built in between SRIN and SGND, 37.4 k between SRIN and SRFB.
I/O I
2
SVCC 37.4 k 2 12.6 k VREF
IN-1 : Non-inverting input pin for CH 1 error amplifier 1. 12.6 k built in between IN-1 and SGND, and 37.4 k between IN-1 and SVCC. Set CH 1, DCDC output to 5 V.
I
3
VREF VREF IN-1 38 A 3 0.5 mA
EO 1 : Output pin for CH 1 error amplifier. Source current: -38 A, sink current: min. 0.5 mA.
O
4
SVCC
IN-2 : Non-inverting input pin for CH 2 error amplifier.
I
4
VREF
5 5 6
SGND : Signal GND pin. EO 2 : Output pin for CH 2 error amplifier. Source current: -38 A, sink current: min. 0.5 mA.
O
VREF VREF IN-2 38 A 6 0.5 mA
8
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I Terminal Equivalent Circuits (continued)
Pin No. 7
SVCC 7 20.4 k 8 VREF
Equivalent circuit
Description FB 3 : CH 3 output voltage detection pin. 12.6 k built in between IN-3 and SGND, and 20.4 k between IN-3 and FB 3. DC-DC output of CH 3 is set to 3.3 V. IN-3 : Non-inverting input pin for CH 3 error amplifier 3.
I/O I
8
12.6 k
I
9
VREF VREF IN-3 38 A 9 0.5 mA
EO 3 : Output pin for CH 3 error amplifier. Source current: -38 A, sink current: min. 0.5 mA.
O
10 10 11 11 12
PVCC1 : CH 1, CH 2 power supply pin for output block. PGND1 : CH 1, CH 2 output block GND pin. SS 1 : CH 1 soft start time setting pin. Connect a capacitor between this pin and GND. CH 1 max. duty ratio is set to 88% (in-house), but max. of on period can be adjusted by connecting a resistor between this pin and VREF pin. See Application Notes [3] 8. Out 1 : Output SW Tr. driver pin at start-up and pushpull output pin at PWM control. Absolute maximum rating of output source current at PWM is -50 mA.
I
VREF 43.8 k 12 56.2 k
EO 1 CT PWM1
13
VREF
O
SVCC1
13 OSC
a) at start-up
13
b) at PWM control
14 14
VBAT : Battery voltage application pin.
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I Terminal Equivalent Circuits (continued)
Pin No. 15 Equivalent circuit Description SS 2 : CH 2 soft start time setting pin. Connect a capacitor between this pin and GND. CH 2 max. duty ratio is set to 88% (in-house), but max. of on period can be adjusted by connecting a resistor between this pin and VREF pin. See Application Notes [3] 8. Out 2 : Totem pole type output pin. Normal output current 100 mA and a peak current 400 mA can be taken out. I/O I
VREF 43.8 k 15 56.2 k
EO 2 CT PWM2
16
SVCC1
O
16
17
VREF 43.8 k 17 56.2 k PWM3 EO 3 CT
SS 3 : CH 3 soft start time setting pin. Connect a capacitor between this pin and GND. CH 3 max. duty ratio is set to 88% (in-house), but max. of on period can be adjusted by connecting a resistor between this pin and VREF pin. See Application Notes [3] 8. Out 3 : Totem pole type output pin. Normal output current 100 mA and a peak current 400 mA can be taken out.
I
18
SVCC2
O
18
19
SVCC2
19
Out 4 : Totem pole type output pin. Normal output current 100 mA and a peak current 400 mA can be taken out.
O
20
VREF 43.8 k 20 56.2 k
EO 4 CT PWM4
SS 4 : CH 4 soft start time setting pin. Connect a capacitor between this pin and GND. CH 4 max. duty ratio is set to 84% (in-house), but max. of on period can be adjusted by connecting a resistor between this pin and VREF pin. See Application Notes [3] 8.
I
10
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I Terminal Equivalent Circuits (continued)
Pin No. 21 Equivalent circuit Description Out 5 : Totem pole type output pin. Normal output current 100 mA and a peak current 400 mA can be taken out. I/O O
SVCC2
21
22
VREF 43.8 k 22 56.2 k PWM5 EO 5 CT
SS 5 : CH 5 soft start time setting pin. Connect a capacitor between this pin and GND. CH 5 max. duty ratio is set to 88% (in-house), but max. of on period can be adjusted by connecting a resistor between this pin and VREF pin. See Application Notes [3] 8. Out 6 : Totem pole type output pin. Normal output current 100 mA and a peak current 400 mA can be taken out.
I
23
SVCC2
O
23
24
VREF 43.8 k 24 56.2 k
EO 6 CT PWM6
SS 6 : CH 6 soft start time setting pin. Connect a capacitor between this pin and GND. CH 6 max. duty ratio is set to 88% (in-house), but max. of on period can be adjusted by connecting a resistor between this pin and VREF pin. See Application Notes [3] 8. PGND2 : CH 3 to CH 6 output block GND pin. PVCC2 : CH 3 to CH 6 power supply pin for output block. EO 6 : Output pin for CH 6 error amplifier. Source current: -38 A, sink current: min. 0.5 mA.
I
25 25
26 26 27
VREF IN+6 IN-6 38 A 27 0.5 mA
O
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I Terminal Equivalent Circuits (continued)
Pin No. 28 SVCC Equivalent circuit Description IN+6 : Inverting input pin for CH 6 error amplifier. I/O I
29
29
28
IN-6 : Non-inverting input pin for CH 6 error amplifier.
I
30
VREF VREF IN-5 38 A 30 0.5 mA
EO 5 : Output pin for CH 5 error amplifier. Source current: -38 A, sink current: min. 0.5 mA.
O
31
SVCC
IN-5 : Non-inverting input pin for CH 5 error amplifier.
I
31
VREF
32 32 33
SVCC : Power supply pin for signal block. IN-4 : Non-inverting input pin for CH 4 error amplifier. FB 4 : CH 4 output voltage detection pin. 12.6 k built in between IN-4 and SGND, and 12.4 k between IN-4 and FB 3. DC-DC output of CH 4 is set to 2.5 V. EO 4 : Output pin for CH 4 error amplifier. Source current: -38 A, sink current: min. 0.5 mA.
I
SVCC
34
34 12.4 k 33 12.6 k VREF
I
35
VREF VREF IN-4 38 A 35 0.5 mA
O
12
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I Terminal Equivalent Circuits (continued)
Pin No. 36 SVCC Step up Step down VREF 36 Equivalent circuit Description UDSW : CH 3 step down / step-up output setup pin. N-channel drive and voltage step-up operation with UDSW of SVCC potential, P-channel drive and voltage step-down operation with UDSW of GND potential. I/O I
37
SVCC 1.2 A
LACH SRQ
Output cutoff
SCP : A capacitor connecting pin to set a time constant of timer latch short-circuit protection circuit to protect from CH 2 to CH 6 output short circuit. Use within 1 000 pF or more of capacitance. Charged current ICHG is 1.2 A typ. CT : Frequency setting capacitor connecting pin for start-up and for PWM control. 80 kHz fixed inside at startup, and use in the range of 100 kHz to 1 MHz by setting up the resistor at RT pin in PWM control. Here, use the 560 pF fixed capacitor.
O
37 38
at start-up
O
VBAT
38
at PWM control
SVCC 38 0.3 V 39 RT : Frequency setting resistor connection pin at PWM control. Use within 100 kHz to 1 MHz of oscillation frequency using a 8 k to 100 k resistor in combination with the capacitor at CT pin. VREF : Inner reference voltage output pin. Reference voltage is 1.26 V1% at IREF = - 0.1 mA, and SVCC = 5 V. Connect a capacitor of 0.1 F or more between VREF and GND for phase compensation. O
LACH SRQ
Dischavging current circuit
39
0.7 V
40 SVCC 40
O
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I Terminal Equivalent Circuits (continued)
Pin No. 41 Equivalent circuit VBAT 2.4 A
LACH SRQ
Description SCP1 : A capacitor connecting pin to set the time constant of a timer latch short circuit protection circuit at CH 1 output short circuit. Use the IC within 1 000 pF or more of capacitance. Charged current ICHG1 is 2.4 A typ.
I/O O
Output cut-off
0.3 V 41 42 SVCC 1.2 A High CH 6 operating
VREF 42 43 SVCC 1.2 A
CTL 6 : CH 6 on-off control pin. By connecting a capacitor between this pin and GND, you can make delay for a rise time. Input voltage range at on / off control by outer signal is 0 to SVCC.
I
VREF 43 44 SVCC 1.2 A
High CH 5 operating
CTL 5 : CH 5 on-off control pin. By connecting a capacitor between this pin and GND, you can make delay for a rise time. Input voltage range at on / off control by outer signal is 0 to SVCC.
I
VREF 44 45 SVCC 1.2 A
High CH 3, 4 operating
CTL 34 : CH 3, CH 4 on-off control pin. By connecting a capacitor between this pin and GND, you can make delay for a rise time. Input voltage range at on / off control by outer signal is 0 to SVCC.
I
VREF 45
High CH 2 operating
CTL 2 : CH 2 on-off control pin. By connecting a capacitor between this pin and GND, you can make delay for a rise time. Input voltage range at on / off control by outer signal is 0 to SVCC.
I
14
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I Terminal Equivalent Circuits (continued)
Pin No. 46 Equivalent circuit Description CTL 1 : On / off control pin for all CHs and CH 1. Inner circuit and CH 1 output start at VCTL1 1 V typ. Standby current at VCTL1 of off is 42 A typ. at VBAT = 3 V. Input voltage range of CTL 1 pin is 0 to VBAT. SRDV : External PNP transistor driving pin for a regulator amplifier. The sink current capability is more than 10 mA and a pull-up resistor of 200 k to SVCC is built in. SRFB : Output voltage detection input pin in regulator amplifier. There are built in 12.6 k between SRIN and SGND, 37.4 k between SRIN and SRFB and regulator output is set to 5 V. I/O I
46 20 k 10 k Inner circiut start/stop
47
SVCC
O
SRIN VREF 48 48 37.4 k SRIN 12.6 k
47
I
VREF
I Application Notes
[1] PD Ta curves of TQFP048-P-0707B PD T a
0.900 0.800 0.772 0.700 Mounted on standard board (glass epoxy: 50 mm x 50 mm x t0.8 mm) Rth(j-a) = 129.5C/W
Power dissipation PD (W)
0.600 0.500 0.400 0.399 0.300 0.200 0.100 0.000 0 25 50 75 100 125 Independent IC without a heat sink Rth(j-a) = 250.6C/W
Ambient temperature Ta (C)
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I Application Notes (continued)
[2] Usage Notes 1. CH 1 operates first and steps up input voltage to 5 V allowing a low input power operation from 1.5 V. This 5 V for CH 1 is used as supply voltage for entire IC. Since the protection circuit is designed for the above operation, you are required to refrain from using for other than the application circuit. For instance, do not use in applying the voltage directly to SVCC. 2. Power dissipation Power dissipation PD is proportionate to supply voltage and varies according to CH 1 output load, FET input capacitance of CH 1 to CH 6 and oscillation frequency, etc. On use, refer to the PD Ta curve and be careful not to exceed power dissipation of the package, according to the following equation: P = (SVCC - VBEQ1 - VOUT1 x IOUT1 x ROUT (VOUT1 - VBAT) x IOUT )x + 5 x SVCC x Ciss x f hfeQ1 x VBAT hfeQ1 x VBAT
+ SVCC x ICC + VBAT x IBAT < Pd VBEQ1 HfeQ1 ROUT Ciss f ICC IBAT : Base-emitter voltage of CH 1 NPN transistor : Current amplification ratio of CH 1 NPN transistor : Bias current limit resistance to CH 1 NPN transistor : Input capacitance of CH 2 to CH 6 output connecting FET : Oscillation frequency : SVCC, PVCC1, PVCC2 pin current : VBAT pin current
[3] Function descriptions 1. Reference voltage block The reference voltage block is constructed with a band gap circuit and it outputs temperature-compensated reference of 1.26 V typ. and of precision 1%. The reference voltage is stabilized with 4.5 V or more of supply voltage. It is also used as reference for an error amplifier 1 to 6 and the regulator amplifier as well. 2. The triangular wave generator block a) At start-up Due to the capacitor 560 pF connected to CT pin (pin 38), a triangle wave of approx. 0.76 V high, 0.69 V low and frequency of 80 kHz is generated. b) A PWM operation When SVCC potential reaches 4.1 V typ. by start of CH 1, the oscillation switches to a saw-tooth wave of approx. 0.76 V high and approx. 0.3 V low from start oscillation due to a timing capacitor and RT pin (pin 39) connection resistor. And it is connected to non-inverting input of PWM comparator IC inside. An oscillation frequency abruptly can be set 100 kHz to max. 1 MHz by the external RT pin-connected resistor.
VCTH 0.76 V VCTL 0.69 V VCTL 0.3 V t2 (dischavging) T
t1 Frequency 80 kHz Startup oscillation PWM oscillation
Figure 1-1. Triangular oscillation waveform
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I Application Notes (continued)
[3] Function descriptions (continued) 2. The triangular wave generator block (continued)
CTL 1 pin voltage
VCC low voltage protection reset voltage
Supply voltage (VCC) Battery voltage (VBAT) Internal reference voltage
Triangular wave (CT)
SS pin voltage Error amplifier output (EO)
Out pin waveform Startup oscillation operation Soft start The maximum duty
Figure 1-2. The operation from startup to PWM control
Moreover, please calculate the oscillation frequency from below equation. 4 x VRT 1.09 x 1010 f [Hz] RT x CT x (VCTH - VCTL) RT *VRT 0.7 V, CT = 560 pF, VCTH - VCTL 0.46 V As the above formula is intended to calculate the oscillation frequency of 540 kHz in the product specifications, a rapid charging time at frequency change, overshoot and undershoot amount are not considered. The calculated value in the above formula is no more than estimation. In this respect, your final confirmation better be done by using an actual product. See "Application Note [4] Characteristic curves" for the characteristics of oscillation frequency vs. RT pin resistance.
Note) When setting an oscillation frequency, never fail to set a timing capacitor connected to CT pin (pin 38) to 560 pF, and set with RT pin connecting resistor.
3. VBAT operation error prevention circuit at a low input voltage It protects the system from damage or deterioration due to operation error of control in a transient state of VBAT start or halt. From the rise of VBAT up to 1.43 V typ, set SCP 1 pin (pin 41) to 0 V and cut off the bias to a startup oscillation circuit so as to halt CH 1 output completely. 4. SVCC operation error prevention circuit at a low input voltage This circuit protects from damage or deterioration of the system due to operation error of control in an IC self bias forming and transient state by starting and halting CH 1. It also sets SCP pin (pin 37) , each SS pin (pin 12 , pin 15, pin 17, pin 20, pin22 and pin 24) and each EO pin (pin 3, pin 6, pin 9, pin 27, pin 30 and pin 35) to 0 V upto 4.1 V typ. at SVCC rise-up in order to shut down an output drive transistor or keep a halt time to 100%. CT pin (pin 38) is in a pre-oscillation state during the above-mentioned period (a triangular wave) and is switched to a normal oscillation (saw-tooth wave) in sync with the release of error prevention function (SVCC > 4.1 V) at SVCC low input voltage. At this time, each SS and EO pin is also released and moves to PWM.
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AN1149NFHK
I Application Notes (continued)
[3] Function descriptions (continued)
SVCC operation start voltage (4.1 V typ.) VBAT operation start voltage (1.43 V typ.) VBAT CT pin waveform SS pin waveform Error amplifier output (EO) SVCC
Out pin waveform
Figure 2. Low input operation error prevention timing chart at VBAT, SVCC startup
5. Error amplifier block The PNP transistor input error amplifier detects the output voltage of DC-DC converter and inputs the amplified signal to PWM comparator. Non-inverting input (reference side) of each CH except for CH 6 is set to 1.26 V of inner reference voltage. As shown in the following figures, connecting resistors and capacitors between EO pin and In-pin of each CH allows your arbitrary gain setting and phase compensation. SVCC IN-1
R1 37.4 k 12.6 k R2
CH 2 output
2 VREF 3
IN-2
To PWM Comp
(1.26 V)
4 VREF
To PWM Comp
(1.26 V)
EO 1 CH 1 FB 3 7 IN-3
R3 20.4 k 12.6 k R4
EO 2 FB 4 34 IN-4
To PWM Comp
R5
6 CH 2
12.4 k 12.6 k
8 VREF 9
33
R6
To PWM Comp
(1.26 V)
VREF 35 EO 4
(1.26 V)
EO 3 CH 3
CH 5 output
CH 4
CH 6 output
IN-5
31 VREF
To PWM Comp
(1.26 V)
IN+6 28 IN-6 29 VREF VREF EO 6 27
(1.26 V)
To PWM Comp
EO 5
30 CH 5
CH 6 (at inverting
Figure 3. Connection method of error amplifier 18
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AN1149NFHK
I Application Notes (continued)
[3] Function descriptions (continued) 5. Error amplifier block (continued) Further, CH 1, CH 3 and CH 4 have a built-in output voltage detection resistor of precision of 1% so that DCDC output can be set to 5 V, 3.3 V and 2.5 V respectively. But it is also possible to set an output voltage arbitrarily by an external resistor. When you make the output voltages of CH 1, CH 3 and CH 4 variable, it is recommended to set them by connecting the resistors as shown in the figure 4. Setting of resistance value (equation) and its approximate value can be found in the following equation: Equation to set output voltages for CH 1, CH 3 and CH 4: Output voltage = 1 +
Output voltage (SVCC, VFB3, VFB4)
(
RO1 RO2
R1 R2
RO2 + R2 RO1 + R1
)
RO1 VIN RO2
R1 R2
VIN
Figure 4. Resistor connecting diagram to set output voltage
The resistor values are selected assuming CH 1 is varied from 4.5 V to 6.0 V VIN (V) 1.26 1.26 1.26 1.26 1.26 R1 (k) 37.4 37.4 37.4 37.4 37.4 R2 (k) 12.6 12.6 12.6 12.6 12.6 RO1 (k) 23.3 26.3 29.7 33.4 37.7 RO2 (k) 10 10 10 10 10 SVCC (V) 4.50 4.75 5.00 5.25 5.50
1.26 37.4 12.6 42.4 10 5.75
IC built-in resistor
External resistor
1.26 37.4 12.6 47.8 10 6.00
The resistor values are selected assuming CH 3 is varied from 3.0 V to 3.6 V VIN (V) 1.26 1.26 1.26 1.26 1.26 R1 (k) 20.4 20.4 20.4 20.4 20.4 R2 (k) 12.6 12.6 12.6 12.6 12.6 RO1 (k) 12.4 13.6 14.8 16.2 17.7 RO2 (k) 10 10 10 10 10 VFB3 (V) 3.00 3.10 3.20 3.30 3.40
1.26 20.4 12.6 19.3 10 3.50
1.26 20.4 12.6 21 10 3.60
The resistor values are selected assuming CH 4 is varied from 1.6 V to 2.8 V VIN (V) 1.26 1.25 1.25 1.25 1.25 R1 (k) 12.4 12.4 12.4 12.4 12.4 R2 (k) 12.6 12.6 12.6 12.6 12.6 RO1 (k) 1.71 3.06 4.58 6.44 8.75 RO2 (k) 10 10 10 10 10 VFB4 (V) 1.60 1.80 2.00 2.20 2.40
1.25 12.4 12.6 11.7 10 2.60
1.25 12.4 12.6 15.6 10 2.80
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AN1149NFHK
I Application Notes (continued)
[3] Function descriptions (continued) 6. Timer latch short circuit protection circuit for CH 1 When overload or short circuit state lasts for a certain period of time, this circuit protects a main switch element, a fly-wheel diode, choke coil, etc. from damage or deterioration. This protection circuit considers CH 1 output voltage drop as output short circuit and actuates protective function. If CH 1 output voltage (SVCC) lowers down to 3.9 V typ. or less, a timer circuit is actuated by output inversion of short circuit detection comparator, and the protection-enable capacitor attached at SCP 1 pin (pin 41) starts recharging. Unless CH 1 output (SVCC) returns to the normal voltage range (SVCC > 4.3 V) by the time when a capacitor voltage reaches 0.3 V, a latch circuit is set, shuts down the output drive transistor and makes halt time 100%. As this short circuit protection circuit works in short circuit of CH 1 output i.e. that of SVCC, if it works, CH 2 to CH 6 all also halt. Short circuit protection can be released by either of the following two ways: 1. Once lower VBAT potential down to under-limit threshold voltage or less of VBAT low voltage protection circuit and then reset. 2. Bring CTL 1 to Low and then reset.
Note) It is regarded as output short-circuit at power on and SCP 1 pin voltage starts recharging. Therefore, it is necessary to set the SCP 1 pin capacitance so that output voltage of DC-DC converter may be actuated before IC sets a short circuit detection latch circuit.
DC-DC output start time < Timer latch time
SVCC
Circuit operation stop voltage (3.9 V typ.) Short circuit detection
SS 1 pin voltage Error amplifier output (EO 1)
Out 1 pin waveform
0.3 V
SCP 1 pin waveform Timer Tscp1
Figure 5. CH 1 output short circuit protect operation
Equation for timer: Cscp1 x 0.3 Cscp1 x 106 = [sec] Tscp1 = 2.4 A 8
* Cscp1 : capacitor connected to SCP 1 pin
20
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AN1149NFHK
I Application Notes (continued)
[3] Function descriptions (continued) 7. Timer latch short circuit protection circuit for CH 2 to CH 6 This circuit protects the external main switch element, fly-wheel diode and choke coil from damage or degradation caused when over load or short circuit of each channel lasts for a certain period. This protection circuit can detect short circuit by the output signal from each error amplifier. When an output voltage of DC-DC converter is lowered and any pin (EO 2 to EO 6 pin) of pin 6, pin 9, pin 27, pin 30 and pin 35 becomes 1.26 V or more, a time circuit starts to work due to an output voltage inversion of a short circuit detection comparator, and a protection-enable capacitor attached to SCP pin (pin 37) starts re-charging. If an output of error amplifier does not return to a normal voltage until this capacitor voltage reaches 0.9 V , a halt period is set to 100% by setting a latch circuit and shutting down an output drive transistor. This short circuit protection circuit will stop all CH operations including CH 1 when one of CH 2 to CH 6 short-circuits. Meanwhile, a short-circuit protection can be released in either of the following two methods: 1. Once lower VBAT potential down to under-limit threshold voltage or less of VBAT low voltage protection circuit and then reset. 2. Bring CTL 1 to Low and then reset.
Note) It is regarded as output short-circuit at power on and SCP 1 pin voltage starts recharging. Therefore, it is necessary to set the SCP 1 pin capacitance so that output voltage of DC-DC converter may be actuated before IC sets a short circuit detection latch circuit. Note that a startup time will be delayed especially for a soft start.
Output voltage 0V SS pin voltage Error amplifier output
Out pin waveform 0.9 V SCP pin waveform Timer Tscp
Figure 6. CH 2 to CH 6 output short circuit protect operation
Equation for timer: Cscp x 0.9 Tscp = = 0.75 Cscp x 106 1.2 A
[sec]
* Cscp : capacitor connected to SCP pin
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AN1149NFHK
I Application Notes (continued)
[3] Function descriptions (continued) 8. PWM comparator block A PWM comparator controls the on period of output pulse according to an input voltage. The saw-tooth wave of a CT pin turns on the output transistor during its lower period than SS / EO pin. A maximum duty ratio is set to 84% for CH 4 and 88% typ. for others, but if you connect a resistor between each SS pin and SGND or VREF, you can set to 0% to 100%. Further, if you connect a capacitor between each SS pin and GND, a soft start which spreads gradually the on period of output pulse at start up operation. Equation for Max-Du setting: VSS - VCTL MaxDU = x 100 [%] VCTH - VCTL
* VSS =
56.2 x RO2 x (RO1 + 43.8) [V] 100 x RO1 x RO2 + 56.2 x 43.8 x (RO1 + RO2)
*VCTH = 0.76 V, VCTL = 0.3 V Equation for soft start setting: TSS = CSS x 56.2k x 1n
(
1 VDTC 1- VSS
)
*VSS 0.7 V, VDTC : SS pin voltage after TSS time
CT pin waveform Out pin waveform
RO1 SS CSS RO2
43.8 k
43.8 k
Soft start time: TSS
Figure 7. Soft start operation
9. CH 1 output block a) At startup At start up time, a driving current is supplied by PNP transistor at output on, and output Tr. is turned off by the built-in resistor 15 k at output off, as shown right figures. An output source current at the turn on is approx. 5 mA typ. and the sink current is determined by a baseemitter voltage (VBE) of SWTr. and the built-in resistor 15 k. As mentioned above, both output sink and source currents are small. In this respect, you are required to use a bipolar transistor for an external SW element so that CH 1 output load current may be lower than the current found by the following equation. IO = hfe x IST
Figure 8. Output DU and soft start setting
VBAT
SVCC1
13 OSC 15 k
a) at start-up
13
b) at PWM control
Figure 9. CH 1 output drive form
IO : CH 1 output load current at startup hfe : Current amplification ratio of an external SW element IST : Output sink or source current at startup whichever langer.
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IC built-in resistor
SS pin waveform
VREF
40
AN1149NFHK
I Application Notes (continued)
[3] Function descriptions (continued) 9. CH 1 output block (continued) b) At PWM control At the time of PWM control, CH 1 output is switched to a totem pole type as shown in the figure 3. Output sink or source current is approximately 20 mA typ. 10. CH 2 to CH 6 output block All the output circuits are of a totem pole type. A sink or source current is maximum 100 mA and a peak current is maximum 0.4 A, enabling you to operate directly MOSFET as an external SW element. Further, for CH 3, you can select either N-channel or P-channel for an external SW element by setting UDSW (pin 36). * CH 2, CH 5 and CH 6 are set to N-channel driving and CH 4 to P-channel driving.
Note) Output high voltage for CH 3 and CH 4 is VCC - 1 V (max.). Be careful of selecting a threshold voltage value of P-channel MOS when using CH 3 and CH 4 SW elements of the P-channel.
11. CTL block This functions as on / off for each CH and enables you to run a sequence control as shown in the figure 10.
Note) 1. Since CH 1 output is used as a bias (SVCC) of IC, you cannot operate on / off of other CHs as long as CH 1 (CTL 1) is not driven. 2. CH 3 and CH 4 are commonly controlled by CTL 34 (pin 44). When you do not use either CH 3 or CH 4, use the IC in the state that there are no oscillations at output by short-circuiting SS or EO pin of the unused CH to GND. 3. Abrupt rise of CTL-1 pin voltage likely causes operation error. After connecting a resistor and a capacitor to CTL-1 pin, use the rise of CTL-1 pin according to the slope shown below: CTL-1 rise-up slope is dv/dt < 5.5 mV/s
CTL2 CTL34
CTL5
CTL6
AN1149FHK
1.26 V
CTL 34
44
CTL 6
CTL 5
42
43
45
CTL 2
CCTL34
CCTL6
CCTL5
CCTL2
CH 2 CH 3, 4 CH 5 CH 6
CCTL2 < CCTL34 < CCTL5 < CCTL6
Stop
Start
SVCC * UVLO released
Figure 10. CTL sequence control
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AN1149NFHK
I Application Notes (continued)
[3] Function descriptions (continued) 12. Regulator amplifier block A regulator amplifier which forms a three-pin regulator by connecting an external PNP transistor to SRFB (pin 47) and SRDV (pin 48) is bult in. CH 1 output is exclusively used for a step-up circuit and you can keep the output constant by using a regulator amplifier under the conditions on which input battery voltage (VBAT) varies widely. The sink current of a regulator amplifier is 10 mA typ. and a detection resistor of 1% precision to set output voltage to 5 V is built in. Set an output voltage in the same way as for error amplifier if variable output is needed. (See the "Application Note - [3] 5.)
Note) When using a regulator amplifier, insert a resistor R1 between base and SRDV (pin 48) of an external PNP transistor to protect from a rush-in current, as shown in the figure below:
VBAT
CH 1 output
R1 13 Out 1 SVCC SRFB 32 48 47 SRDV 37.4 k 1 SRIN 40 VREF 12.6 k
Figure 11. Connection of regulator amplifier
24
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AN1149NFHK
I Application Notes (continued)
[4] Characteristic curves DU linearity characteristics (CH 1)
100 100
DU linearity characteristics (CH 2)
80
80
60
60
DU (%)
40
DU (%)
40 20 20 0 0.3 0.4 0.5 0.6 0.7 0.8 0 0.3
0.4
0.5
0.6
0.7
0.8
EO 1 (V)
EO 2 (V)
DU linearity characteristics (CH 3)
100
DU linearity characteristics (CH 4)
100
80
80
60
60
DU (%)
DU (%)
40
40
20
20
0 0.3
0.4
0.5
0.6
0.7
0.8
0 0.3
0.4
0.5
0.6
0.7
0.8
EO 3 (V)
EO 4 (V)
DU linearity characteristics (CH 5)
100
100
DU linearity characteristics (CH 6)
80
80
60
60
DU (%)
40
DU (%)
40
20
20
0 0.3
0.4
0.5
0.6
0.7
0.8
0 0.3
0.4
0.5
0.6
0.7
0.8
EO 5 (V)
EO 6 (V)
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AN1149NFHK
I Application Notes (continued)
[4] Characteristic curves (continued) RT-CT (oscillation frequency) characteristics: CT = 560 (pF)
1 000
Startup oscillation frequency VBAT fluctuation at start-up
110
800
100
600
90
f (kHz)
f (kHz)
400
80
200
70
0 0 20
60
40 60 80 100 120
1
2
3
4
5
6
7
8
9
RT (k)
VBAT (V)
Normal oscillation frequency VCC fluctuation
590 580 570
Oscillator frequency temperature characteristics
560
550
540
560
f (kHz)
f (kHz)
550 540 530
530
520
510
520 510 4 5 6 7 8 9
500 -50
0
50
100
150
VCC (V)
Ta (C)
Duty ratio temperature characteristics
94
VREF temperature characteristics
1.272
92
1.267
90
88 Other 86 CH 4 84
VREF (V)
100 150
DU (%)
1.262
1.257
1.252
82 -50
0
50
1.247 -50
0
50
100
150
Ta (C)
Ta (C)
26
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AN1149NFHK
I Application Circuit Examples
* Application circuit examples. VBAT : JIS SUM-3 dry battery (2 units), 1.5 V to 3.6 V
VO6-2 (-30 V)
VO6-1
VO5-1
VO5-2
(15 V)
(12 V)
VO4 (2.5 V)
VO3 (3.3 V)
VO2
VO1 13 Out 1 SRDV (N.C.) 48
(5 V)
23 Out 6
21 Out 5
19 Out 4
18 Out 3
16 Out 2
24 SS 6
22 SS 5
20 SS 4
17 SS 3
PGND2 25 PVCC2 26 EO 6 27 IN+6 28 IN-6 29 EO 5 30 IN-5 31 SVCC 32 IN-4 33 FB 4 34 EO 4 35 UDSW 36
SCP 37 CT 38 RT 39 VREF 40 SCP 1 41 CTL 6 42 CTL 5 43 CTL 34 44 CTL 2 45 CTL 1 46 SRFB 47
15 SS 2
14 VBAT
12 SS 1 11 PGND1 10 PVCC1 9 EO 3 8 IN-3 7 FB3
AN1149NFHK
6 EO 2 5 SGND 4 IN-2 3 EO 1 2 IN-1 1 SRIN (N.C.)
SW34
SW6
SW5
SW2
VABT
SW1
(5 V)
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AN1149NFHK
I Application Circuit Examples (continued)
* Application circuit examples. VBAT : JIS SUM-3 dry battery (4 units), 3 V to 7.2 V
VO1 VO3 (3.3 V) VO2
(5 V) (5 V)
VO6-2 (-30 V)
VO6-1
VO5-2
VO5-1
L4
VO4 (2.5 V)
(15 V)
(12 V)
PGND2 25 PVCC2 26 EO 6 27 IN+6 28 IN-6 29 EO 5 30 IN-5 31 SVCC 32 IN-4 33 FB 4 34 EO 4 35 UDSW 36
13 Out 1
12 SS 1 11 PGND1 10 PVCC1 9 EO 3 8 IN-3 7 FB 3 6 EO 2 5 SGND 4 IN-2 3 EO 1 2 IN-1 1 SRIN
23 Out 6
21 Out 5
19 Out 4
18 Out 3
16 Out 2
24 SS 6
22 SS 5
20 SS 4
17 SS 3
AN1149NFHK
SCP 37
CT 38
RT 39
VREF 40
SCP 1 41
CTL 6 42
CTL 5 43
CTL 34 44
CTL 2 45
15 SS 2
SRFB 47
VABT SW1
14 VBAT
SW34
SW6
SW5
28
SDH00014BEB
SW2
CTL 1 46
SRDV 48
Request for your special attention and precautions in using the technical information and semiconductors described in this book
(1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this book and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this book is limited to showing representative characteristics and applied circuits examples of the products. It neither warrants non-infringement of intellectual property right or any other rights owned by our company or a third party, nor grants any license. (3) We are not liable for the infringement of rights owned by a third party arising out of the use of the product or technologies as described in this book. (4) The products described in this book are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: * Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. * Any applications other than the standard applications intended. (5) The products and product specifications described in this book are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (6) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage, and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (7) When using products for which damp-proof packing is required, observe the conditions (including shelf life and amount of time let standing of unsealed items) agreed upon when specification sheets are individually exchanged. (8) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of Matsushita Electric Industrial Co., Ltd.
2002 MAY

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