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HCC4029B HCF4029B
PRESETTABLE UP/DOWN COUNTER BINARY OR BCD DECADE
.MEDI .MULTI ." .BI .BCDOUTPUTSI .STANDARDI .5V,10V,AND15VPARAMETRI .I .QUI .100%TESTEDFORQUI .MEETSALLREQUI
DESCRIPTION
UM SPEED OPERATION - 8MHz (typ.) @ CL = 50pF AND VDD-VSS = 10V -PACKAGE PARALLEL CLOCKING FOR SYNCHRONOUS HIGH SPEED OUTPUT RESPONSE OR RIPPLE CLOCKING FOR SLOW CLOCK INPUT RISE AND FALL TIMES PRESET ENABLE" AND INDIVIDUAL "JAM" INPUTS PROVIDED NARY OR DECADE UP/DOWN COUNTING N DECADE MODE ZED SYMMETRICAL OUTPUT CHARACTERISTICS C RATINGS NPUT CURRENT OF 100nA AT 18V AND 25C FOR HCC DEVICE ESCENT CURRENT SPECIFIED TO 20V FOR HCC DEVICE ESCENT CURRENT REMENTS OF JEDEC TENTATIVE STANDARD No. 13A, "STANDARD SPECIFICATIONS FOR DESCRIPTION OF "B" SERIES CMOS DEVICES"
EY (Plastic Package)
F (Ceramic Package)
M1 (Micro Package)
C1 (Chip Carrier)
ORDER CODES : HCC4029BF HCF4029BM1 HCF4029BEY HCF4029BC1
The HCC4029B (extended temperature range) and HCF4029B (intermediate temperature range) are monolithic integrated circuit, available in 16-lead dual in-line plastic or ceramic package and plastic micro package. The HCC/HCF4029B consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. The inputs consist of a single CLOCK, CARRY-IN (CLOCK ENABLE), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAM signals. Q1, Q2, Q3, Q4 and a CARRY OUT signal are provided as outputs. A high PRESET ENABLE signal allows information on the JAM INPUTS to preset the counter to any state asynchronously with the clock. A low on each JAM line, when the PRESET-ENABLE signal is high, resets the counter to its zero count. The counter is advanced one count at the positive transition of the clock when the CARRY-IN and PRESET ENABLE signals, are low. Advancement is inhibited when the CARRY-IN or PRESET ENABLE signals are high. The CARRYOUT signal is normally high and goes low when the
PIN CONNECTIONS
NC = No Internal Connection
September 1988
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HCC/HCF4029B
counter reaches its maximum count in the UP mode or the minimum count in the DOWN mode provided the CARRY-IN signal is low. The CARRY-IN signal in the low state can thus be considered a CLOCK ENABLE. The CARRY-IN terminal must be connected to VSS whennot in use. Binary counting is accomplished when the BINARY/DECADE input is high ; the counter counts in the decade mode when the BINARY/DECADE input is low. The counter FUNCTIONAL DIAGRAM counts Up when to UP/DOWN INPUT is high, and Down when the UP/DOWN INPUT is low. Multiple packages can be connected in either a parallelclocking or a ripple-clocking arrangement as shown in cascading counter packages. Parallel clocking provides synchronous control and hence faster response from all counting outputs. Ripple-clocking allows for longer clock input rise and fall times.
ABSOLUTE MAXIMUM RATING
Symbol VDD * Vi II Ptot Parameter Supply Voltage: HCC Types HCF Types Input Voltage DC Input Current (any one input) Total Power Dissipation (per package) Dissipation per Output Transistor for Top = Full Package Temperature Range Operating Temperature: HCC Types HCF Types Storage Temperature Value -0.5 to +20 -0.5 to +18 -0.5 to VDD + 0.5 10 200 100 -55 to +125 -40 to +85 -65 to +150 Unit V V V mA mW mW
o o o
Top Tstg
C C C
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress ratingonly and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for external periods may affect device reliability. All voltage values are referred to VSS pin voltage.
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HCC/HCF4029B
RECOMMENDED OPERATING CONDITIONS
Symbol VDD VI Top Parameter Supply Voltage: HCC Types HCF Types Input Voltage Operating Temperature: HCC Types HCF Types Value 3 to 18 3 to 15 0 to VDD -55 to +125 -40 to +85 Unit V V V
o o
C C
LOGIC DIAGRAMS
TRUTH TABLES
CLOCK X X TE X O X I X
X DON'T CARE
PE O I O I I
J O X I X X
Q O Q I Q Q
Q I Q O Q NC Q NC
Control Input BIN/DEC (B/D) UP/DOWN (U/D) Preset Enable (PE)
Logic Level I O I O I O I
Action Binary Count Decade Count Up Count Down Count Jam In No Jam No Counter Advance at Pos. Clock Transition Advance Counter at Pos. Clock Transition
Carry In (Cl) (Clock Enable) O
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HCC/HCF4029B
TIMING DIAGRAMS Binary Mode
Decade Mode
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HCC/HCF4029B
STATIC ELECTRICAL CHARACTERISTICS (over recommended operating conditions)
Test Conditios Symbol IL Parameter Quiescent Current VI (V) 0/5 HCC Types 0/10 0/15 0/20 HCF Types V OH Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Output Drive Current 0/5 HCC Types 0/5 0/10 0/15 0/5 HCF Types 0/5 0/10 0/15 IOL Output Sink Current HCC Types HCF Types IIH, IIL Input Leakage Current HCC Types HCF Types Input Capacitance 0/5 0/10 0/15 0/5 0/10 0/15 0/18 Any Input 0/15 Any Input 15 0.3 10 5
-5
Value TLOW * Min. Max. 5 10 20 100 20 40 80 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 -2 -0.64 -1.6 -4.2 -1.53 -0.52 -1.3 -3.6 0.64 1.6 4.2 0.52 1.3 3.6 0.1 -1.6 -0.51 -1.3 -3.4 -1.36 -0.44 -1.1 -3.0 0.51 1.3 3.4 0.44 1.1 3.0 -3.2 -1 -2.6 -6.8 -3.2 -1 -2.6 -6.8 1 2.6 6.8 1 2.6 6.8 10-5 0.1 0.3 7.5 3.5 7 11 1.5 3 4 -1.15 -0.36 -0.9 -2.4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 0.36 0.9 2.4 1 1 pF A mA mA 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 V V 25 oC Min. Typ. Max. 0.04 0.04 0.04 0.08 0.04 0.04 0.04 5 10 20 100 20 40 80 4.95 9.95 14.95 0.05 0.05 0.05 V V THIGH * Min. Max. 150 300 600 3000 150 300 600 A Unit
VO (V)
|IO| VDD (A) (V) 5 10 15 20 5 10 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 15 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 5 10 15 5 10 15 5 10 15 18
0/5 0/10 0/15 0/5 0/10 0/15 5/0 10/0 15/0 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 0.4 0.5 1.5
VOL
VIH
V IL
IOH
CI
* TLOW = -55 oC for HCC device: -40 oC for HCF device. * THIGH = +125 oC for HCC device: +85 oC for HCF device. The Noise Margin for both "1" and "0" level is: 1V min. with VDD = 5 V, 2 V min. with VDD = 10 V, 2.5 V min. with VDD = 15 V
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HCC/HCF4029B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25 o C, C L = 50 pF, RL = 200 K, o typical temperature coefficent for all VDD values is 03 %/ C, all input rise and fall times= 20 ns)
Symbol tPLH tPHL tPLH tPHL tTLH tTHL tW Parameter Propagation Delay Time (Q Outputs) Test Conditions VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Min. Value Typ. 250 120 90 280 130 95 100 50 40 90 45 30 Max. 500 240 180 560 260 190 200 100 80 180 90 60 15 15 15 60 20 12 340 140 100 Unit ns
Propagation Delay Time (Carry Output)
ns
Transition Time (Q Outputs, Carry Output)
ns
Minimum Clock Pulse Width
ns
tr, tf **
Clock Rise and Fall Time
s
tsetup *
Minimum Setup Time (Carry Input)
tsetup
Minimum Setup Time (B/D or UD)
fmax
Maximum Clock Input Frequency
2 4 5.5
30 10 6 170 70 50 4 8 11 235 100 80 320 145 105 65 35 25 100 55 40 170 70 50 25 15 12 100 35 30
ns
MHz
PRESET ENABLE Propagation Delay Time (Q Outputs) tPLH tPHL tPLH tPHL tW Propagation Delay Time (Carry Output)
Minimum Preset Enable (Pulse Width)
trem *
Minimum Preset Enable (Removal Time)
470 200 160 640 290 210 130 70 50 200 110 80 340 140 100 50 30 25 200 70 60
ns
ns
ns
CARRY INPUT Propagation Delay Time (Carry Output) tPHL tPLH tsetup *** Minimum Setup Time (Carry In)
ns
ns
thold
Minimum Hold Time (Carry In)
* From Up/Down, Binary/Decade, Carry In or Preset Enable Control Inputs to Clock Edge ** If more than one unit is cascated in the parallel clocked application tr should be made less than or equal to the sum of the fixed propagation delay at 15 pF and the transition time of the carry output driving stage for the estimated capacitance load. *** From Carry in to Clock Edge.
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HCC/HCF4029B
Typical Output Low (sink) Current Characteristics. Minimum Output Low (sink) Current Charac-
Typical Output High (source) Current Characteristics.
Minimum Output High (source) Current Characteristics.
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HCC/HCF4029B
APPLICATIONS Conversion of Clock up, Clock Down Input Signals to Clock and Up/Down Inputs Signals. The HCC/HCF4029B CLOCK and UP/DOWN inputs are used directly in most applications. In applications where CLOCK UP and CLOCK DOWN inputs are provided, conversion to the HCC/HCF4029B CLOCK and UP/DOWN inputs can easily be realized by use of the circuit. HCC/HCF4029B changes count on positive transitions of CLOCK UP or CLOCK DOWN inputs. For the gate configuration shown below, when counting up the CLOCK DOWN input must be maintained high and conversely when counting down the CLOCK UP input must be maintained high.
Cascading Counter Packages.
*
CARRY-OUT lines at the 2nd, 3rd, et., stages may have a negative-going glitch pulse resulting from differential delays of different HCC/HCF4029B IC's. These negative-going glitches do not affect proper HCC/HCF4029B operation. However, if the CARRY-OUT signals are used to trigger other edge-sensitive logic devices, such as FF's or counters, the CARRY-OUT signals should be gated with the clock signal using a 2-input NOR gate such as HCC/HCF4001B.
Ripple Clocking Mode : The Up/Down control can be changed at any count. The only restriction on changing the Up/Down control is that the clock input to the first counting stage must be high.
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HCC/HCF4029B
Plastic DIP16 (0.25) MECHANICAL DATA
mm MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP. MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 inch TYP. MAX.
DIM.
P001C
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HCC/HCF4029B
Ceramic DIP16/1 MECHANICAL DATA
mm MIN. A B D E e3 F G H L M N P Q 7.8 2.29 0.4 1.17 0.22 0.51 0.38 17.78 2.79 0.55 1.52 0.31 1.27 10.3 8.05 5.08 0.307 0.090 0.016 0.046 0.009 0.020 3.3 0.015 0.700 0.110 0.022 0.060 0.012 0.050 0.406 0.317 0.200 TYP. MAX. 20 7 0.130 MIN. inch TYP. MAX. 0.787 0.276
DIM.
P053D
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HCC/HCF4029B
SO16 (Narrow) MECHANICAL DATA
DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm TYP. MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.004 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010
P013H
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HCC/HCF4029B
PLCC20 MECHANICAL DATA
mm MIN. A B D d1 d2 E e e3 F G M M1 1.27 1.14 7.37 1.27 5.08 0.38 0.101 0.050 0.045 9.78 8.89 4.2 2.54 0.56 8.38 0.290 0.050 0.200 0.015 0.004 TYP. MAX. 10.03 9.04 4.57 MIN. 0.385 0.350 0.165 0.100 0.022 0.330 inch TYP. MAX. 0.395 0.356 0.180
DIM.
P027A
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HCC/HCF4029B
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics. (c) 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A
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