View K4S283232E_294078.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

K4S283232E-T
CMOS SDRAM
4Mx32 SDRAM E-die TSOP
Revision 1.0 May. 2003
Rev. 1.0 May. 2003
K4S283232E-T
Revision History
Revision 1.0 (May 14. 2003)
* First spec release.
CMOS SDRAM
Rev. 1.0 May. 2003
K4S283232E-T
1M x 32Bit x 4 Banks SDRAM in 86TSOP2
FEATURES
*. 3.3V power supply * LVTTL compatible with multiplexed address * Four banks operation * MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) * All inputs are sampled at the positive going edge of the system clock *. Burst read single-bit write operation * DQM for masking *. Auto & self refresh *. 64ms refresh period (4K cycle). *. 86TSOP2.
CMOS SDRAM
GENERAL DESCRIPTION
The K4S283232E is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications.
ORDERING INFORMATION
Part No. K4S283232E-TC/L60 K4S283232E-TC/L75 K4S283232E-TC/L1L Max Freq. Interface Package 166MHz(CL=3) 133MHz(CL=3) LVTTL 86TSOP2 100MHz(CL=3)
FUNCTIONAL BLOCK DIAGRAM
I/O Control LWE LDQM
Data Input Register
Bank Select 1M x 32 Sense AMP 1M x 32 1M x 32 1M x 32 Refresh Counter
Output Buffer
Row Decoder
Row Buffer
DQi
Address Register
CLK ADD
Column Decoder Col. Buffer Latency & Burst Length
LRAS
LCBR
LCKE LRAS LCBR LWE LCAS Timing Register
Programming Register LWCBR
CLK
CKE
CS
RAS
CAS
WE
DQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.0 May. 2003
K4S283232E-T
PIN CONFIGURATION (Top view)
CMOS SDRAM
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 N.C VDD DQM0 WE CAS RAS CS A11 BA0 BA1 A10/AP A0 A1 A2 DQM2 VDD N.C DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 N.C VSS DQM1 N.C N.C CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS N.C DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26 DQ25 VSSQ DQ24 VSS
86Pin TSOP (II) (400mil x 875mil) (0.5 mm Pin pitch)
Rev. 1.0 May. 2003
K4S283232E-T
PIN FUNCTION DESCRIPTION
Pin CLK CS Name System clock Chip select Input Function Active on the positive going edge to sample all inputs.
CMOS SDRAM
Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA7 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device.
CKE
Clock enable
A0 ~ A11
Address
BA0 ~ BA1
Bank select address
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
DQM DQ0 ~ 31 VDD/VSS VDDQ/VSSQ
Data input/output mask Data input/output Power supply/ground Data output power/ground No connection /reserved for future use
N.C/RFU
Rev. 1.0 May. 2003
K4S283232E-T
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1 50
CMOS SDRAM
Unit V V C W mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA =0 to 70C) Parameter Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Symbol VDD VDDQ VIH VIL VOH VOL ILI Min 3.0 3.0 2.0 -0.3 2.4 -10 Typ 3.3 3.3 3.0 0 Max 3.6 3.6 VDD+0.3 0.8 0.4 10 Unit V V V V V V uA 1 2 IOH = -2mA IOL = 2mA 3 Note
Note : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include HI-Z output leakage for all bi-directional buffers with tri-state outputs. 4. Dout is disabled, 0V VOUT VDDQ.
CAPACITANCE
Clock
(VDD = 3.3V, TA = 23C, f = 1MHz, VREF =0.9V 50 mV) Pin Symbol CCLK CIN CADD COUT Min Max 4.0 4.0 4.0 6.0 Unit pF pF pF pF Note
RAS, CAS, WE, CS, CKE, DQM0~ DQM3 Address(A0 ~ A11, BA0 ~ BA1) DQ0 ~ DQ31
Rev. 1.0 May. 2003
K4S283232E-T
DC CHARACTERISTICS
Recommended operating conditions(Voltage referenced to VSS = 0V, TA = 0 to 70C) Parameter Symbol Burst length = 1 tRC tRC(min) IO = 0 mA CKE VIL(max), tCC = 10ns Test Condition -60 Operating Current (One Bank Active) Precharge Standby Current in power-down mode ICC1 ICC2P 110 Version -75 95 1 1 12
CMOS SDRAM
Unit -1L 90 mA
Note
1
ICC2PS CKE & CLK VIL(max), tCC = ICC2N CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 10ns
mA
Precharge Standby Current in non power-down mode ICC2NS Active Standby Current in power-down mode Active Standby Current in non power-down mode (One Bank Active) ICC3P
mA 7 4 4 25 25 mA mA
ICC3PS CKE & CLK VIL(max), tCC = ICC3N ICC3NS CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IO = 0 mA Page burst 4Banks Activated tCCD = 2CLKs tRC tRC(min) CKE 0.2V C L 800
mA
Operating Current (Burst Mode) Refresh Current Self Refresh Current
ICC4
120
95
90
mA
1
ICC5 ICC6
200
180 2 800
150
mA mA
2
800
uA
Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)
Rev. 1.0 May. 2003
K4S283232E-T
AC OPERATING TEST CONDITIONS (VDD = 3.0V ~ 3.6V, TA = 0 to 70C)
Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition
3.0V
CMOS SDRAM
Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2
Vtt = 1.4V
Unit V V ns V
1200 Output 870 VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA 50pF Output Z0 = 50
50
50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data Symbol - 60 tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 CAS latency=2 60 12 18 18 42 Version - 75 15 20 20 45 100 65 2 tRDL + tRP 1 1 1 2 1 84 -1L 20 24 24 60 ns ns ns ns us ns CLK CLK CLK CLK ea 1 2 3 2 2 4 5 1 1 1 1 Unit Note
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. Minimum 2CLK tDAL is required to complete row precharge. 4. All parts allow every cycle column address change. 5. In case of row precharge interrupt, auto precharge and read burst stop.
Rev. 1.0 May. 2003
K4S283232E-T
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter CAS latency=3 CAS latency=2 CLK to valid output delay CAS latency=3 CAS latency=2 Output data hold time CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 tCH tCL tSS tSH tSLZ tSHZ tOH 2.5 2.5 2.5 2.5 2 1 1 5.4 6 tSAC Symbol Min CLK cycle time tCC 6.0 10 5.4 6 2.5 2.5 2.5 2.5 2 1 1 6 6 - 60 Max 1000 Min 7.5 10 6 6 2.5 2.5 3 3 2.5 1.5 1 - 75 Max 1000 Min 10 12
CMOS SDRAM
-1L Max 1000 ns 1
Unit
Note
6 6
ns
1,2
ns
2
ns ns ns ns ns 6 6 ns
3 3 3 3 2
Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Rev. 1.0 May. 2003
K4S283232E-T
SIMPLIFIED TRUTH TABLE
COMMAND Register Mode Register Set Auto Refresh Refresh Entry Self Refresh Exit
CKEn-1 CKEn CS RAS CAS WE DQM BA0,1
CMOS SDRAM
A10/AP A11, A9 ~ A0 Note
H H
X H L H X X
L L L H L L
L L H X L H
L L H X H L
L H H X H H
X X
OP CODE X
1, 2 3 3 3 3
L H H
X X X V V
X Row Address L H L H X V X L H X
Column Address (A0~A7) Column Address (A0~A7)
Bank Active & Row Addr. Read & Column Address Write & Column Address Burst Stop Precharge Bank Selection All Banks Entry Exit Entry Precharge Power Down Mode Exit DQM No Operation Command Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable
4 4, 5 4 4, 5 6
H H H
X X X
L L L H L X H L H L
H H L X V X X H X V X
L H H X V X X H X V
L L L X V X X H X V
X X X
V
Clock Suspend or Active Power Down
H L H
L H L
X X X
X
X X V X X 7
L H H
H
X
H L
X H
X H
X H
X
(V=Valid, X=Dont Care, H=Logic High, L=Logic Low) Note : 1. OP Code : Operand Code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency is 0), but in read operation it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).
Rev. 1.0 May. 2003
DEVICE OPERATIONS
A. MODE REGISTER FIELD TABLE TO PROGRAM MODES
CMOS SDRAM
Register Programmed with Normal MRS
Address Function BA0 ~ BA1*1 "0" Setting for Normal MRS A11 ~ A10/AP RFU A9 W.B.L A8 A7 A6 A5 CAS Latency A4 A3 BT A2 A1 Burst Length A0
Test Mode
Normal MRS Mode
Test Mode A8 0 0 1 1 A7 0 1 0 1 Type Mode Register Set Reserved Reserved Reserved A6 0 0 0 0 1 1 1 1 CAS Latency A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Latency Reserved 1 2 3 Reserved Reserved Reserved Reserved 0 0 Setting for Normal MRS A3 0 1 Burst Type Type Sequential Interleave Mode Select BA1 BA0 Mode A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 Burst Length A0 0 1 0 1 0 1 0 1 BT=0 1 2 4 8 BT=1 1 2 4 8
Write Burst Length A9 0 1 Length Burst Single Bit
Reserved Reserved Reserved Reserved Reserved Reserved Full Page Reserved
Full Page Length : 256(x32)
B. Power Up Sequence
1. Apply power and start clock, Attempt to maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs. 2. Power is applied to VDD and VDDQ (simultaneously). 3. Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 4. Issue precharge commands for all banks of the devices. 5. Issue 2 or more auto-refresh commands. 6. Issue a mode register set command to initialize the mode register.
Note : 1. In order to assert normal MRS, BA0 and BA1 should set "0" absolutely.
ELECTRONICS

▲Up To Search▲

Price & Availability of K4S283232E

	To Download K4S283232E Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .