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L6227
DMOS DUAL FULL BRIDGE DRIVER WITH PWM CURRENT CONTROLLER
s s s s s s s s s s s
OPERATING SUPPLY VOLTAGE FROM 8 TO 52V 2.8A OUTPUT PEAK CURRENT (1.4A DC) RDS(ON) 0.73 TYP. VALUE @ Tj = 25 C OPERATING FREQUENCY UP TO 100KHz NON DISSIPATIVE OVERCURRENT PROTECTION DUAL INDEPENDENT CONSTANT tOFF PWM CURRENT CONTROLLERS SLOW DECAY SYNCHRONOUS RECTIFICATION CROSS CONDUCTION PROTECTION THERMAL SHUTDOWN UNDER VOLTAGE LOCKOUT INTEGRATED FAST FREE WHEELING DIODES
PowerDIP24 (20+2+2)
PowerSO36
SO24 (20+2+2)
ORDERING NUMBERS: L6227N (PowerDIP24) L6227PD (PowerSO36) L6227D (SO24)
TYPICAL APPLICATIONS s BIPOLAR STEPPER MOTOR s DUAL DC MOTOR DESCRIPTION The L6227 is a DMOS Dual Full Bridge designed for motor control applications, realized in MultiPowerBLOCK DIAGRAM
BCD technology, which combines isolated DMOS Power Transistors with CMOS and bipolar circuits on the same chip. The device also includes two independent constant off time PWM Current Controllers that performs the chopping regulation. Available in PowerDIP24 (20+2+2), PowerSO36 and SO24 (20+2+2) packages, the L6227 features a non-dissipative overcurrent protection on the high side Power MOSFETs and thermal shutdown.
VBOOT
VBOOT VBOOT VBOOT CHARGE PUMP OCDA OVER CURRENT DETECTION 10V 10V
VSA
VCP
OUT1A OUT2A
THERMAL PROTECTION ENA IN1A IN2A VOLTAGE REGULATOR GATE LOGIC
SENSEA
PWM ONE SHOT MONOSTABLE MASKING TIME + SENSE COMPARATOR BRIDGE A OVER CURRENT DETECTION
VSB
VREFA RCA
10V
5V
OCDB
OUT1B OUT2B SENSEB VREFB RCB BRIDGE B
ENB IN1B IN2B
GATE LOGIC
D99IN1085A
March 2003
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L6227
ABSOLUTE MAXIMUM RATINGS
Symbol VS VOD Parameter Supply Voltage Differential Voltage between VSA, OUT1A, OUT2A, SENSEA and VSB, OUT1B, OUT2B, SENSEB Bootstrap Peak Voltage Input and Enable Voltage Range Voltage Range at pins VREFA and VREFB Test conditions VSA = VSB = VS VSA = VSB = VS = 60V; VSENSEA = VSENSEB = GND VSA = VSB = VS Value 60 60 Unit V V
VBOOT VIN,VEN VREFA, VREFB
VS + 10 -0.3 to +7 -0.3 to +7 -0.3 to +7 -1 to +4
V V V V V A
VRCA, VRCB Voltage Range at pins RCA and RCB VSENSEA, VSENSEB IS(peak) Voltage Range at pins SENSEA and SENSEB Pulsed Supply Current (for each VS pin), internally limited by the overcurrent protection RMS Supply Current (for each VS pin) Storage and Operating Temperature Range VSA = VSB = VS; tPULSE < 1ms VSA = VSB = VS
3.55
IS Tstg, TOP
1.4 -40 to 150
A C
RECOMMENDED OPERATING CONDITIONS
Symbol VS VOD Parameter Supply Voltage Differential Voltage Between VSA, OUT1A, OUT2A, SENSEA and VSB, OUT1B, OUT2B, SENSEB Voltage Range at pins VREFA and VREFB Voltage Range at pins SENSEA and SENSEB RMS Output Current Operating Junction Temperature Switching Frequency -25 (pulsed tW < trr) (DC) Test Conditions VSA = VSB = VS VSA = VSB = VS; VSENSEA = VSENSEB -0.1 -6 -1 MIN 8 MAX 52 52 Unit V V
VREFA, VREFB VSENSEA, VSENSEB IOUT Tj fsw
5 6 1 1.4 +125 100
V V V A C KHz
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L6227
THERMAL DATA
Symbol Rth-j-pins Rth-j-case Rth-j-amb1 Rth-j-amb1 Rth-j-amb1 Rth-j-amb2
(1) (2) (3) (4)
Description Maximum Thermal Resistance Junction-Pins Maximum Thermal Resistance Junction-Case Maximum Thermal Resistance Junction-Ambient
1
PowerDIP24 19 44 59
SO24 15 52 78
PowerSO36 2 36 16 63
Unit C/W C/W C/W C/W C/W C/W
Maximum Thermal Resistance Junction-Ambient 2 Maximum Thermal Resistance Junction-Ambient 3 Maximum Thermal Resistance Junction-Ambient 4
Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the bottom side of 6cm2 (with a thickness of 35m). Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6cm2 (with a thickness of 35m). Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6cm2 (with a thickness of 35m), 16 via holes and a ground layer. Mounted on a multi-layer FR4 PCB without any heat sinking surface on the board.
PIN CONNECTIONS (Top View)
GND N.C. N.C.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
D02IN1347
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
GND N.C. N.C. VSB OUT2B N.C. VBOOT ENB VREFB IN2B IN1B SENSEB RCB N.C. OUT1B N.C. N.C. GND
IN1A IN2A SENSEA RCA OUT1A GND GND OUT1B RCB SENSEB IN1B IN2B
1 2 3 4 5 6 7 8 9 10 11 12
D02IN1346
24 23 22 21 20 19 18 17 16 15 14 13
VREFA ENA VCP OUT2A VSA GND GND VSB OUT2B VBOOT ENB VREFB
VSA OUT2A N.C. VCP ENA VREFA IN1A IN2A SENSEA RCA N.C. OUT1A N.C. N.C. GND
PowerDIP24/SO24
PowerSO36 (5)
(5)
The slug is internally connected to pins 1,18,19 and 36 (GND pins).
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L6227
PIN DESCRIPTION
PACKAGE SO24/ PowerDIP24 PIN # 1 2 3 4 PowerSO36 PIN # 10 11 12 13 IN1A IN2A SENSEA RCA Logic input Logic input Power Supply RC Pin Bridge A Logic Input 1. Bridge A Logic Input 2. Bridge A Source Pin. This pin must be connected to Power Ground through a sensing power resistor. RC Network Pin. A parallel RC network connected between this pin and ground sets the Current Controller OFF-Time of the Bridge A. Bridge A Output 1. Signal Ground terminals. In Power DIP and SO packages, these pins are also used for heat dissipation toward the PCB. Bridge B Output 1. RC Network Pin. A parallel RC network connected between this pin and ground sets the Current Controller OFF-Time of the Bridge B. Bridge B Source Pin. This pin must be connected to Power Ground through a sensing power resistor. Bridge B Input 1 Bridge B Input 2 Bridge B Current Controller Reference Voltage. Do not leave this pin open or connect to GND. Name Type Function
5 6, 7, 18, 19 8 9
15 1, 18, 19, 36 22 24
OUT1A GND
Power Output GND
OUT1B RCB
Power Output RC Pin
10 11 12 13 14
25 26 27 28 29
SENSEB IN1B IN2B VREFB ENB
Power Supply Logic Input Logic Input Analog Input
Logic Input (6) Bridge B Enable. LOW logic level switches OFF all Power MOSFETs of Bridge B. This pin is also connected to the collector of the Overcurrent and Thermal Protection transistor to implement over current protection. If not used, it has to be connected to +5V through a resistor. Supply Voltage Power Output Power Supply Power Supply Power Output Output Bootstrap Voltage needed for driving the upper Power MOSFETs of both Bridge A and Bridge B. Bridge B Output 2. Bridge B Power Supply Voltage. It must be connected to the supply voltage together with pin VSA. Bridge A Power Supply Voltage. It must be connected to the supply voltage together with pin VSB. Bridge A Output 2. Charge Pump Oscillator Output.
15 16 17 20 21 22
30 32 33 4 5 7
VBOOT OUT2B VSB VSA OUT2A VCP
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L6227
PIN DESCRIPTION (continued)
23 8 ENA Logic Input (6) Bridge A Enable. LOW logic level switches OFF all Power MOSFETs of Bridge A. This pin is also connected to the collector of the Overcurrent and Thermal Protection transistor to implement over current protection. If not used, it has to be connected to +5V through a resistor. Analog Input Bridge A Current Controller Reference Voltage. Do not leave this pin open or connect to GND.
24
9
VREFA
(6)
Also connected at the output drain of the Over current and Thermal protection MOSFET. Therefore, it has to be driven putting in series a resistor with a value in the range of 2.2K - 47K, recommended 33K.
ELECTRICAL CHARACTERISTICS (Tamb = 25 C, Vs = 48V, unless otherwise specified)
Symbol Parameter Test Conditions Min 5.8 5 All Bridges OFF; Tj = -25C to 125C (7) Typ 6.3 5.5 5 Max 6.8 6 10 Unit V V mA C VSth(ON) Turn-on Threshold VSth(OFF) Turn-off Threshold IS Quiescent Supply Current
Tj(OFF)
Thermal Shutdown Temperature
165
Output DMOS Transistors RDS(ON) High-Side +Low-Side Switch ON Resistance Leakage Current Tj = 25 C Tj =125 C (7) IDSS EN = Low; OUT = VS EN = Low; OUT = GND Source Drain Diodes VSD trr tfr Forward ON Voltage Reverse Recovery Time Forward Recovery Time ISD = 1.4A, EN = LOW If = 1.4A 1.15 300 200 1.3 V ns ns -0.3 1.47 2.35 1.69 2.7 2 mA mA
Logic Input VIL VIH IIL IIH Vth(ON) Vth(OFF) Vth(HYS) Low level logic input voltage High level logic input voltage Low Level Logic Input Current High Level Logic Input Current Turn-on Input Threshold Turn-off Input Threshold Input Threshold Hysteresis 0.8 0.25 GND Logic Input Voltage 7V Logic Input Voltage 1.8 1.3 0.5 -0.3 2 -10 10 2.0 0.8 7 V V A A V V V
Switching Characteristics tD(on)EN Enable to out turn ON delay time (8) ILOAD =1.4A, Resistive Load 500 800 ns
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L6227
ELECTRICAL CHARACTERISTICS (continued) (Tamb = 25 C, Vs = 48V, unless otherwise specified)
Symbol tD(on)IN tRISE tD(off)EN tD(off)IN tFALL tdt fCP Parameter Input to out turn ON delay time Output rise time(8) Test Conditions ILOAD =1.4A, Resistive Load (dead time included) ILOAD =1.4A, Resistive Load 40 500 500 40 0.5 -25CEnable to out turn OFF delay time (8) ILOAD =1.4A, Resistive Load Input to out turn OFF delay time Output Fall Time (8) Dead Time Protection Charge pump frequency ILOAD =1.4A, Resistive Load ILOAD =1.4A, Resistive Load
PWM Comparator and Monostable IRCA, IRCB Source Current at pins RCA and RCB Voffset tPROP tBLANK tON(MIN) tOFF Offset Voltage on Sense Comparator Turn OFF Propagation Delay (9) Internal Blanking Time on SENSE pins Minimum On Time PWM Recirculation Time ROFF = 20K; COFF = 1nF ROFF = 100K; COFF = 1nF IBIAS Input Bias Current at pins VREFA and VREFB VRCA = VRCB = 2.5V VREFA, VREFB = 0.5V 3.5 5.5 5 500 1 2.5 13 61 10 3 mA mV ns s s s s A
Over Current Protection ISOVER ROPDR Input Supply Overcurrent Protection Threshold Open Drain ON Resistance Tj = -25C to 125C (7) I = 4mA I = 4mA; CEN < 100pF I = 4mA; CEN < 100pF 2 2.8 40 200 100 3.55 60 A ns ns
tOCD(ON) OCD Turn-on Delay Time (10) tOCD(OFF) OCD Turn-off Delay Time (10)
(7) (8) (9) (10)
Tested at 25C in a restricted range and guaranteed by characterization. See Fig. 1. Measured applying a voltage of 1V to pin SENSE and a voltage drop from 2V to 0V to pin VREF. See Fig. 2.
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L6227
Figure 1. Switching Characteristic Definition
EN
Vth(ON) Vth(OFF) t IOUT 90%
10%
D01IN1316
t tFALL tD(OFF)EN tD(ON)EN tRISE
Figure 2. Overcurrent Detection Timing Definition
IOUT ISOVER
ON BRIDGE OFF VEN 90%
10% tOCD(ON) tOCD(OFF)
D02IN1399
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L6227
CIRCUIT DESCRIPTION POWER STAGES and CHARGE PUMP The L6227 integrates two independent Power MOS Full Bridges. Each Power MOS has an Rdson = 0.73ohm (typical value @ 25C), with intrinsic fast freewheeling diode. Cross conduction protection is achieved using a dead time (td = 1s typical) between the switch off and switch on of two Power MOS in one leg of a bridge. Using N Channel Power MOS for the upper transistors in the bridge requires a gate drive voltage above the power supply voltage. The Bootstrapped (VBOOT) supply is obtained through an internal Oscillator and few external components to realize a charge pump circuit as shown in Figure 3. The oscillator output (VCP) is a square wave at 600kHz (typical) with 10V amplitude. Recommended values/part numbers for the charge pump circuit are shown in Table1. Table 1. Charge Pump External Components Values
CBOOT CP RP D1 D2 220nF 10nF 100 1N4148 1N4148
ESD PROTECTION
D01IN1329
thermal protection MOSFETs (one for the Bridge A and one for the Bridge B) are also connected to these pins. Due to these connections some care needs to be taken in driving these pins. The ENA and ENB inputs may be driven in one of two configurations as shown in figures 5 or 6. If driven by an open drain (collector) structure, a pull-up resistor REN and a capacitor CEN are connected as shown in Fig. 5. If the driver is a standard Push-Pull structure the resistor REN and the capacitor CEN are connected as shown in Fig. 6. The resistor REN should be chosen in the range from 2.2k to 47K. Recommended values for REN and CEN are respectively 33K and 10nF. More information on selecting the values is found in the Overcurrent Protection section. Figure 4. Logic Inputs Internal Structure
5V
Figure 5. ENA and ENB Pins Open Collector Driving
5V REN 5V
Figure 3. Charge Pump Circuit
VS D1 D2 RP CP VCP VBOOT VSA VSB
D01IN1328
CBOOT
OPEN COLLECTOR OUTPUT
ENA or ENB CEN
D02IN1349
Figure 6. ENA and ENB Pins Push-Pull Driving
5V
LOGIC INPUTS Pins IN1A, IN2B, IN1B and IN2B are TTL/CMOS and uC compatible logic inputs. The internal structure is shown in Fig. 4. Typical value for turn-on and turn-off thresholds are respectively Vthon = 1.8V and Vthoff = 1.3V. Pins ENA and ENB have identical input structure with the exception that the drains of the Overcurrent and
PUSH-PULL OUTPUT
REN
ENA or ENB CEN
D02IN1350
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L6227
TRUTH TABLE
INPUTS EN L H H H H IN1 X L H L H IN2 X L L H H OUT1 High Z GND Vs GND (Vs) Vs OUTPUTS OUT2 High Z GND GND (Vs) Vs Vs Disable Brake Mode (Lower Path) Forward Reverse Brake Mode (Upper Path) Description (*)
X = Don't care High Z = High Impedance Output GND (Vs) = GND during Ton, Vs during Toff (*) Valid only in case of load connected between OUT1 and OUT2 PWM CURRENT CONTROL The L6227 includes a constant off time PWM current controller for each of the two bridges. The current control circuit senses the bridge current by sensing the voltage drop across an external sense resistor connected between the source of the two lower power MOS transistors and ground, as shown in Figure 7. As the current in the load builds up the voltage across the sense resistor increases proportionally. When the voltage drop across the sense resistor becomes greater than the voltage at the reference input (VREFA or VREFB) the sense comparator triggers the monostable switching the low-side MOS off. The low-side MOS remain off for the time set by the monostable and the motor current recirculates in the upper path. When the monostable times out the bridge will again turn on. Since the internal dead time, used to prevent cross conduction in the bridge, delays the turn on of the power MOS, the effective off time is the sum of the monostable time plus the dead time. Figure 7. PWM Current Controller Simplified Schematic
VSA (or B) TO GATE LOGIC BLANKING TIME MONOSTABLE 1s FROM THE LOW-SIDE GATE DRIVERS 2H MONOSTABLE RESET 1H
5mA
Q (0) (1)
S R
BLANKER
IOUT OUT2A(or B) DRIVERS + DEAD TIME DRIVERS + DEAD TIME LOADA (or B)
5V 2.5V +
OUT1A(or B)
SENSE COMPARATOR + COMPARATOR OUTPUT RCA(or B) C R -
2L
1L
VREFA(or B) RSENSE
SENSEA(or B)
D02IN1352
Figure 8 shows the typical operating waveforms of the output current, the voltage drop across the sensing resistor, the RC pin voltage and the status of the bridge. Immediately after the low-side Power MOS turns on, a high peak current flows through the sensing resistor due to the reverse recovery of the freewheeling diodes. The L6227 provides a 1s Blanking Time tBLANK that inhibits the comparator output so that this current spike cannot prematurely re-trigger the monostable.
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L6227
Figure 8. Output Current Regulation Waveforms
IOUT VREF RSENSE tOFF tON tOFF
VSENSE VREF 0
1s tBLANK
1s tBLANK
Slow Decay
Slow Decay
VRC 5V 2.5V
tRCRISE
tRCRISE
tRCFALL 1s tDT ON
SYNCHRONOUS RECTIFICATION
D02IN1351
tRCFALL 1s tDT
OFF
B
C
D
A
B
C
D
Figure 9 shows the magnitude of the Off Time tOFF versus COFF and ROFF values. It can be approximately calculated from the equations: tRCFALL = 0.6 * ROFF * COFF tOFF = tRCFALL + tDT = 0.6 * ROFF * COFF + tDT where ROFF and COFF are the external component values and tDT is the internally generated Dead Time with: 20K ROFF 100K 0.47nF COFF 100nF tDT = 1s (typical value) Therefore: tOFF(MIN) = 6.6s tOFF(MAX) = 6ms These values allow a sufficient range of tOFF to implement the drive circuit for most motors. The capacitor value chosen for COFF also affects the Rise Time tRCRISE of the voltage at the pin RCOFF. The Rise Time tRCRISE will only be an issue if the capacitor is not completely charged before the next time the monostable is triggered. Therefore, the on time tON, which depends by motors and supply parameters, has to
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L6227
be bigger than tRCRISE for allowing a good current regulation by the PWM stage. Furthermore, the on time tON can not be smaller than the minimum on time tON(MIN).
t O N > t O N ( MIN ) = 2.5 s (typ. value) t O N > t RCRISE - t DT
tRCRISE = 600 * COFF Figure 10 shows the lower limit for the on time tON for having a good PWM current regulation capacity. It has to be said that tON is always bigger than tON(MIN) because the device imposes this condition, but it can be smaller than tRCRISE - tDT. In this last case the device continues to work but the off time tOFF is not more constant. So, small COFF value gives more flexibility for the applications (allows smaller on time and, therefore, higher switching frequency), but, the smaller is the value for COFF, the more influential will be the noises on the circuit performance.
Figure 9. tOFF versus COFF and ROFF
1 .10
4
toff [s]

R off = 100k
3
1 .10
R off = 47k R off = 20k
100
10
1 0.1 1 Coff [nF] 10 100
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L6227
Figure 10. Area where tON can vary maintaining the PWM regulation.
100
ton(min) [s]
10
1.5s (typ. value)
1 0.1
1 Coff [nF]
10
100
SLOW DECAY MODE Figure 11 shows the operation of the bridge in the Slow Decay mode. At the start of the off time, the lower power MOS is switched off and the current recirculates around the upper half of the bridge. Since the voltage across the coil is low, the current decays slowly. After the dead time the upper power MOS is operated in the synchronous rectification mode. When the monostable times out, the lower power MOS is turned on again after some delay set by the dead time to prevent cross conduction. Figure 11. Slow Decay Mode Output Stage Configurations
A) ON TIME
D01IN1336
B) 1s DEAD TIME
C) SYNCHRONOUS RECTIFICATION
D) 1s DEAD TIME
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L6227
NON-DISSIPATIVE OVERCURRENT PROTECTION The L6227 integrates an Overcurrent Detection Circuit (OCD). This circuit provides protection against a short circuit to ground or between two phases of the bridge. With this internal over current detection, the external current sense resistor normally used and its associated power dissipation are eliminated. Figure 12 shows a simplified schematic of the overcurrent detection circuit. To implement the over current detection, a sensing element that delivers a small but precise fraction of the output current is implemented with each high side power MOS. Since this current is a small fraction of the output current there is very little additional power dissipation. This current is compared with an internal reference current IREF. When the output current in one bridge reaches the detection threshold (typically 2.8A) the relative OCD comparator signals a fault condition. When a fault condition is detected, the EN pin is pulled below the turn off threshold (1.3V typical) by an internal open drain MOS with a pull down capability of 4mA. By using an external R-C on the EN pin, the off time before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs.
Figure 12. Overcurrent Protection Simplified Schematic
OUT1A POWER SENSE 1 cell I1A POWER DMOS n cells I2A POWER DMOS n cells POWER SENSE 1 cell VSA OUT2A HIGH SIDE DMOSs OF THE BRIDGE A
TO GATE LOGIC
C or LOGIC
+
OCD COMPARATOR I1A / n (I1A+I2A) / n I2A / n
+5V REN CEN ENA RDS(ON) 40 TYP.
INTERNAL OPEN-DRAIN
IREF
OVER TEMPERATURE
D02IN1353
Figure 13 shows the Overcurrent Detection operation. The Disable Time tDISABLE before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected whether by CEN and REN values and its magnitude is reported in Figure 14. The Delay Time tDELAY before turning off the bridge when an overcurrent has been detected depends only by CEN value. Its magnitude is reported in Figure 15. CEN is also used for providing immunity to pin EN against fast transient noises. Therefore the value of CEN should be chosen as big as possible according to the maximum tolerable Delay Time and the REN value should be chosen according to the desired Disable Time. The resistor REN should be chosen in the range from 2.2K to 47K. Recommended values for REN and CEN are respectively 33K and 10nF that allow obtaining 100s Disable Time.
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L6227
Figure 13. Overcurrent Protection Waveforms
IOUT ISOVER
VEN VDD Vth(ON) Vth(OFF) VEN(LOW)
ON OCD OFF ON BRIDGE OFF tOCD(ON) tEN(FALL) tD(OFF)EN tOCD(OFF) tEN(RISE) tD(ON)EN
D02IN1400
tDELAY
tDISABLE
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L6227
Figure 14. tDISABLE versus C EN and REN (VDD = 5V).
1 .10
3
REN = 47k REN = 33k
100 tdisable [us]
REN = 10k
10
REN = 3.3k REN = 2.2k
1
1
10 Cen [nF]
100
Figure 15. tDELAY versus CEN (VDD = 5V).
10
tdelay [s]
1
0.1
1
10 Cen [nF]
100
THERMAL PROTECTION In addition to the Ovecurrent Protection, the L6227 integrates a Thermal Protection for preventing the device destruction in case of junction over temperature. It works sensing the die temperature by means of a sensible element integrated in the die. The device switch-off when the junction temperature reaches 165C (typ. value) with 15C hysteresis (typ. value).
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L6227
APPLICATION INFORMATION A typical application using L6227 is shown in Fig. 16. Typical component values for the application are shown in Table 3. A high quality ceramic capacitor in the range of 100 to 200 nF should be placed between the power pins (VSA and VSB) and ground near the L6227 to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching. The capacitors connected from the ENA and ENB inputs to ground set the shut down time for the BrgidgeA and BridgeB respectively when an over current is detected (see Overcurrent Protection). The two current sensing inputs (SENSEA and SENSEB) should be connected to the sensing resistors with a trace length as short as possible in the layout. The sense resistors should be non-inductive resistors to minimize the di/dt transients across the resistor. To increase noise immunity, unused logic pins (except ENA and ENB) are best connected to 5V (High Logic Level) or GND (Low Logic Level) (see pin description). It is recommended to keep Power Ground, Signal Ground and Charge Pump Ground (low side of CBOOT capacitor) separated on PCB. Table 2. Component Values for Typical Application
C1 C2 CA CB CBOOT CP CENA CENB CREFA CREFB 100uF 100nF 1nF 1nF 220nF 10nF 10nF 10nF 68nF 68nF D1 D2 RA RB RENA RENB RP RSENSEA RSENSEB 1N4148 1N4148 39K 39K 33K 33K 100 0.6 0.6
Figure 16. Typical Application
+ VS 8-52VDC VSA C1 C2 D1 VSB 20 17 24 13 VREFA VREFB CREFA RP D2 VCP CP VBOOT SENSEA SENSEB OUT1A OUT2A LOADB OUT1B OUT2B 15 3 10 11 12 1 2 IN1B IN2B IN1A IN2A CA RCA RA CB 9 RCB RB IN1B IN2B IN1A IN2A 22 23 14 ENA ENB CENA CREFB RENA ENA RENB ENB CENB VREFA = 0-1V VREFB = 0-1V
POWER GROUND -
SIGNAL GROUND
CBOOT
RSENSEA RSENSEB LOADA
5 21 8 16
GND GND GND GND
18 19 6 7
4
D02IN1343
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L6227
OUTPUT CURRENT CAPABILITY AND IC POWER DISSIPATION In Fig. 17 and Fig. 18 are shown the approximate relation between the output current and the IC power dissipation using PWM current control driving two loads, for two different driving types: - One Full Bridge ON at a time (Fig.17) in which only one load at a time is energized. - Two Full Bridges ON at the same time (Fig.18) in which two loads at the same time are energized. For a given output current and driving type the power dissipated by the IC can be easily evaluated, in order to establish which package should be used and how large must be the on-board copper dissipating area to guarantee a safe operating junction temperature (125C maximum). Figure 17. IC Power Dissipation versus Output Current with One Full Bridge ON at a time.
ONE FULL BRIDGE ON AT A TIME
10 8 6
IA IB
I OUT
PD [W]
4 2 0
I OUT Test Conditions: Supply Voltage = 24V No PWM fSW = 3 0 kHz (slow decay)
0
0.25
0.5 0.75
1
1.25
1.5
I OUT [A]
Figure 18. IC Power Dissipation versus Output Current with Two Full Bridges ON at the same time.
TWO FULL BRIDGES ON AT THE SAME TIME
10 8 6
IA
I OUT
IB
2
PD [W ]
4 2 0
I OUT
Test Conditions: Supply Voltage = 24V
0 0.25 0.5 0.75 1 1.25 1.5
I OUT [A ]
No PWM f SW = 30 kHz (slow decay)
THERMAL MANAGEMENT In most applications the power dissipation in the IC is the main factor that sets the maximum current that can be delivered by the device in a safe operating condition. Therefore, it has to be taken into account very carefully. Besides the available space on the PCB, the right package should be chosen considering the power dissipation. Heat sinking can be achieved using copper on the PCB with proper area and thickness. Figures 20, 21 and 22 show the Junctionto-Ambient Thermal Resistance values for the PowerSO36, PowerDIP24 and SO24 packages. For instance, using a PowerSO package with copper slug soldered on a 1.5 mm copper thickness FR4 board with 6cm2 dissipating footprint (copper thickness of 35m), the Rth j-amb is about 35C/W. Fig. 19 shows mounting methods for this package. Using a multi-layer board with vias to a ground plane, thermal impedance can be reduced down to 15C/W.
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L6227
Figure 19. Mounting the PowerSO package.
Slug soldered to PCB with dissipating area
Slug soldered to PCB with dissipating area plus ground layer
Slug soldered to PCB with dissipating area plus ground layer contacted through via holes
Figure 20. PowerSO36 Junction-Ambient thermal resistance versus on-board copper area.
C / W
43
38
33
W ith o ut G ro u nd La yer
28
W ith Gro un d La yer W ith Gro un d La yer+ 16 via H o le s
23
18
On-Board Copper Area
13 1 2 3 4 5 6 7 8 9 10 11 12 13
s q. cm
Figure 21. PowerDIP24 Junction-Ambient thermal resistance versus on-board copper area.
C / W
49 48 47 46 45 44 43 42 41 40 39 1 2 3 4 5 6 7 8 9 10 11 12
s q . cm
C o p pe r Are a is o n To p S i de C o p pe r Are a is o n Bo tto m S id e
On-Board Copper Area
Figure 22. SO24 Junction-Ambient thermal resistance versus on-board copper area.
C / W 68 66 64 62 60 58 56 54 52 50 48 1 2 3 4 5 6 7 8 9 10 11 12 s q. cm
C o pp er A re a is o n T op S id e
On-Board Copper Area
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L6227
mm TYP. inch TYP.
DIM. A a1 a2 a3 b c D (1) D1 E e e3 E1 (1) E2 E3 E4 G H h L N S
MIN. 0.10 0 0.22 0.23 15.80 9.40 13.90
MAX. 3.60 0.30 3.30 0.10 0.38 0.32 16.00 9.80 14.50
MIN. 0.004 0 0.008 0.009 0.622 0.370 0.547
MAX. 0.141 0.012 0.130 0.004 0.015 0.012 0.630 0.385 0.570
OUTLINE AND MECHANICAL DATA
0.65 11.05 10.90 5.80 2.90 0 15.50 0.80 11.10 0.429 2.90 6.20 0.228 3.20 0.114 0.10 0 15.90 0.610 1.10 1.10 0.031 10(max.) 8 (max.)
0.0256 0.435 0.437 0.114 0.244 0.126 0.004 0.626 0.043 0.043
PowerSO36
(1): "D" and "E1" do not include mold flash or protrusions - Mold flash or protrusions shall not exceed 0.15mm (0.006 inch) - Critical dimensions are "a3", "E" and "G".
N
N a2 A DETAIL A e3 H lead e A a1 E DETAIL A
c DETAIL B
D a3
36 19
slug BOTTOM VIEW E3
B E2 E1 DETAIL B
0.35 Gage Plane
D1
1
1
8
-C-
S h x 45 b
0.12
M
L
SEATING PLANE G C
AB
PSO36MEC
(COPLANARITY)
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L6227
DIM. MIN. A A1 A2 B B1 c D E e E1 e1 L M 3.180 6.350 0.410 1.400 0.200 31.62 7.620 0.380
mm TYP. MAX. 4.320 0.015 3.300 0.460 1.520 0.250 31.75 0.510 1.650 0.300 31.88 8.260 2.54 6.600 7.620 3.430 0.125 6.860 0.250 0.016 0.055 0.008 1.245 0.300 MIN.
inch TYP. MAX. 0.170
OUTLINE AND MECHANICAL DATA
0.130 0.018 0.060 0.010 1.250 0.020 0.065 0.012 1.255 0.325 0.100 0.260 0.300 0.270
0.135
Powerdip 24
0 min, 15 max.
E1
A2
A
L
A1
B
B1
e
e1
D
24
13 c
1
12 M
SDIP24L
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L6227
mm DIM. MIN. A A1 B C D (1) E e H h L k ddd 10.0 0.25 0.40 2.35 0.10 0.33 0.23 15.20 7.40 1.27 10.65 0;75 1.27 0.394 0.010 0.016 TYP. MAX. 2.65 0.30 0.51 0.32 15.60 7.60 MIN. 0.093 0.004 0.013 0.009 0.598 0.291
inch TYP. MAX. 0.104 0.012 0.200 0.013 0.614 0.299 0.050 0.419 0.030 0.050 Weight: 0.60gr
OUTLINE AND MECHANICAL DATA
0 (min.), 8 (max.) 0.10 0.004
(1) "D" dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side.
SO24
0070769 C
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L6227
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
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(R)

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