View LTC3418_295719.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LTC3418 8A, 4MHz, Monolithic Synchronous Step-Down Regulator DESCRIPTIO
The LTC(R)3418 is a high efficiency, monolithic synchronous step-down DC/DC converter utilizing a constant frequency, current mode architecture. It operates from an input voltage range of 2.25V to 5.5V and provides a regulated output voltage from 0.8V to 5V while delivering up to 8A of output current. The internal synchronous power switch increases efficiency and eliminates the need for an external Schottky diode. Switching frequency is set by an external resistor or can be synchronized to an external clock. OPTI-LOOP(R) compensation allows the transient response to be optimized over a wide range of loads and output capacitors. The LTC3418 can be configured for either Burst Mode operation or forced continuous operation. Forced continuous operation reduces noise and RF interference while Burst Mode operation provides high efficiency by reducing gate charge losses at light loads. In Burst Mode operation, external control of the burst clamp level allows the output voltage ripple to be adjusted according to the requirements of the application. A tracking input in the LTC3418 allows for proper sequencing with respect to another power supply.
, LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131, 6724174.
FEATURES

High Efficiency: Up to 95% 8A Output Current 2.25V to 5.5V Input Voltage Range Low RDS(ON) Internal Switch: 35m Tracking Input to Provide Easy Supply Sequencing Programmable Frequency: 300kHz to 4MHz 0.8V 1% Reference Allows Low Output Voltage Quiescent Current: 380A Selectable Forced Continuous/Burst Mode(R) Operation with Adjustable Burst Clamp Synchronizable Switching Frequency Low Dropout Operation: 100% Duty Cycle Power Good Output Voltage Monitor Overtemperature Protected 38-Lead Low Profile (0.75mm) Thermally Enhanced QFN (5mm x 7mm) Package
APPLICATIO S

Microprocessor, DSP and Memory Supplies Distributed 2.5V, 3.3V and 5V Power Systems Automotive Applications Point of Load Regulation Notebook Computers
TYPICAL APPLICATIO
VIN 2.8V TO 5.5V
Efficiency and Power Loss vs Load Current
100 90 EFFICIENCY 100000
2.5V/8A Step-Down Regulator
CIN 100F 0.2H COUT 100F x2
SVIN TRACK PVIN RT 2.2M 30.1k SW LTC3418 PGOOD RUN/SS ITH 4.99k 820pF PGND SGND
EFFICIENCY (%)
VOUT 2.5V 8A
80 70 60 50 40 POWER LOSS
1000pF
SYNC/MODE VFB 332 1.69k 4.32k
3418 TA01a
30 20 0.01 0.1 1 LOAD CURRENT (A)
U
U
U
10000
POWER LOSS (mW)
1000
100
10 VIN = 3.3V VOUT = 2.5V 10
3418 TA01b
1
3418f
1
LTC3418
ABSOLUTE MAXIMUM RATINGS
(Note 1)
PACKAGE/ORDER INFORMATION
TOP VIEW TRACK PGND PGND PGND PGND PGND PGND
Input Supply Voltage .................................. - 0.3V to 6V ITH, RUN/SS, VFB Voltages ......................... - 0.3V to VIN SYNC/MODE Voltages ............................... - 0.3V to VIN TRACK Voltage .......................................... -0.3V to VIN SW Voltage .................................. - 0.3V to (VIN + 0.3V) Operating Ambient Temperature Range (Note 2) .............................................. - 40C to 85C Junction Temperature (Note 5) ............................. 125C Storage Temperature Range ................. -65C to 125C
38 37 36 35 34 33 32 SW 1 SW 2 PVIN 3 PVIN 4 PGOOD 5 RT 6 RUN/SS 7 SGND 8 PVIN 9 PVIN 10 SW 11 SW 12 13 14 15 16 17 18 19 PGND PGND PGND VREF PGND PGND PGND 39 31 SW 30 SW 29 PVIN 28 PVIN 27 SYNC/MODE 26 ITH 25 VFB 24 SVIN 23 PVIN 22 PVIN 21 SW 20 SW
UHF PACKAGE 38-LEAD (7mm x 5mm) PLASTIC QFN TJMAX = 125C, JA = 34C/W, JC = 1C/W EXPOSED PAD (PIN 39) IS PGND AND MUST BE SOLDERED TO PCB
ORDER PART NUMBER UH PART MARKING
LTC3418EUHF 3418
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
SYMBOL VIN VFB IFB VFB VLOADREG VTRACK ITRACK VPGOOD RPGOOD IQ PARAMETER Input Voltage Range Regulated Feedback Voltage Feedback Input Current Reference Voltage Line Regulation Output Voltage Load Regulation Tracking Voltage Offset Tracking Voltage Range TRACK Input Current Power Good Range Power Good Resistance Input DC Bias Current Active Current Shutdown
The indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 3.3V. (Note 2)
CONDITIONS 0C TA 85C (Note 3) VIN = 2.5V to 5.5V (Note 3) Measured in Servo Loop, VITH = 0.36V Measured in Servo Loop, VITH = 0.84V VTRACK = 0.4V 0 100 7.5 100 (Note 4) VFB = 0.7V, VITH = 1V VRUN = 0V 380 0.03

MIN 2.25
TYP 0.800 0.800 100 0.04 0.02 -0.02
MAX 5.5 0.808 0.816 200 0.2 0.2 -0.2 15 0.8 200 9 150 450 1.5
UNITS V V V nA %/V % % mV V nA % A A
3418f
0.792 0.784
2
U
W
U
U
WW
W
LTC3418
ELECTRICAL CHARACTERISTICS
SYMBOL fOSC fSYNC RPFET RNFET ILIMIT VUVLO VREF ILSW VRUN PARAMETER Switching Frequency Switching Frequency Range SYNC Capture Range RDS(ON) of P-Channel FET RDS(ON) of N-Channel FET Peak Current Limit Undervoltage Lockout Threshold Reference Output SW Leakage Current RUN Threshold
The indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 3.3V. (Note 2)
CONDITIONS ROSC = 69.8k (Note 6) (Note 6) ISW = 600mA ISW = - 600mA 12 1.75 1.219 VRUN = 0V, VIN = 5.5V 0.5 MIN 0.88 0.3 0.3 35 25 17 2 1.250 0.1 0.65 2.25 1.281 1 0.8 TYP 1 MAX 1.12 4 4 50 35 UNITS MHz MHz MHz m m A V V A V
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LTC3418 is guaranteed to meet performance specifications from 0oC to 70oC. Specifications over the -40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: The LTC3418 is tested in a feedback loop that adjusts VFB to achieve a specified error amplifier output voltage (ITH).
Note 4: Dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. Note 5: TJ is calculated from the ambient temperature TA and power dissipation PD as follows: LTC3418: TJ = TA + (PD)(34C/W) Note 6: This parameter is guaranteed by design and characterization.
TYPICAL PERFOR A CE CHARACTERISTICS
Internal Reference Voltage vs Temperature
0.8000 0.7995 VIN = 3.3V
45 40
REFERENCE VOLTAGE (V)
ON-RESISTANCE (m)
PFET 30 NFET 25 20 15 10 5
ON-RESISTANCE (m)
0.7990 0.7985 0.7980 0.7975 0.7970 0.7965 0.7960 -40 -20 0 20 40 60 80 TEMPERATURE (C) 100 120
3418 G07
UW
TA = 25C unless otherwise noted.
Switch On-Resistance vs Input Voltage
50 45 40 35 30 25 20 15 10 5 2.75 3.25 3.75 4.25 4.75 INPUT VOLTAGE (V) 5.25
3418 G01
On-Resistance vs Temperature
VIN = 3.3V
35
PFET NFET
0 2.25
0 -40 -20
0
20 40 60 80 TEMPERATURE (C)
100 120
3418 G02
3418f
3
LTC3418 TYPICAL PERFOR A CE CHARACTERISTICS
Switch Leakage vs Input Voltage
5.0 4.5
QUIESCENT CURRENT (A) 500 450 400 FREQUENCY (kHz) 350 300 250 200 150 100 50
4.0
LEAKAGE CURRENT (nA)
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 2.25 2.75 3.25 3.75 4.25 4.75 INPUT VOLTAGE (V) 5.25
3418 G03
NFET
PFET
Frequency vs Temperature
1100 1080 1060 FREQUENCY (kHz) FREQUENCY (kHz) 1040 1020 1000 980 960 940 920 900 -40 -20 0 20 40 60 80 TEMPERATURE (C) 100 120
3418 G06
VIN = 3.3V
EFFICIENCY (%)
Efficiency vs Load Current
100 90 80
EFFICIENCY (%)
Burst Mode OPERATION
70
EFFICIENCY (%)
60 50 40 30 20 10 VIN = 3.3V VOUT = 2.5V
FORCED CONTINUOUS
60 50 40 30 20 10 FORCED CONTINUOUS VOUT = 2.5V 0.1 1 LOAD CURRENT (A) 10
3418 G11
EFFICIENCY (%)
0 0.01
0.1 1 LOAD CURRENT (A)
4
UW
3418 G10
TA = 25C unless otherwise noted.
Quiescent Current vs Input Voltage
4500 4000 3500 3000 2500 2000 1500 1000 500 0
Frequency vs ROSC
VIN = 3.3V
0 2.5 3 4 4.5 3.5 INPUT VOLTAGE (V) 5 5.5
3418 G04
10
50
90
130 170 ROSC (k)
210
250
3418 G08
Frequency vs Input Voltage
1100 1080 1060 1040 1020 1000 980 960 940 920 900 2.25 2.75 3.25 3.75 4.25 4.75 INPUT VOLTAGE (V) 5.25
3418 G05
Efficiency and Power Loss vs Load Current
100 90 80 70 60 50 40 30 20 0.01 0.1 1 LOAD CURRENT (A) VIN = 3.3V VOUT = 2.5V 10
3418 TA01b
100000 EFFICIENCY
10000
POWER LOSS (mW)
1000 POWER LOSS 100
10
1
Efficiency vs Load Current
100 90 3.3V 80 70 5V 80 70 60 50 40 30 20 10 100 90
Efficiency vs Load Current
3.3V 5V
10
0 0.01
0 0.01
Burst Mode OPERATION VOUT = 2.5V 0.1 1 LOAD CURRENT (A) 10
3418 G12
3418f
LTC3418 TYPICAL PERFOR A CE CHARACTERISTICS
Peak Inductor Current vs Burst Clamp Voltage
12
PEAK INDUCTOR CURRENT (A)
10
VOUT/VOUT (%)
8 6 4 2 0 0 0.1 0.2 5V
3.3V 0.3 0.4 0.5 VBCLAMP (V) 0.6 0.7 0.8 -0.30 0 1 2 6 5 4 3 LOAD CURRENT (A) 7 8
Load Step Transient
OUTPUT VOLTAGE 100mV/DIV
INDUCTOR CURRENT 5A/DIV
VIN = 3.3V 40s/DIV VOUT = 2.5V LOAD STEP: 3A TO 8A
PI FU CTIO S
SW (Pins 1, 2, 11, 12, 20, 21, 30, 31): Switch Node Connection to Inductor. This pin connects to the drains of the internal main and synchronous power MOSFET switches. PVIN (Pins 3, 4, 9, 10, 22, 23, 28, 29): Power Input Supply. Decouple this pin to PGND with a capacitor. PGOOD (Pin 5): Power Good Output. Open-drain logic output that is pulled to ground when the output voltage is not within 7.5% of regulation point. RT (Pin 6): Oscillator Resistor Input. Connecting a resistor to ground from this pin sets the switching frequency. RUN/SS (Pin 7): Run Control and Soft-Start Input. Forcing this pin below 0.5V shuts down the LTC3418. In shutdown all functions are disabled drawing <1.5A of supply current. A capacitor to ground from this pin sets the ramp time to full output current. SGND (Pin 8): Signal Ground. All small-signal components and compensation components should connect to this ground, which in turn connects to PGND at one point. PGND (Pins 13, 14, 15, 17, 18, 19, 32, 33, 34, 36, 37, 38): Power Ground. Connect this pin closely to the (-) terminal of CIN and COUT. VREF (Pin 16): Reference Output. Decouple this pin with a 2.2F capacitor. SVIN (Pin 24): Signal Input Supply. Decouple this pin to SGND with a capacitor.
3418f
UW
3418 G13
TA = 25C unless otherwise noted.
Load Regulation
0 -0.05 -0.10 -0.15 -0.20 -0.25 VIN = 3.3V VOUT = 1.8V f = 1MHz
Load Step Transient
OUTPUT VOLTAGE 100mV/DIV
INDUCTOR CURRENT 5A/DIV
VIN = 3.3V 20s/DIV VOUT = 2.5V LOAD STEP: 800mA TO 8A
3418 G15
3418 G14
Burst Mode Operation
Start-Up Transient
OUTPUT VOLTAGE 100mV/DIV
OUTPUT VOLTAGE 500mV/DIV
INDUCTOR CURRENT 1A/DIV
3418 G16
INDUCTOR CURRENT 2A/DIV VIN = 3.3V VOUT = 2.5V LOAD: 200mA 20s/DIV
3418 G17
VIN = 3.3V VOUT = 2.5V LOAD: 8A
1ms/DIV
3418 G18
U
U
U
5
LTC3418
PI FU CTIO S
VFB (Pin 25): Feedback Pin. Receives the feedback voltage from a resistive divider connected across the output. ITH (Pin 26): Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. Nominal voltage range for this pin is from 0.2V to 1.4V with 0.4V corresponding to the zero-sense voltage (zero current). SYNC/MODE (Pin 27): Mode Select and External Clock Synchronization Input. To select Forced Continuous, tie to SVIN. Connecting this pin to a voltage between 0V and 1V selects Burst Mode operation with the burst clamp set to the pin voltage. TRACK (Pin 35): Voltage Tracking Input. Feedback voltage will regulate to the voltage on this pin during start-up power sequencing. Exposed Pad (Pin 39): The Exposed Pad is PGND and must be soldered to the PCB ground.
BLOCK DIAGRA
VREF
16
35
TRACK ERROR AMPLIFIER
25
VFB
0.74V
+
LOGIC 0.86V
-
NMOS CURRENT COMPARATOR
7
RUN
5
PGOOD CURRENT REVERSE COMPARATOR
RT 6 27
SYNC/MODE
6
-
RUN/SS
-
+
+
W
U
U
U
24 SVIN
8 SGND
26 ITH 3 4 SLOPE COMPENSATION RECOVERY BURST COMPARATOR BCLAMP PMOS CURRENT COMPARATOR 9
PVIN 29 28 23 22
VOLTAGE REFERENCE
10
+ -
+ -
- +
SYNC/MODE
+
SLOPE COMPENSATION 1
+ -
OSCILLATOR
SW 2 12 21 31
11 20 30
PGND 13 14 15 17 18 19 32 33 34 36 37 38
3418 BD
3418f
LTC3418
OPERATIO
Main Control Loop The LTC3418 is a monolithic, constant frequency, current mode step-down DC/DC converter. During normal operation, the internal top power switch (P-channel MOSFET) is turned on at the beginning of each clock cycle. Current in the inductor increases until the current comparator trips and turns off the top power MOSFET. The peak inductor current at which the current comparator shuts off the top power switch is controlled by the voltage on the ITH pin. The error amplifier adjusts the voltage on the ITH pin by comparing the feedback signal from a resistor divider on the VFB pin with an internal 0.8V reference. When the load current increases, it causes a reduction in the feedback voltage relative to the reference. The error amplifier raises the ITH voltage until the average inductor current matches the new load current. When the top power MOSFET shuts off, the synchronous power switch (N-channel MOSFET) turns on until either the bottom current limit is reached or the beginning of the next clock cycle. The bottom current limit is set at -8A for force continuous mode and 0A for Burst Mode operation. The operating frequency is externally set by an external resistor connected between the RT pin and ground. The practical switching frequency can range from 300kHz to 4MHz. Overvoltage and undervoltage comparators will pull the PGOOD output low if the output voltage comes out of regulation by 7.5%. In an overvoltage condition, the top power MOSFET is turned off and the bottom power MOSFET is switched on until either the overvoltage condition clears or the bottom MOSFET's current limit is reached. Forced Continuous Connecting the SYNC/MODE pin to SVIN will disable Burst Mode operation and force continuous current operation. At light loads, forced continuous mode operation is less efficient than Burst Mode operation, but may be desirable in some applications where it is necessary to keep switching harmonics out of a signal band. The output voltage ripple is minimized in this mode.
U
Burst Mode Operation Connecting the SYNC/MODE pin to a voltage in the range of 0V to 1V enables Burst Mode operation. In Burst Mode operation, the internal power MOSFETs operate intermittently at light loads. This increases efficiency by minimizing switching losses. During Burst Mode operation, the minimum peak inductor current is externally set by the voltage on the SYNC/MODE pin and the voltage on the ITH pin is monitored by the burst comparator to determine when sleep mode is enabled and disabled. When the average inductor current is greater than the load current, the voltage on the ITH pin drops. As the ITH voltage falls below 350mV, the burst comparator trips and enables sleep mode. During sleep mode, the top power MOSFET is held off while the load current is solely supplied by the output capacitor. When the output voltage drops, the top and bottom power MOSFETs begin switching to bring the output back into regulation. This process repeats at a rate that is dependent on the load demand. Pulse skipping operation can be implemented by connecting the SYNC/MODE pin to ground. This forces the burst clamp level to be at 0V. As the load current decreases, the peak inductor current will be determined by the voltage on the ITH pin until the ITH voltage drops below 400mV. At this point, the peak inductor current is determined by the minimum on-time of the current comparator. If the load demand is less than the average of the minimum on-time inductor current, switching cycles will be skipped to keep the output voltage in regulation. Frequency Synchronization The internal oscillator of the LTC3418 can by synchronized to an external clock connected to the SYNC/MODE pin. The frequency of the external clock can be in the range of 300kHz to 4MHz. For this application, the oscillator timing resistor should be chosen to correspond to a frequency that is 25% lower than the synchronization frequency. During synchronization, the burst clamp is set to 0V, and each switching cycle begins at the falling edge of the clock signal.
3418f
7
LTC3418
OPERATIO
Dropout Operation When the input supply voltage decreases toward the output voltage, the duty cycle increases toward the maximum on-time. Further reduction of the supply voltage forces the main switch to remain on for more than one cycle eventually reaching 100% duty cycle. The output voltage will then be determined by the input voltage minus the voltage drop across the internal P-channel MOSFET and the inductor. Low Supply Operation The LTC3418 is designed to operate down to an input supply voltage of 2.25V. One important consideration at low input supply voltages is that the RDS(ON) of the P-channel and N-channel power switches increases. The user should calculate the power dissipation when the LTC3418 is used at 100% duty cycle with low input voltages to ensure that thermal limits are not exceeded. Slope Compensation and Inductor Peak Current Slope compensation provides stability in constant frequency architectures by preventing subharmonic oscillations at duty cycles greater than 50%. It is accomplished internally by adding a compensating ramp to the inductor current signal. Normally, the maximum inductor peak current is reduced when slope compensation is added. In the LTC3418, however, slope compensation recovery is implemented to keep the maximum inductor peak current constant throughout the range of duty cycles. This keeps the maximum output current relatively constant regardless of duty cycle.
8
U
Short-Circuit Protection When the output is shorted to ground, the inductor current decays very slowly during a single switching cycle. To prevent current runaway from occurring, a secondary current limit is imposed on the inductor current. If the inductor valley current increases larger than 15A, the top power MOSFET will be held off and switching cycles will be skipped until the inductor current is reduced. Voltage Tracking Some microprocessors and DSP chips need two power supplies with different voltage levels. These systems often require voltage sequencing between the core power supply and the I/O power supply. Without proper sequencing, latch-up failure or excessive current draw may occur that could result in damage to the processor's I/O ports or the I/O ports of a supporting system device such as memory, an FPGA or a data converter. To ensure that the I/O loads are not driven until the core voltage is properly biased, tracking of the core supply and the I/O supply voltage is necessary. Voltage tracking is enabled by applying a ramp voltage to the TRACK pin. When the voltage on the TRACK pin is below 0.8V, the feedback voltage will regulate to this tracking voltage. When the tracking voltage exceeds 0.8V, tracking is disabled and the feedback voltage will regulate to the internal reference voltage. Voltage Reference Output The LTC3418 provides a 1.25V reference voltage that is capable of sourcing up to 5mA of output current. This reference voltage is generated from a linear regulator and is intended for applications requiring a low noise reference voltage. To ensure that the output is stable, the reference voltage pin should be decoupled with a minimum of 2.2F.
3418f
LTC3418
APPLICATIO S I FOR ATIO
The basic LTC3418 application circuit is shown on the front page of this data sheet. External component selection is determined by the maximum load current and begins with the selection of the operating frequency and inductor value followed by CIN and COUT. Operating Frequency Selection of the operating frequency is a tradeoff between efficiency and component size. High frequency operation allows the use of smaller inductor and capacitor values. Operation at lower frequencies improves efficiency by reducing internal gate charge losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. The operating frequency of the LTC3418 is determined by an external resistor that is connected between the RT pin and ground. The value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator and can be calculated by using the following equation:
ROSC =
7.3 * 1010 [] - 2.5k f
Although frequencies as high as 4MHz are possible, the minimum on-time of the LTC3418 imposes a minimum limit on the operating duty cycle. The minimum on-time is typically 80ns. Therefore, the minimum duty cycle is equal to: 100 * 80ns * f(Hz) Inductor Selection For a given input and output voltage, the inductor value and operating frequency determine the ripple current. The ripple current IL increases with higher VIN or VOUT and decreases with higher inductance: V V IL = OUT 1- OUT VIN fL
U
Having a lower ripple current reduces the core losses in the inductor, the ESR losses in the output capacitors and the output voltage ripple. Highest efficiency operation is achieved at low frequency with small ripple current. This, however, requires a large inductor. A reasonable starting point for selecting the ripple current is IL = 0.4(IMAX). The largest ripple current occurs at the highest VIN. To guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation:
W
UU
VOUT VOUT L= 1- V fIL(MAX) IN(MAX)
The inductor value will also have an effect on Burst Mode operation. The transition from low current operation begins when the peak inductor current falls below a level set by the burst clamp. Lower inductor values result in higher ripple current which causes this to occur at lower load currents. This causes a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to increase. Inductor Core Selection Once the value for L is known, the type of inductor must be selected. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on the inductance selected. As the inductance increases, core losses decrease. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates "hard," which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate!
3418f
9
LTC3418
APPLICATIO S I FOR ATIO
Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don't radiate much energy, but generally cost more than powdered iron core inductors with similar characteristics. The choice of which style inductor to use mainly depends on the price vs size requirements and any radiated field/EMI requirements. New designs for surface mount inductors are available from Coiltronics, Coilcraft, Toko and Sumida. CIN and COUT Selection The input capacitance, CIN, is needed to filter the trapezoidal wave current at the source of the top MOSFET. To prevent large voltage transients from occurring, a low ESR input capacitor sized for the maximum RMS current should be used. The maximum RMS current is given by:
IRMS = IOUT(MAX) VOUT VIN VIN -1 VOUT
This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. The selection of COUT is determined by the effective series resistance (ESR) that is required to minimize voltage ripple and load step transients as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response as described in a later section. The output ripple, VOUT, is determined by:
1 VOUT IL ESR + 8 fCOUT
The output ripple is highest at maximum input voltage since IL increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS
10
U
current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR, but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing. Using Ceramic Input and Output Capacitors Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. However, care must be taken when these capacitors are used at the input and output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part. When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. Output Voltage Programming The output voltage is set by an external resistive divider according to the following equation: R2 VOUT = 0.8 1 + R1 The resistive divider allows pin VFB to sense a fraction of the output voltage as shown in Figure 1.
3418f
W
UU
LTC3418
APPLICATIO S I FOR ATIO
VOUT R2 VFB LTC3418 SGND
3418 F01
R1
Figure 1. Setting the Output Voltage
Burst Clamp Programming If the voltage on the SYNC/MODE pin is less than VIN by 1V, Burst Mode operation is enabled. During Burst Mode operation, the voltage on the SYNC/MODE pin determines the burst clamp level, which sets the minimum peak inductor current, IBURST, for each switching cycle. A graph showing the relationship between the minimum peak inductor current and the voltage on the SYNC/MODE pin can be found in the Typical Performance Characteristics section. In the graph, VBURST is the voltage on the SYNC/ MODE pin. IBURST can only be programmed in the range of 0A to 10A. For values of VBURST less than 0.4V, IBURST is set at 0A. As the output load current drops, the peak inductor currents decrease to keep the output voltage in regulation. When the output load current demands a peak inductor current that is less than IBURST, the burst clamp will force the peak inductor current to remain equal to IBURST regardless of further reductions in the load current. Since the average inductor current is greater than the output load current, the voltage on the ITH pin will decrease. When the ITH voltage drops to 350mV, sleep mode is enabled in which both power MOSFETs are shut off and switching action is discontinued to minimize power consumption. All circuitry is turned back on and the power MOSFETs begin switching again when the output voltage drops out of regulation. The value for IBURST is determined by the desired amount of output voltage ripple. As the value of IBURST increases, the sleep period between pulses and the output voltage ripple increase. The burst clamp voltage, VBURST, can be set by a resistor divider from the VFB pin to the SGND pin as shown in the Typical Application on the front page of this data sheet. Pulse skipping, which is a compromise between low output voltage ripple and efficiency during low load current operation, can be implemented by connecting the
OUTPUT VOLTAGE
OUTPUT VOLTAGE
U
SYNC/MODE pin to ground. This sets IBURST to 0A. In this condition, the peak inductor current is limited by the minimum on-time of the current comparator; and the lowest output voltage ripple is achieved while still operating discontinuously. During very light output loads, pulse skipping allows only a few switching cycles to be skipped while maintaining the output voltage in regulation. Voltage Tracking The LTC3418 allows the user to program how its output voltage ramps during start-up by means of the TRACK pin. Through this pin, the output voltage can be set up to either track coincidentally or ratiometrically follow another output voltage as shown in Figure 2. If the voltage on the TRACK pin is less than 0.8V, voltage tracking is enabled. During voltage tracking, the output voltage regulates to the tracking voltage through a resistor divider network.
VOUT2 VOUT1 TIME
3418 F02a
W
UU
Figure 2a. Coincident Tracking
VOUT2
VOUT1
TIME
3418 F02a
Figure 2b. Ratiometric Sequencing
3418f
11
LTC3418
APPLICATIO S I FOR ATIO
The output voltage during tracking can be calculated with the following equation: R2 VOUT = VTRACK 1 + , VTRACK < 0.8 V R1 To implement the coincident tracking in Figure 2a, connect an extra resistor divider to the output of VOUT2 and connect its midpoint to the TRACK pin of the LTC3418 as shown in Figure 3a. The ratio of this divider should be selected the same as that of VOUT1's resistor divider. To implement the ratiometric sequencing in Figure 2b, no extra resistor divider is necessary. Simply connect the TRACK pin to VFB2, as shown in Figure 3b.
VOUT2 (MASTER) R2 TRACK PIN R1 R3 R4 VFB(MASTER) PIN TRACK PIN R2 VFB(MASTER) R1
3418 F03
(3a) Coincident Setup
(3b) Ratiometric Setup
Figure 3
Frequency Synchronization The LTC3418's internal oscillator can be synchronized to an external clock signal. During synchronization, the top MOSFET turn-on is locked to the falling edge of the external frequency source. The synchronization frequency range is 300kHz to 4MHz. Synchronization only occurs if the external frequency is greater than the frequency set by the external resistor. Because slope compensation is generated by the oscillator's RC circuit, the external frequency should be set 25% higher than the frequency set by the external resistor to ensure that adequate slope compensation is present. Soft-Start The RUN/SS pin provides a means to shut down the LTC3418 as well as a timer for soft-start. Pulling the RUN/ SS pin below 0.5V places the LTC3418 in a low quiescent current shutdown state (IQ < 1.5A). The LTC3418 contains a soft-start clamp that can be set externally with a resistor and capacitor on the RUN/SS pin
12
U
as shown in Typical Application on the front page of this data sheet. The soft-start duration can be calculated by using the following formula:
W
UU
tSS = RSS * CSS * In
VIN [Seconds] VIN - 1.8 V
When the voltage on the RUN/SS pin is raised above 2V, the full current range becomes available on ITH. Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as: Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses: VIN quiescent current and I2R losses. The VIN quiescent current loss dominates the efficiency loss at very low load currents whereas the I2R loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence. 1. The VIN quiescent current is due to two components: the DC bias current as given in the Electrical Characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge dQ moves from VIN to ground. The resulting dQ/dt is the current out of VIN that is typically larger than the DC bias current. In continuous mode, IGATECHG = f(QT + QB) where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias and gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages.
3418f
VOUT2 (MASTER)
LTC3418
APPLICATIO S I FOR ATIO
2. I2R losses are calculated from the resistances of the internal switches, RSW, and external inductor RL. In continuous mode the average output current flowing through inductor L is "chopped" between the main switch and the synchronous switch. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 - DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses, simply add RSW to RL and multiply the result by the square of the average output current. Other losses including CIN and COUT ESR dissipative losses and inductor core losses generally account for less than 2% of the total loss. Thermal Considerations In most applications, the LTC3418 does not dissipate much heat due to its high efficiency. But, in applications where the LTC3418 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 150C, both power switches will be turned off and the SW node will become high impedance. To avoid the LTC3418 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: TR = (PD)(JA) where PD is the power dissipated by the regulator and JA is the thermal resistance from the junction of the die to the ambient temperature. For the 38-Lead 5mm x 7mm QFN package, the JA is 34C/W.
U
The junction temperature, TJ, is given by: TJ = TA + TR where TA is the ambient temperature. Note that at higher supply voltages, the junction temperature is lower due to reduced switch resistance (RDS(ON)). Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ILOAD(ESR), where ESR is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. The ITH pin external components and output capacitor shown in the Typical Application on the front page of this data sheet will provide adequate compensation for most applications. Design Example As a design example, consider using the LTC3418 in an application with the following specifications: VIN = 3.3V, VOUT = 2.5V, IOUT(MAX) = 8A, IOUT(MIN) = 200mA, f = 1MHz. Because efficiency is important at both high and low load current, Burst Mode operation will be utilized. First, calculate the timing resistor: ROSC = 7.3 * 1010 - 2.5k = 70.5k 1 * 106 Use a standard value of 69.8k. Next, calculate the inductor value for about 40% ripple current:
2.5V 2.5V L= = 0.19H 1- (1MHz)(3.2A ) 3.3V
3418f
W
UU
13
LTC3418
APPLICATIO S I FOR ATIO
Using a 0.2H inductor results in a maximum ripple current of:
2.5V 2.5V IL = = 3.03A 1- (1MHz)(0.2H) 3.3V
COUT will be selected based on the ESR that is required to satisfy the output voltage ripple requirement and the bulk capacitance needed for loop stability. For this design, five 100F ceramic capacitors will be used. CIN should be sized for a maximum current rating of:
2.5V 3.3V - 1 = 3.43ARMS IRMS = (8 A ) 3.3V 2.5V
Decoupling the PVIN and SVIN pins with four 100F capacitors is adequate for this application. The burst clamp and output voltage can now be programmed by choosing the values of R1, R2 and R3. The voltage on the MODE pin will be set to 0.67V by the resistor
VIN 3.3V 3 CIN 100F x4 4 9 10 22 RSS 2.2M RSVIN 100 CSVIN 1F X7R RPG 100k 23 28 29 24 PVIN PVIN PVIN PVIN PVIN PVIN PVIN PVIN SVIN LTC3418 CSS 1000pF X7R 35 5 TRACK PGOOD
CITH 820pF X7R
RITH 7.5k C1 47pF X7R
7 RUN/SS 26 ITH ROSC 69.8k 6 RT 8 SGND 13 PGND 14 PGND 15 PGND 17 PGND
CIN, COUT: AVX 18126D107MAT L1: TOKO FDV0620-R20M
Figure 4. 2.5V, 8A Regulator at 1MHz, Burst Mode Operation
3418f
14
U
divider consisting of R2 and R3. A burst clamp voltage of 0.67V will set the minimum inductor current, IBURST, to approximately 1.2A. If we set the sum of R2 and R3 to 200k, then the following equations can be solved.
R2 + R3 = 200k R2 0.8 V 1+ = R3 0.67 V
W
UU
The two equations shown above result in the following values for R2 and R3: R2 = 33.2k, R3 = 169k. The value of R1 can now be determined by solving the equation:
R1 2.5V = 202.2k 0.8 V R1 = 430k 1+
A value of 432k will be selected for R1. Figure 4 shows the complete schematic for this design example.
L1 0.2H COUT 100F x5 C1 22pF X7R R1 432k
SW SW SW SW SW SW SW SW VFB
1 2 11 12 20 21 30 31 25
VOUT 2.5V 8A
SYNC/MODE PGND PGND PGND PGND PGND PGND PGND PGND VREF
27 38 37 36 34 33 32 19 18 16
R2 33.2k
R3 169k
CREF 2.2F X7R
3418 F04
VREF
LTC3418
APPLICATIO S I FOR ATIO
PC Board Layout Checklist
When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3418. Check the following in your layout. 1. A ground plane is recommended. If a ground plane layer is not used, the signal and power grounds should be segregated with all small-signal components returning to the SGND pin at one point which is then connected to the PGND pin close to the LTC3418. 2. Connect the (+) terminal of the input capacitor(s), CIN, as close as possible to the PVIN pin. This capacitor provides the AC current into the internal power MOSFETs.
Top Layer Figure 5. LTC3418 Layout Diagram
U
3. Keep the switching node, SW, away from all sensitive small-signal nodes. 4. Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power components. You can connect the copper areas to any DC net (PVIN, SVIN, VOUT, PGND, SGND or any other DC rail in your system). 5. Connect the VFB pin directly to the feedback resistors. The resistor divider must be connected between VOUT and SGND. 6. To minimize switching noise coupling to SVIN, place a local filter between SVIN and PVIN.
Bottom Layer
3418f
W
UU
15
LTC3418
TYPICAL APPLICATIO S
3.3V, 8A Step-Down Regulator Synchronized to 1.25MHz
VIN 5V 3 CIN 100F x2 4 9 10 22 RSS 2.2M RPG 100k 23 28 29 24 RSVIN 100 CSVIN 1F X7R CSS 1000pF X7R 1 2 11 12 20 21 30 31 25 C1 1000pF X7R R1 6.34k L1 0.33H COUT 100F x3 VOUT 3.3V 8A PVIN PVIN PVIN PVIN PVIN PVIN PVIN PVIN SVIN LTC3418 35 5 TRACK PGOOD VREF PGND PGND PGND PGND PGND PGND PGND PGND PGND 16 38 37 36 34 33 32 19 18 17 R2 2k CREF 2.2F X7R VREF SW SW SW SW SW SW SW SW VFB
CITH 2200pF X7R
1.2V, 8A Step-Down Regulator at 2MHz, Forced Continuous Mode
VIN 3.3V CIN 100F x4 3 4 9 10 22 RSS 2.2M RPG 100k 23 28 29 24 RSVIN 100 CSVIN 1F X7R CSS 1000pF X7R 1 2 11 12 20 21 30 31 25 C1 1000pF X7R R1 1k L1 0.2H COUT 100F x3 VOUT 1.2V 8A
CITH 2200pF X7R
CIN, COUT: AVX 12106D107MAT L1: COOPER FP3-R20
16
U
RITH 2k C1 47pF X7R
7 RUN/SS 26 ITH ROSC 69.8k 6 RT 8 SGND 13 PGND 14 PGND 15 PGND 27 SYNC/MODE
1.25MHz CLOCK
CIN, COUT: TDK C3225X5R0J107M L1: VISHAY DALE IHLP-2525CZ-01
3418 TA02
PVIN PVIN PVIN PVIN PVIN PVIN PVIN PVIN SVIN LTC3418
SW SW SW SW SW SW SW SW VFB
35 27 5 7
TRACK SYNC/MODE PGOOD
VREF PGND PGND PGND PGND PGND PGND PGND PGND PGND
16 38 37 36 34 33 32 19 18 17 R2 2k CREF 2.2F X7R
VREF
RITH 4.99k C1 47pF X7R
RUN/SS 26 ITH ROSC 30.1k 6 RT 8 SGND 14 PGND 15 PGND 13 PGND
3418 TA03
3418f
LTC3418
TYPICAL APPLICATIO S
1.8V, 8A Step-Down Regulator with Tracking
VIN 3.3V
CIN 100F x4 RSS 2.2M RPG 100k
RSVIN 100 CSVIN C SS 1F 1000pF X7R X7R
CITH 2200pF X7R
RITH 3.32k C1 47pF X7R
CIN, COUT: TDK C3225X5R0J107M L1: VISHAY DALE IHLP-2525CZ-01
U
I/O SUPPLY R4 2k 35 3 4 9 10 22 23 29 28 R3 2.55k 1 2 11 12 20 21 30 31 25
2.5V
L1 0.2H COUT 100F x2 C1 1000pF X7R R1 2.55k
TRACK PVIN PVIN PVIN PVIN PVIN PVIN PVIN PVIN LTC3418
SW SW SW SW SW SW SW SW VFB
VOUT 1.8V 8A
24 5 27 7
SVIN PGOOD SYNC/MODE RUN/SS
VREF PGND PGND PGND PGND PGND PGND PGND PGND PGND
16 38 37 36 34 33 32 19 18 17 R2 2k CREF 2.2F X7R
VREF
26 I ROSC 69.8k 6 TH RT 8 SGND 13 PGND 14 PGND 15 PGND
3418 TA04
3418f
17
LTC3418
TYPICAL APPLICATIO S
1.8V, 16A Step-Down Regulator
VIN 3.3V 3 CIN1 100F x4 4 9 10 22 RSS1 2.2M RPG1 100k 23 28 29 24 RSVIN1 100 CSVIN1 1F X7R PVIN PVIN PVIN PVIN PVIN PVIN PVIN PVIN SVIN LTC3418 CSS1 1000pF X7R 35 5 7 C1A 47pF X7R TRACK PGOOD RUN/SS PGND PGND PGND PGND PGND PGND PGND PGND PGND VREF 38 37 36 34 33 32 19 18 17 16 CREF1 2.2F X7R R2 2k COUT 100F x4 VOUT 1.8V 16A SW SW SW SW SW SW SW SW VFB 1 2 11 12 20 21 30 31 25 C2 1000pF X7R R1 2.55k L1 0.2H
CIN2 100F x4
RSVIN2 100
CSVIN2 1F X7R
CSS2 1000pF X7R
18
U
26 ITH ROSC1 59k 6 RT 8 SGND 13 PGND 14 PGND 15 PGND 27 SYNC/MODE
RITH 2k
CITH 2200pF X7R L2 0.2H
3 4 9 10 22 RSS2 2.2M RPG2 100k 23 28 29 24
PVIN PVIN PVIN PVIN PVIN PVIN PVIN PVIN SVIN LTC3418
SW SW SW SW SW SW SW SW VFB
1 2 11 12 20 21 30 31 25
C3 1000pF X7R
R3 2.55k
35 5 7
TRACK PGOOD
PGND PGND PGND PGND PGND PGND PGND PGND PGND VREF
38 37 36 34 33 32 19 18 17 16 CREF2 2.2F X7R R4 2k
C1B 47pF X7R
RUN/SS 26 ITH ROSC2 69.8k 6 RT 8 SGND 13 PGND 14 PGND 15 PGND 27 SYNC/MODE
CIN1, CIN2, COUT: TDK C3225X5R0J107M L1, L2: VISHAY DALE IHLP-2525CZ-01
3418 TA06
3418f
LTC3418
PACKAGE DESCRIPTIO
5.50 0.05 (2 SIDES) 4.10 0.05 (2 SIDES) 3.15 0.05 (2 SIDES)
5.00 0.10 (2 SIDES)
PIN 1 TOP MARK (SEE NOTE 6)
7.00 0.10 (2 SIDES)
0.75 0.05
NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE M0-220 VARIATION WHKD 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
UHF Package 38-Lead Plastic QFN (5mm x 7mm)
(Reference LTC DWG # 05-08-1701)
0.70 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC 5.20 0.05 (2 SIDES) 6.10 0.05 (2 SIDES) 7.50 0.05 (2 SIDES) RECOMMENDED SOLDER PAD LAYOUT 0.75 0.05 0.00 - 0.05 3.15 0.10 (2 SIDES) 0.435 0.18 0.18 37 38 1 2 0.23 5.15 0.10 (2 SIDES) 0.40 0.10 0.200 REF 0.25 0.05 0.200 REF 0.00 - 0.05 0.50 BSC R = 0.115 TYP
(UH) QFN 1203
BOTTOM VIEW--EXPOSED PAD
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
3418f
19
LTC3418
TYPICAL APPLICATIO
VIN 2.5V
RSVIN 100
CSVIN 1F X7R CSS 1000pF X7R
RELATED PARTS
PART NUMBER LT1616 LT1676 LT1765 LTC1879 LTC3405/LTC3405A LTC3406/LTC3406B LTC3407 LTC3411 LTC3412 LTC3413 LTC3414 LTC3416 DESCRIPTION 500mA (IOUT), 1.4MHz, High Efficiency Step-Down DC/DC Converter 450mA (IOUT), 100kHz, High Efficiency Step-Down DC/DC Converter 25V, 2.75A (IOUT), 1.25MHz, High Efficiency Step-Down DC/DC Converter 1.20A (IOUT), 550kHz, Synchronous Step-Down DC/DC Converter 300mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converter 600mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converter Dual 600mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converter 1.25A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 2.5A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 3A (IOUT Sink/source), 2MHz, Monolithic Synchronous Regulator for DDR/QDR Memory Termination 4A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 4A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter with Tracking COMMENTS 90% Efficiency, VIN: 3.6V to 25V, VOUT = 1.25V, IQ = 1.9mA, ISD < 1A, ThinSOT Package 90% Efficiency, VIN: 7.4V to 60V, VOUT = 1.24V, IQ = 3.2mA, ISD < 2.5A, S8 Package 90% Efficiency, VIN: 3V to 25V, VOUT = 1.2V, IQ = 1mA, ISD < 15A, S8, TSSOP16E Packages 95% Efficiency, VIN: 2.7V to 10V, VOUT = 0.8V, IQ = 15A, ISD < 1A, TSSOP16 Package 95% Efficiency, VIN: 2.75V to 6V, VOUT = 0.8V, IQ = 20A, ISD < 1A, ThinSOT Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT = 0.6V, IQ = 20A, ISD < 1A, ThinSOT Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT = 0.6V, IQ = 40A, ISD < 1A, MS Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT = 0.8V, IQ = 60A, ISD < 1A, MS Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT = 0.8V IQ = 60A, ISD < 1A, TSSOP16E Package 90% Efficiency, VIN: 2.25V to 5.5V, VOUT = VREF/2, IQ = 280A, ISD < 1A, TSSOP16E Package 95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 64A, ISD < 1A, TSSOP20E Package 95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 300A, ISD < 1A, TSSOP20E Package
3418f LT/TP 0205 1K * PRINTED IN THE USA
20
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
U
Low Noise 1.5V, 8A Step-Down Regulator
3 CIN 100F x4 4 9 10 22 RSS 2.2M RPG 100k 23 28 29 24 PVIN PVIN PVIN PVIN PVIN PVIN PVIN PVIN SVIN LTC3418 35 5 TRACK PGOOD VREF PGND PGND PGND PGND PGND PGND PGND PGND PGND 16 38 37 36 34 33 32 19 18 17 R2 2k CREF 2.2F X7R VREF SW SW SW SW SW SW SW SW VFB 1 2 11 12 20 21 30 31 25 C1 1000pF X7R R1 1.78k L1 0.2H COUT 100F x3 VOUT 1.5V 8A CITH 2200pF X7R RITH 3.32k C1 47pF X7R 7 RUN/SS 26 ITH ROSC 69.8k 6 RT 27 SYNC/MODE 8 SGND 13 PGND 14 PGND 15 PGND CIN, COUT: TDK C3225X5R0J107M L1: VISHAY DALE IHLP-2525CZ-01
3418 TA05
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2005

▲Up To Search▲

Price & Availability of LTC3418

	To Download LTC3418 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .